diff options
| author | Mat M <mathew1800@gmail.com> | 2016-05-18 08:32:36 -0400 |
|---|---|---|
| committer | Mat M <mathew1800@gmail.com> | 2016-05-18 08:32:36 -0400 |
| commit | 7a7488a0bb30abe41f182ed5fc66c4c9fe1a94f0 (patch) | |
| tree | 438014cb26c451bf0c97534bb767dcc7ba171d90 | |
| parent | 960297e57742be500dbd73b76b7c960cab7fa6c9 (diff) | |
| parent | 3a45eacb16d1d80dd378fc3ae7330fce351a21de (diff) | |
Merge pull request #1814 from JayFoxRox/fix-read-after-write
Fix read-after-write in SMUAD, SMLAD, SMUSD, SMLSD
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 8d4b26815..cfc67287f 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -5527,28 +5527,32 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { // SMUAD and SMLAD if (BIT(op2, 1) == 0) { - RD = (product1 + product2); + u32 rd_val = (product1 + product2); if (inst_cream->Ra != 15) { - RD += cpu->Reg[inst_cream->Ra]; + rd_val += cpu->Reg[inst_cream->Ra]; if (ARMul_AddOverflowQ(product1 + product2, cpu->Reg[inst_cream->Ra])) cpu->Cpsr |= (1 << 27); } + RD = rd_val; + if (ARMul_AddOverflowQ(product1, product2)) cpu->Cpsr |= (1 << 27); } // SMUSD and SMLSD else { - RD = (product1 - product2); + u32 rd_val = (product1 - product2); if (inst_cream->Ra != 15) { - RD += cpu->Reg[inst_cream->Ra]; + rd_val += cpu->Reg[inst_cream->Ra]; if (ARMul_AddOverflowQ(product1 - product2, cpu->Reg[inst_cream->Ra])) cpu->Cpsr |= (1 << 27); } + + RD = rd_val; } } |