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authorFernando Sahmkow <fsahmkow27@gmail.com>2020-06-19 19:40:07 -0400
committerFernando Sahmkow <fsahmkow27@gmail.com>2020-06-27 11:36:27 -0400
commit4105f38022a525aab2e7d4288f121b4f0a0dd7b2 (patch)
tree3cf68e47fcc17442111b8af16a3fff19b3f3434f /src/core/arm/dynarmic
parentce350e7ce03b8d9e3e2c8ff8774f9b929a70047f (diff)
SVC: Implement 32-bits wrappers and update Dynarmic.
Diffstat (limited to 'src/core/arm/dynarmic')
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_32.cpp8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
index 5df4fc079..cfda12098 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
@@ -222,13 +222,17 @@ void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
Dynarmic::A32::Context context;
jit->SaveContext(context);
ctx.cpu_registers = context.Regs();
+ ctx.extension_registers = context.ExtRegs();
ctx.cpsr = context.Cpsr();
+ ctx.fpscr = context.Fpscr();
}
void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
Dynarmic::A32::Context context;
context.Regs() = ctx.cpu_registers;
+ context.ExtRegs() = ctx.extension_registers;
context.SetCpsr(ctx.cpsr);
+ context.SetFpscr(ctx.fpscr);
jit->LoadContext(context);
}
@@ -243,7 +247,9 @@ void ARM_Dynarmic_32::ClearInstructionCache() {
jit->ClearCache();
}
-void ARM_Dynarmic_32::ClearExclusiveState() {}
+void ARM_Dynarmic_32::ClearExclusiveState() {
+ jit->ClearExclusiveState();
+}
void ARM_Dynarmic_32::PageTableChanged(Common::PageTable& page_table,
std::size_t new_address_space_size_in_bits) {