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authorbunnei <bunneidev@gmail.com>2018-03-18 22:35:47 -0400
committerGitHub <noreply@github.com>2018-03-18 22:35:47 -0400
commit23a0d2d7b77fa619edc7d69d0162bd3071b67b4b (patch)
tree85f20b5e8bbd0b1b2b6e28eac6224908a0f3b7fe /src/core/core.h
parent2dc3a56e9602e0bfba9bfc19f31f0433d1564ccc (diff)
parentbc88cae0c730ece6d027778267eb0fa256479bda (diff)
Merge pull request #193 from N00byKing/3184_2_robotic_boogaloo
Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
Diffstat (limited to 'src/core/core.h')
-rw-r--r--src/core/core.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/core/core.h b/src/core/core.h
index 635109b21..552c8f5ee 100644
--- a/src/core/core.h
+++ b/src/core/core.h
@@ -53,10 +53,10 @@ public:
* is not required to do a full dispatch with each instruction. NOTE: the number of instructions
* requested is not guaranteed to run, as this will be interrupted preemptively if a hardware
* update is requested (e.g. on a thread switch).
- * @param tight_loop Number of instructions to execute.
+ * @param tight_loop If false, the CPU single-steps.
* @return Result status, indicating whether or not the operation succeeded.
*/
- ResultStatus RunLoop(int tight_loop = 100000);
+ ResultStatus RunLoop(bool tight_loop = true);
/**
* Step the CPU one instruction