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authorReinUsesLisp <reinuseslisp@airmail.cc>2021-02-21 23:42:38 -0300
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-22 21:51:22 -0400
commit274897dfd59b4d08029ab7e93be4f84654abcdc8 (patch)
tree083336a4d665476a87b888368878a311a7edab2a /src/shader_recompiler/backend/spirv/emit_spirv.h
parent704c6f353f68745168902c6c66c04bb730bd30e6 (diff)
spirv: Fixes and Intel specific workarounds
Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv.h')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index 922e294a7..cec80c13e 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -202,10 +202,10 @@ Id EmitUGreaterThan(EmitContext& ctx, Id lhs, Id rhs);
Id EmitINotEqual(EmitContext& ctx, Id lhs, Id rhs);
Id EmitSGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs);
Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs);
-void EmitLogicalOr(EmitContext& ctx);
-void EmitLogicalAnd(EmitContext& ctx);
-void EmitLogicalXor(EmitContext& ctx);
-void EmitLogicalNot(EmitContext& ctx);
+Id EmitLogicalOr(EmitContext& ctx, Id a, Id b);
+Id EmitLogicalAnd(EmitContext& ctx, Id a, Id b);
+Id EmitLogicalXor(EmitContext& ctx, Id a, Id b);
+Id EmitLogicalNot(EmitContext& ctx, Id value);
Id EmitConvertS16F16(EmitContext& ctx, Id value);
Id EmitConvertS16F32(EmitContext& ctx, Id value);
Id EmitConvertS16F64(EmitContext& ctx, Id value);