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author | bunnei <bunneidev@gmail.com> | 2023-04-14 16:56:34 -0700 |
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committer | GitHub <noreply@github.com> | 2023-04-14 16:56:34 -0700 |
commit | e0895a85810d76d810b40ade50dc514a459b685e (patch) | |
tree | cf3d44618ee0757f4994917066ba48c3b8151ac6 /src/shader_recompiler/backend/spirv | |
parent | 07694609fb85dda70d4ede4b8d3e4248c6cef2de (diff) | |
parent | c0e5ecc399cc08e4cd54b04c8d63b99e1fcbddc7 (diff) |
Merge pull request #10030 from Wollnashorn/botw-amd-fix
shader_recompiler: Fix ImageGather rounding on AMD/Intel
Diffstat (limited to 'src/shader_recompiler/backend/spirv')
-rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_image.cpp | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp index 02073c420..7d901c04b 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_image.cpp @@ -261,6 +261,30 @@ Id BitTest(EmitContext& ctx, Id mask, Id bit) { const Id bit_value{ctx.OpBitwiseAnd(ctx.U32[1], shifted, ctx.Const(1u))}; return ctx.OpINotEqual(ctx.U1, bit_value, ctx.u32_zero_value); } + +Id ImageGatherSubpixelOffset(EmitContext& ctx, const IR::TextureInstInfo& info, Id texture, + Id coords) { + // Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on + // AMD hardware as on Maxwell or other Nvidia architectures. + const auto calculate_coords{[&](size_t dim) { + const Id nudge{ctx.Const(0x1p-9f)}; + const Id image_size{ctx.OpImageQuerySizeLod(ctx.U32[dim], texture, ctx.u32_zero_value)}; + Id offset{dim == 2 ? ctx.ConstantComposite(ctx.F32[dim], nudge, nudge) + : ctx.ConstantComposite(ctx.F32[dim], nudge, nudge, ctx.f32_zero_value)}; + offset = ctx.OpFDiv(ctx.F32[dim], offset, ctx.OpConvertUToF(ctx.F32[dim], image_size)); + return ctx.OpFAdd(ctx.F32[dim], coords, offset); + }}; + switch (info.type) { + case TextureType::Color2D: + case TextureType::Color2DRect: + return calculate_coords(2); + case TextureType::ColorArray2D: + case TextureType::ColorCube: + return calculate_coords(3); + default: + return coords; + } +} } // Anonymous namespace Id EmitBindlessImageSampleImplicitLod(EmitContext&) { @@ -423,6 +447,9 @@ Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id const IR::Value& offset, const IR::Value& offset2) { const auto info{inst->Flags<IR::TextureInstInfo>()}; const ImageOperands operands(ctx, offset, offset2); + if (ctx.profile.need_gather_subpixel_offset) { + coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords); + } return Emit(&EmitContext::OpImageSparseGather, &EmitContext::OpImageGather, ctx, inst, ctx.F32[4], Texture(ctx, info, index), coords, ctx.Const(info.gather_component), operands.MaskOptional(), operands.Span()); @@ -432,6 +459,9 @@ Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, const IR::Value& offset, const IR::Value& offset2, Id dref) { const auto info{inst->Flags<IR::TextureInstInfo>()}; const ImageOperands operands(ctx, offset, offset2); + if (ctx.profile.need_gather_subpixel_offset) { + coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords); + } return Emit(&EmitContext::OpImageSparseDrefGather, &EmitContext::OpImageDrefGather, ctx, inst, ctx.F32[4], Texture(ctx, info, index), coords, dref, operands.MaskOptional(), operands.Span()); |