diff options
| author | Subv <subv2112@gmail.com> | 2018-04-20 09:16:55 -0500 |
|---|---|---|
| committer | Subv <subv2112@gmail.com> | 2018-04-20 21:09:33 -0500 |
| commit | c3a8ea76f180fbaf2d58d0454e7adc2bb1f30009 (patch) | |
| tree | 5b23e8812808e3b3f87a874b0d4e5a418675ea85 /src/video_core/engines | |
| parent | 0a5e01b710b66b9264ceb469903e8b8f16faf516 (diff) | |
ShaderGen: Implemented predicated instruction execution.
Each predicated instruction will be wrapped in an `if (predicate) { instruction_body; }` in the GLSL, where `predicate` is one of the predicate boolean variables previously set by fsetp.
Diffstat (limited to 'src/video_core/engines')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index fb639a417..e6c2fd367 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -331,7 +331,11 @@ union Instruction { OpCode opcode; BitField<0, 8, Register> gpr0; BitField<8, 8, Register> gpr8; - BitField<16, 4, Pred> pred; + union { + BitField<16, 4, Pred> full_pred; + BitField<16, 3, u64> pred_index; + } pred; + BitField<19, 1, u64> negate_pred; BitField<20, 8, Register> gpr20; BitField<20, 7, SubOp> sub_op; BitField<28, 8, Register> gpr28; |
