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authorSubv <subv2112@gmail.com>2018-04-20 09:04:54 -0500
committerSubv <subv2112@gmail.com>2018-04-20 14:57:40 -0500
commitd03fc774756306aa8fd89abd5522c928b46336c7 (patch)
tree89b74e72ec1dafe6889a34826e383e45c1f80def /src/video_core/engines
parent2e0a9f66a0d41dd81bfaa7078aad9b53bedb547e (diff)
ShaderGen: Register id 255 is special and is hardcoded to return 0 (SR_ZERO).
Diffstat (limited to 'src/video_core/engines')
-rw-r--r--src/video_core/engines/shader_bytecode.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 7cd125f05..b0da805db 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -13,6 +13,9 @@ namespace Tegra {
namespace Shader {
struct Register {
+ // Register 255 is special cased to always be 0
+ static constexpr size_t ZeroIndex = 255;
+
constexpr Register() = default;
constexpr Register(u64 value) : value(value) {}