diff options
author | Subv <subv2112@gmail.com> | 2018-02-11 23:44:12 -0500 |
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committer | Subv <subv2112@gmail.com> | 2018-02-11 23:44:12 -0500 |
commit | 6cddf9d88e7fc49919fda92bcd4235797c56f07f (patch) | |
tree | 3f7da3795b5561b2d325325b72610996e2857742 /src/video_core/gpu.h | |
parent | e01a8f218707b6f3ed0f111c432440b07ea5b6ff (diff) |
Make a GPU class in VideoCore to contain the GPU state.
Also moved the GPU MemoryManager class to video_core since it makes more sense for it to be there.
Diffstat (limited to 'src/video_core/gpu.h')
-rw-r--r-- | src/video_core/gpu.h | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/video_core/gpu.h b/src/video_core/gpu.h new file mode 100644 index 000000000..a961f3fd4 --- /dev/null +++ b/src/video_core/gpu.h @@ -0,0 +1,55 @@ +// Copyright 2018 yuzu Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#pragma once + +#include <memory> +#include <unordered_map> +#include "common/common_types.h" +#include "video_core/engines/fermi_2d.h" +#include "video_core/engines/maxwell_3d.h" +#include "video_core/engines/maxwell_compute.h" +#include "video_core/memory_manager.h" + +namespace Tegra { + +enum class EngineID { + FERMI_TWOD_A = 0x902D, // 2D Engine + MAXWELL_B = 0xB197, // 3D Engine + MAXWELL_COMPUTE_B = 0xB1C0, + KEPLER_INLINE_TO_MEMORY_B = 0xA140, + MAXWELL_DMA_COPY_A = 0xB0B5, +}; + +class GPU final { +public: + GPU() { + memory_manager = std::make_unique<MemoryManager>(); + maxwell_3d = std::make_unique<Engines::Maxwell3D>(); + fermi_2d = std::make_unique<Engines::Fermi2D>(); + maxwell_compute = std::make_unique<Engines::MaxwellCompute>(); + } + ~GPU() = default; + + /// Processes a command list stored at the specified address in GPU memory. + void ProcessCommandList(GPUVAddr address, u32 size); + + std::unique_ptr<MemoryManager> memory_manager; + +private: + /// Writes a single register in the engine bound to the specified subchannel + void WriteReg(u32 method, u32 subchannel, u32 value); + + /// Mapping of command subchannels to their bound engine ids. + std::unordered_map<u32, EngineID> bound_engines; + + /// 3D engine + std::unique_ptr<Engines::Maxwell3D> maxwell_3d; + /// 2D engine + std::unique_ptr<Engines::Fermi2D> fermi_2d; + /// Compute engine + std::unique_ptr<Engines::MaxwellCompute> maxwell_compute; +}; + +} // namespace Tegra |