video_core: Rearrange pixel format names

Normalizes pixel format names to match Vulkan names. Previous to this
commit pixel formats had no convention, leading to confusion and
potential bugs.

1 files changed, 43 insertions, 43 deletions

diff --git a/src/video_core/gpu.h b/src/video_core/gpu.h
index 464f5c7d6..d646c441c 100644
--- a/src/video_core/gpu.h
+++ b/src/video_core/gpu.h
@@ -39,42 +39,42 @@ namespace Tegra {
 
 enum class RenderTargetFormat : u32 {
     NONE = 0x0,
-    RGBA32_FLOAT = 0xC0,
-    RGBA32_SINT = 0xC1,
-    RGBA32_UINT = 0xC2,
-    RGBA16_UNORM = 0xC6,
-    RGBA16_SNORM = 0xC7,
-    RGBA16_SINT = 0xC8,
-    RGBA16_UINT = 0xC9,
-    RGBA16_FLOAT = 0xCA,
-    RG32_FLOAT = 0xCB,
-    RG32_SINT = 0xCC,
-    RG32_UINT = 0xCD,
-    RGBX16_FLOAT = 0xCE,
-    BGRA8_UNORM = 0xCF,
-    BGRA8_SRGB = 0xD0,
-    RGB10_A2_UNORM = 0xD1,
-    RGB10_A2_UINT = 0xD2,
-    RGBA8_UNORM = 0xD5,
-    RGBA8_SRGB = 0xD6,
-    RGBA8_SNORM = 0xD7,
-    RGBA8_SINT = 0xD8,
-    RGBA8_UINT = 0xD9,
-    RG16_UNORM = 0xDA,
-    RG16_SNORM = 0xDB,
-    RG16_SINT = 0xDC,
-    RG16_UINT = 0xDD,
-    RG16_FLOAT = 0xDE,
-    R11G11B10_FLOAT = 0xE0,
+    R32B32G32A32_FLOAT = 0xC0,
+    R32G32B32A32_SINT = 0xC1,
+    R32G32B32A32_UINT = 0xC2,
+    R16G16B16A16_UNORM = 0xC6,
+    R16G16B16A16_SNORM = 0xC7,
+    R16G16B16A16_SINT = 0xC8,
+    R16G16B16A16_UINT = 0xC9,
+    R16G16B16A16_FLOAT = 0xCA,
+    R32G32_FLOAT = 0xCB,
+    R32G32_SINT = 0xCC,
+    R32G32_UINT = 0xCD,
+    R16G16B16X16_FLOAT = 0xCE,
+    B8G8R8A8_UNORM = 0xCF,
+    B8G8R8A8_SRGB = 0xD0,
+    A2B10G10R10_UNORM = 0xD1,
+    A2B10G10R10_UINT = 0xD2,
+    A8B8G8R8_UNORM = 0xD5,
+    A8B8G8R8_SRGB = 0xD6,
+    A8B8G8R8_SNORM = 0xD7,
+    A8B8G8R8_SINT = 0xD8,
+    A8B8G8R8_UINT = 0xD9,
+    R16G16_UNORM = 0xDA,
+    R16G16_SNORM = 0xDB,
+    R16G16_SINT = 0xDC,
+    R16G16_UINT = 0xDD,
+    R16G16_FLOAT = 0xDE,
+    B10G11R11_FLOAT = 0xE0,
     R32_SINT = 0xE3,
     R32_UINT = 0xE4,
     R32_FLOAT = 0xE5,
-    B5G6R5_UNORM = 0xE8,
-    BGR5A1_UNORM = 0xE9,
-    RG8_UNORM = 0xEA,
-    RG8_SNORM = 0xEB,
-    RG8_SINT = 0xEC,
-    RG8_UINT = 0xED,
+    R5G6B5_UNORM = 0xE8,
+    A1R5G5B5_UNORM = 0xE9,
+    R8G8_UNORM = 0xEA,
+    R8G8_SNORM = 0xEB,
+    R8G8_SINT = 0xEC,
+    R8G8_UINT = 0xED,
     R16_UNORM = 0xEE,
     R16_SNORM = 0xEF,
     R16_SINT = 0xF0,
@@ -87,13 +87,13 @@ enum class RenderTargetFormat : u32 {
 };
 
 enum class DepthFormat : u32 {
-    Z32_FLOAT = 0xA,
-    Z16_UNORM = 0x13,
-    S8_Z24_UNORM = 0x14,
-    Z24_X8_UNORM = 0x15,
-    Z24_S8_UNORM = 0x16,
-    Z24_C8_UNORM = 0x18,
-    Z32_S8_X24_FLOAT = 0x19,
+    D32_FLOAT = 0xA,
+    D16_UNORM = 0x13,
+    S8_UINT_Z24_UNORM = 0x14,
+    D24X8_UNORM = 0x15,
+    D24S8_UNORM = 0x16,
+    D24C8_UNORM = 0x18,
+    D32_FLOAT_S8X24_UINT = 0x19,
 };
 
 struct CommandListHeader;
@@ -104,9 +104,9 @@ class DebugContext;
  */
 struct FramebufferConfig {
     enum class PixelFormat : u32 {
-        ABGR8 = 1,
-        RGB565 = 4,
-        BGRA8 = 5,
+        A8B8G8R8_UNORM = 1,
+        RGB565_UNORM = 4,
+        B8G8R8A8_UNORM = 5,
     };
 
     VAddr address;