diff options
| author | Fernando Sahmkow <fsahmkow27@gmail.com> | 2019-11-12 10:07:22 -0400 |
|---|---|---|
| committer | FernandoS27 <fsahmkow27@gmail.com> | 2019-11-14 11:15:27 -0400 |
| commit | f3d1b370aa0fd614cf28f8a609b70906d40da751 (patch) | |
| tree | 028b5f4b34c30d477e6989b49540db508a8db075 /src/video_core/shader | |
| parent | 95137a04e1925c6467a1623a1eb883c14a8c89ba (diff) | |
Shader_IR: Implement FLO instruction.
Diffstat (limited to 'src/video_core/shader')
| -rw-r--r-- | src/video_core/shader/decode/arithmetic_integer.cpp | 18 | ||||
| -rw-r--r-- | src/video_core/shader/node.h | 2 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic_integer.cpp b/src/video_core/shader/decode/arithmetic_integer.cpp index a33d242e9..9208b7bef 100644 --- a/src/video_core/shader/decode/arithmetic_integer.cpp +++ b/src/video_core/shader/decode/arithmetic_integer.cpp @@ -130,6 +130,24 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) { SetRegister(bb, instr.gpr0, value); break; } + case OpCode::Id::FLO_R: + case OpCode::Id::FLO_C: + case OpCode::Id::FLO_IMM: { + Node value; + if (instr.flo.invert) { + op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b); + } + if (instr.flo.is_signed) { + value = Operation(OperationCode::IBitMSB, NO_PRECISE, op_b); + } else { + value = Operation(OperationCode::UBitMSB, NO_PRECISE, op_b); + } + if (instr.flo.sh) { + value = Operation(OperationCode::UBitwiseXor, NO_PRECISE, value, Immediate(31)); + } + SetRegister(bb, instr.gpr0, value); + break; + } case OpCode::Id::SEL_C: case OpCode::Id::SEL_R: case OpCode::Id::SEL_IMM: { diff --git a/src/video_core/shader/node.h b/src/video_core/shader/node.h index 54217e6a4..2d11facaf 100644 --- a/src/video_core/shader/node.h +++ b/src/video_core/shader/node.h @@ -68,6 +68,7 @@ enum class OperationCode { IBitfieldInsert, /// (MetaArithmetic, int base, int insert, int offset, int bits) -> int IBitfieldExtract, /// (MetaArithmetic, int value, int offset, int offset) -> int IBitCount, /// (MetaArithmetic, int) -> int + IBitMSB, /// (MetaArithmetic, int) -> int UAdd, /// (MetaArithmetic, uint a, uint b) -> uint UMul, /// (MetaArithmetic, uint a, uint b) -> uint @@ -86,6 +87,7 @@ enum class OperationCode { UBitfieldInsert, /// (MetaArithmetic, uint base, uint insert, int offset, int bits) -> uint UBitfieldExtract, /// (MetaArithmetic, uint value, int offset, int offset) -> uint UBitCount, /// (MetaArithmetic, uint) -> uint + UBitMSB, /// (MetaArithmetic, uint) -> uint HAdd, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2 HMul, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2 |