diff options
| author | jam1garner <8260240+jam1garner@users.noreply.github.com> | 2021-11-21 21:18:56 -0500 |
|---|---|---|
| committer | jam1garner <8260240+jam1garner@users.noreply.github.com> | 2021-11-21 21:18:56 -0500 |
| commit | c8a67a725de6481c891d5bfe1b83fcb6340c88a3 (patch) | |
| tree | 9211464997cc2f241a56fd88b810f8bd599c9a73 /src | |
| parent | 84eb3e7d02d386bc90eb4a6c6b6e33eea33a42e2 (diff) | |
arm: dynarmic: Implement icache op handling for 'ic iallu' instruction
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_64.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp index 587fffb34..8fe83413c 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp @@ -98,6 +98,9 @@ public: return; case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU: + parent.ClearInstructionCache(); + return; + case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable: default: LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation"); |