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-rw-r--r--src/core/hw/gpu.cpp253
1 files changed, 175 insertions, 78 deletions
diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp
index f0ca4eada..c00be2a83 100644
--- a/src/core/hw/gpu.cpp
+++ b/src/core/hw/gpu.cpp
@@ -15,48 +15,58 @@
namespace GPU {
-Registers g_regs;
+RegisterSet<u32, Regs> g_regs;
u64 g_last_ticks = 0; ///< Last CPU ticks
/**
* Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM
- * @param
+ * @param
*/
void SetFramebufferLocation(const FramebufferLocation mode) {
switch (mode) {
case FRAMEBUFFER_LOCATION_FCRAM:
- g_regs.framebuffer_top_left_1 = PADDR_TOP_LEFT_FRAME1;
- g_regs.framebuffer_top_left_2 = PADDR_TOP_LEFT_FRAME2;
- g_regs.framebuffer_top_right_1 = PADDR_TOP_RIGHT_FRAME1;
- g_regs.framebuffer_top_right_2 = PADDR_TOP_RIGHT_FRAME2;
- g_regs.framebuffer_sub_left_1 = PADDR_SUB_FRAME1;
- //g_regs.framebuffer_sub_left_2 = unknown;
- g_regs.framebuffer_sub_right_1 = PADDR_SUB_FRAME2;
- //g_regs.framebufferr_sub_right_2 = unknown;
+ {
+ auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
+ auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
+
+ framebuffer_top.address_left1 = PADDR_TOP_LEFT_FRAME1;
+ framebuffer_top.address_left2 = PADDR_TOP_LEFT_FRAME2;
+ framebuffer_top.address_right1 = PADDR_TOP_RIGHT_FRAME1;
+ framebuffer_top.address_right2 = PADDR_TOP_RIGHT_FRAME2;
+ framebuffer_sub.address_left1 = PADDR_SUB_FRAME1;
+ //framebuffer_sub.address_left2 = unknown;
+ framebuffer_sub.address_right1 = PADDR_SUB_FRAME2;
+ //framebuffer_sub.address_right2 = unknown;
break;
+ }
case FRAMEBUFFER_LOCATION_VRAM:
- g_regs.framebuffer_top_left_1 = PADDR_VRAM_TOP_LEFT_FRAME1;
- g_regs.framebuffer_top_left_2 = PADDR_VRAM_TOP_LEFT_FRAME2;
- g_regs.framebuffer_top_right_1 = PADDR_VRAM_TOP_RIGHT_FRAME1;
- g_regs.framebuffer_top_right_2 = PADDR_VRAM_TOP_RIGHT_FRAME2;
- g_regs.framebuffer_sub_left_1 = PADDR_VRAM_SUB_FRAME1;
- //g_regs.framebuffer_sub_left_2 = unknown;
- g_regs.framebuffer_sub_right_1 = PADDR_VRAM_SUB_FRAME2;
- //g_regs.framebufferr_sub_right_2 = unknown;
+ {
+ auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
+ auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
+
+ framebuffer_top.address_left1 = PADDR_VRAM_TOP_LEFT_FRAME1;
+ framebuffer_top.address_left2 = PADDR_VRAM_TOP_LEFT_FRAME2;
+ framebuffer_top.address_right1 = PADDR_VRAM_TOP_RIGHT_FRAME1;
+ framebuffer_top.address_right2 = PADDR_VRAM_TOP_RIGHT_FRAME2;
+ framebuffer_sub.address_left1 = PADDR_VRAM_SUB_FRAME1;
+ //framebuffer_sub.address_left2 = unknown;
+ framebuffer_sub.address_right1 = PADDR_VRAM_SUB_FRAME2;
+ //framebuffer_sub.address_right2 = unknown;
break;
}
+ }
}
/**
* Gets the location of the framebuffers
* @return Location of framebuffers as FramebufferLocation enum
*/
-const FramebufferLocation GetFramebufferLocation() {
- if ((g_regs.framebuffer_top_right_1 & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) {
+FramebufferLocation GetFramebufferLocation(u32 address) {
+ if ((address & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) {
return FRAMEBUFFER_LOCATION_VRAM;
- } else if ((g_regs.framebuffer_top_right_1 & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) {
+ } else if ((address & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) {
return FRAMEBUFFER_LOCATION_FCRAM;
} else {
ERROR_LOG(GPU, "unknown framebuffer location!");
@@ -64,91 +74,161 @@ const FramebufferLocation GetFramebufferLocation() {
return FRAMEBUFFER_LOCATION_UNKNOWN;
}
+u32 GetFramebufferAddr(const u32 address) {
+ switch (GetFramebufferLocation(address)) {
+ case FRAMEBUFFER_LOCATION_FCRAM:
+ return Memory::VirtualAddressFromPhysical_FCRAM(address);
+ case FRAMEBUFFER_LOCATION_VRAM:
+ return Memory::VirtualAddressFromPhysical_VRAM(address);
+ default:
+ ERROR_LOG(GPU, "unknown framebuffer location");
+ }
+ return 0;
+}
+
/**
* Gets a read-only pointer to a framebuffer in memory
* @param address Physical address of framebuffer
* @return Returns const pointer to raw framebuffer
*/
const u8* GetFramebufferPointer(const u32 address) {
- switch (GetFramebufferLocation()) {
- case FRAMEBUFFER_LOCATION_FCRAM:
- return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_FCRAM(address));
- case FRAMEBUFFER_LOCATION_VRAM:
- return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_VRAM(address));
- default:
- ERROR_LOG(GPU, "unknown framebuffer location");
- }
- return NULL;
+ u32 addr = GetFramebufferAddr(address);
+ return (addr != 0) ? Memory::GetPointer(addr) : nullptr;
}
template <typename T>
-inline void Read(T &var, const u32 addr) {
- switch (addr) {
- case Registers::FramebufferTopLeft1:
- var = g_regs.framebuffer_top_left_1;
- break;
+inline void Read(T &var, const u32 raw_addr) {
+ u32 addr = raw_addr - 0x1EF00000;
+ int index = addr / 4;
- case Registers::FramebufferTopLeft2:
- var = g_regs.framebuffer_top_left_2;
- break;
+ // Reads other than u32 are untested, so I'd rather have them abort than silently fail
+ if (index >= Regs::NumIds || !std::is_same<T,u32>::value)
+ {
+ ERROR_LOG(GPU, "unknown Read%d @ 0x%08X", sizeof(var) * 8, addr);
+ return;
+ }
- case Registers::FramebufferTopRight1:
- var = g_regs.framebuffer_top_right_1;
- break;
+ var = g_regs[static_cast<Regs::Id>(addr / 4)];
+}
- case Registers::FramebufferTopRight2:
- var = g_regs.framebuffer_top_right_2;
- break;
+template <typename T>
+inline void Write(u32 addr, const T data) {
+ addr -= 0x1EF00000;
+ int index = addr / 4;
- case Registers::FramebufferSubLeft1:
- var = g_regs.framebuffer_sub_left_1;
- break;
+ // Writes other than u32 are untested, so I'd rather have them abort than silently fail
+ if (index >= Regs::NumIds || !std::is_same<T,u32>::value)
+ {
+ ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
+ return;
+ }
- case Registers::FramebufferSubRight1:
- var = g_regs.framebuffer_sub_right_1;
- break;
+ g_regs[static_cast<Regs::Id>(index)] = data;
- case Registers::CommandListSize:
- var = g_regs.command_list_size;
- break;
+ switch (static_cast<Regs::Id>(index)) {
- case Registers::CommandListAddress:
- var = g_regs.command_list_address;
- break;
+ // Memory fills are triggered once the fill value is written.
+ // NOTE: This is not verified.
+ case Regs::MemoryFill + 3:
+ case Regs::MemoryFill + 7:
+ {
+ const auto& config = g_regs.Get<Regs::MemoryFill>(static_cast<Regs::Id>(index - 3));
- case Registers::ProcessCommandList:
- var = g_regs.command_processing_enabled;
- break;
+ // TODO: Not sure if this check should be done at GSP level instead
+ if (config.address_start) {
+ // TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all
+ u32* start = (u32*)Memory::GetPointer(config.GetStartAddress());
+ u32* end = (u32*)Memory::GetPointer(config.GetEndAddress());
+ for (u32* ptr = start; ptr < end; ++ptr)
+ *ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation
- default:
- ERROR_LOG(GPU, "unknown Read%d @ 0x%08X", sizeof(var) * 8, addr);
+ DEBUG_LOG(GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress());
+ }
break;
}
-}
-
-template <typename T>
-inline void Write(u32 addr, const T data) {
- switch (static_cast<Registers::Id>(addr)) {
- case Registers::CommandListSize:
- g_regs.command_list_size = data;
- break;
- case Registers::CommandListAddress:
- g_regs.command_list_address = data;
+ case Regs::DisplayTransfer + 6:
+ {
+ const auto& config = g_regs.Get<Regs::DisplayTransfer>();
+ if (config.trigger & 1) {
+ u8* source_pointer = Memory::GetPointer(config.GetPhysicalInputAddress());
+ u8* dest_pointer = Memory::GetPointer(config.GetPhysicalOutputAddress());
+
+ for (int y = 0; y < config.output_height; ++y) {
+ // TODO: Why does the register seem to hold twice the framebuffer width?
+ for (int x = 0; x < config.output_width / 2; ++x) {
+ struct {
+ int r, g, b, a;
+ } source_color = { 0, 0, 0, 0 };
+
+ switch (config.input_format) {
+ case Regs::FramebufferFormat::RGBA8:
+ {
+ // TODO: Most likely got the component order messed up.
+ u8* srcptr = source_pointer + x * 4 + y * config.input_width * 4 / 2;
+ source_color.r = srcptr[0]; // blue
+ source_color.g = srcptr[1]; // green
+ source_color.b = srcptr[2]; // red
+ source_color.a = srcptr[3]; // alpha
+ break;
+ }
+
+ default:
+ ERROR_LOG(GPU, "Unknown source framebuffer format %x", config.input_format.Value());
+ break;
+ }
+
+ switch (config.output_format) {
+ /*case Regs::FramebufferFormat::RGBA8:
+ {
+ // TODO: Untested
+ u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4);
+ dstptr[0] = source_color.r;
+ dstptr[1] = source_color.g;
+ dstptr[2] = source_color.b;
+ dstptr[3] = source_color.a;
+ break;
+ }*/
+
+ case Regs::FramebufferFormat::RGB8:
+ {
+ // TODO: Most likely got the component order messed up.
+ u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3 / 2;
+ dstptr[0] = source_color.r; // blue
+ dstptr[1] = source_color.g; // green
+ dstptr[2] = source_color.b; // red
+ break;
+ }
+
+ default:
+ ERROR_LOG(GPU, "Unknown destination framebuffer format %x", config.output_format.Value());
+ break;
+ }
+ }
+ }
+
+ DEBUG_LOG(GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%dx%d)-> 0x%08x(%dx%d), dst format %x",
+ config.output_height * config.output_width * 4,
+ config.GetPhysicalInputAddress(), (int)config.input_width, (int)config.input_height,
+ config.GetPhysicalOutputAddress(), (int)config.output_width, (int)config.output_height,
+ config.output_format.Value());
+ }
break;
+ }
- case Registers::ProcessCommandList:
- g_regs.command_processing_enabled = data;
- if (g_regs.command_processing_enabled & 1)
+ case Regs::CommandProcessor + 4:
+ {
+ const auto& config = g_regs.Get<Regs::CommandProcessor>();
+ if (config.trigger & 1)
{
- // u32* buffer = (u32*)Memory::GetPointer(g_regs.command_list_address << 3);
- ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", g_regs.command_list_size, g_regs.command_list_address << 3);
+ // u32* buffer = (u32*)Memory::GetPointer(config.address << 3);
+ ERROR_LOG(GPU, "Beginning 0x%08x bytes of commands from address 0x%08x", config.size, config.address << 3);
// TODO: Process command list!
}
break;
+ }
default:
- ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr);
break;
}
}
@@ -180,7 +260,24 @@ void Update() {
/// Initialize hardware
void Init() {
g_last_ticks = Core::g_app_core->GetTicks();
- SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM);
+// SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM);
+ SetFramebufferLocation(FRAMEBUFFER_LOCATION_VRAM);
+
+ auto& framebuffer_top = g_regs.Get<Regs::FramebufferTop>();
+ auto& framebuffer_sub = g_regs.Get<Regs::FramebufferBottom>();
+ // TODO: Width should be 240 instead?
+ framebuffer_top.width = 480;
+ framebuffer_top.height = 400;
+ framebuffer_top.stride = 480*3;
+ framebuffer_top.color_format = Regs::FramebufferFormat::RGB8;
+ framebuffer_top.active_fb = 0;
+
+ framebuffer_sub.width = 480;
+ framebuffer_sub.height = 400;
+ framebuffer_sub.stride = 480*3;
+ framebuffer_sub.color_format = Regs::FramebufferFormat::RGB8;
+ framebuffer_sub.active_fb = 0;
+
NOTICE_LOG(GPU, "initialized OK");
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-29 13:07:13 +0000