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-rw-r--r--src/core/arm/arm_interface.h28
-rw-r--r--src/core/arm/disassembler/arm_disasm.cpp948
-rw-r--r--src/core/arm/disassembler/arm_disasm.h152
-rw-r--r--src/core/arm/dyncom/arm_dyncom.cpp16
-rw-r--r--src/core/arm/dyncom/arm_dyncom.h4
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp41
-rw-r--r--src/core/arm/skyeye_common/arm_regformat.h2
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.cpp17
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpdouble.cpp9
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpsingle.cpp9
-rw-r--r--src/core/settings.h1
-rw-r--r--src/core/tracer/citrace.h70
12 files changed, 1014 insertions, 283 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index 85ed2c698..5cffe513c 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -62,6 +62,34 @@ public:
virtual void SetReg(int index, u32 value) = 0;
/**
+ * Gets the value of a VFP register
+ * @param index Register index (0-31)
+ * @return Returns the value in the register
+ */
+ virtual u32 GetVFPReg(int index) const = 0;
+
+ /**
+ * Sets a VFP register to the given value
+ * @param index Register index (0-31)
+ * @param value Value to set register to
+ */
+ virtual void SetVFPReg(int index, u32 value) = 0;
+
+ /**
+ * Gets the current value within a given VFP system register
+ * @param reg The VFP system register
+ * @return The value within the VFP system register
+ */
+ virtual u32 GetVFPSystemReg(VFPSystemRegister reg) const = 0;
+
+ /**
+ * Sets the VFP system register to the given value
+ * @param reg The VFP system register
+ * @param value Value to set the VFP system register to
+ */
+ virtual void SetVFPSystemReg(VFPSystemRegister reg, u32 value) = 0;
+
+ /**
* Get the current CPSR register
* @return Returns the value of the CPSR register
*/
diff --git a/src/core/arm/disassembler/arm_disasm.cpp b/src/core/arm/disassembler/arm_disasm.cpp
index f6d44d85a..77af10b54 100644
--- a/src/core/arm/disassembler/arm_disasm.cpp
+++ b/src/core/arm/disassembler/arm_disasm.cpp
@@ -1,9 +1,13 @@
// Copyright 2006 The Android Open Source Project
#include <string>
+#include <unordered_set>
+#include "common/common_types.h"
#include "common/string_util.h"
+
#include "core/arm/disassembler/arm_disasm.h"
+#include "core/arm/skyeye_common/armsupp.h"
static const char *cond_names[] = {
"eq",
@@ -37,6 +41,7 @@ static const char *opcode_names[] = {
"blx",
"bx",
"cdp",
+ "clrex",
"clz",
"cmn",
"cmp",
@@ -46,6 +51,10 @@ static const char *opcode_names[] = {
"ldr",
"ldrb",
"ldrbt",
+ "ldrex",
+ "ldrexb",
+ "ldrexd",
+ "ldrexh",
"ldrh",
"ldrsb",
"ldrsh",
@@ -58,28 +67,105 @@ static const char *opcode_names[] = {
"msr",
"mul",
"mvn",
+ "nop",
"orr",
+ "pkh",
"pld",
+ "qadd16",
+ "qadd8",
+ "qasx",
+ "qsax",
+ "qsub16",
+ "qsub8",
+ "rev",
+ "rev16",
+ "revsh",
"rsb",
"rsc",
+ "sadd16",
+ "sadd8",
+ "sasx",
"sbc",
+ "sel",
+ "sev",
+ "shadd16",
+ "shadd8",
+ "shasx",
+ "shsax",
+ "shsub16",
+ "shsub8",
+ "smlad",
"smlal",
+ "smlald",
+ "smlsd",
+ "smlsld",
+ "smmla",
+ "smmls",
+ "smmul",
+ "smuad",
"smull",
+ "smusd",
+ "ssat",
+ "ssat16",
+ "ssax",
+ "ssub16",
+ "ssub8",
"stc",
"stm",
"str",
"strb",
"strbt",
+ "strex",
+ "strexb",
+ "strexd",
+ "strexh",
"strh",
"strt",
"sub",
"swi",
"swp",
"swpb",
+ "sxtab",
+ "sxtab16",
+ "sxtah",
+ "sxtb",
+ "sxtb16",
+ "sxth",
"teq",
"tst",
+ "uadd16",
+ "uadd8",
+ "uasx",
+ "uhadd16",
+ "uhadd8",
+ "uhasx",
+ "uhsax",
+ "uhsub16",
+ "uhsub8",
"umlal",
"umull",
+ "uqadd16",
+ "uqadd8",
+ "uqasx",
+ "uqsax",
+ "uqsub16",
+ "uqsub8",
+ "usad8",
+ "usada8",
+ "usat",
+ "usat16",
+ "usax",
+ "usub16",
+ "usub8",
+ "uxtab",
+ "uxtab16",
+ "uxtah",
+ "uxtb",
+ "uxtb16",
+ "uxth",
+ "wfe",
+ "wfi",
+ "yield",
"undefined",
"adc",
@@ -131,11 +217,11 @@ static const char *shift_names[] = {
"ROR"
};
-static const char* cond_to_str(uint32_t cond) {
+static const char* cond_to_str(u32 cond) {
return cond_names[cond];
}
-std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
+std::string ARM_Disasm::Disassemble(u32 addr, u32 insn)
{
Opcode opcode = Decode(insn);
switch (opcode) {
@@ -172,6 +258,8 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
return DisassembleBX(insn);
case OP_CDP:
return "cdp";
+ case OP_CLREX:
+ return "clrex";
case OP_CLZ:
return DisassembleCLZ(insn);
case OP_LDC:
@@ -188,6 +276,15 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
case OP_STRBT:
case OP_STRT:
return DisassembleMem(insn);
+ case OP_LDREX:
+ case OP_LDREXB:
+ case OP_LDREXD:
+ case OP_LDREXH:
+ case OP_STREX:
+ case OP_STREXB:
+ case OP_STREXD:
+ case OP_STREXH:
+ return DisassembleREX(opcode, insn);
case OP_LDRH:
case OP_LDRSB:
case OP_LDRSH:
@@ -204,8 +301,76 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
return DisassembleMSR(insn);
case OP_MUL:
return DisassembleMUL(opcode, insn);
+ case OP_NOP:
+ case OP_SEV:
+ case OP_WFE:
+ case OP_WFI:
+ case OP_YIELD:
+ return DisassembleNoOperands(opcode, insn);
+ case OP_PKH:
+ return DisassemblePKH(insn);
case OP_PLD:
return DisassemblePLD(insn);
+ case OP_QADD16:
+ case OP_QADD8:
+ case OP_QASX:
+ case OP_QSAX:
+ case OP_QSUB16:
+ case OP_QSUB8:
+ case OP_SADD16:
+ case OP_SADD8:
+ case OP_SASX:
+ case OP_SHADD16:
+ case OP_SHADD8:
+ case OP_SHASX:
+ case OP_SHSAX:
+ case OP_SHSUB16:
+ case OP_SHSUB8:
+ case OP_SSAX:
+ case OP_SSUB16:
+ case OP_SSUB8:
+ case OP_UADD16:
+ case OP_UADD8:
+ case OP_UASX:
+ case OP_UHADD16:
+ case OP_UHADD8:
+ case OP_UHASX:
+ case OP_UHSAX:
+ case OP_UHSUB16:
+ case OP_UHSUB8:
+ case OP_UQADD16:
+ case OP_UQADD8:
+ case OP_UQASX:
+ case OP_UQSAX:
+ case OP_UQSUB16:
+ case OP_UQSUB8:
+ case OP_USAX:
+ case OP_USUB16:
+ case OP_USUB8:
+ return DisassembleParallelAddSub(opcode, insn);
+ case OP_REV:
+ case OP_REV16:
+ case OP_REVSH:
+ return DisassembleREV(opcode, insn);
+ case OP_SEL:
+ return DisassembleSEL(insn);
+ case OP_SMLAD:
+ case OP_SMLALD:
+ case OP_SMLSD:
+ case OP_SMLSLD:
+ case OP_SMMLA:
+ case OP_SMMLS:
+ case OP_SMMUL:
+ case OP_SMUAD:
+ case OP_SMUSD:
+ case OP_USAD8:
+ case OP_USADA8:
+ return DisassembleMediaMulDiv(opcode, insn);
+ case OP_SSAT:
+ case OP_SSAT16:
+ case OP_USAT:
+ case OP_USAT16:
+ return DisassembleSAT(opcode, insn);
case OP_STC:
return "stc";
case OP_SWI:
@@ -213,6 +378,19 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
case OP_SWP:
case OP_SWPB:
return DisassembleSWP(opcode, insn);
+ case OP_SXTAB:
+ case OP_SXTAB16:
+ case OP_SXTAH:
+ case OP_SXTB:
+ case OP_SXTB16:
+ case OP_SXTH:
+ case OP_UXTAB:
+ case OP_UXTAB16:
+ case OP_UXTAH:
+ case OP_UXTB:
+ case OP_UXTB16:
+ case OP_UXTH:
+ return DisassembleXT(opcode, insn);
case OP_UMLAL:
case OP_UMULL:
case OP_SMLAL:
@@ -224,22 +402,22 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
return NULL;
}
-std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn)
+std::string ARM_Disasm::DisassembleALU(Opcode opcode, u32 insn)
{
- static const uint8_t kNoOperand1 = 1;
- static const uint8_t kNoDest = 2;
- static const uint8_t kNoSbit = 4;
+ static const u8 kNoOperand1 = 1;
+ static const u8 kNoDest = 2;
+ static const u8 kNoSbit = 4;
std::string rn_str;
std::string rd_str;
- uint8_t flags = 0;
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t is_immed = (insn >> 25) & 0x1;
- uint8_t bit_s = (insn >> 20) & 1;
- uint8_t rn = (insn >> 16) & 0xf;
- uint8_t rd = (insn >> 12) & 0xf;
- uint8_t immed = insn & 0xff;
+ u8 flags = 0;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 is_immed = (insn >> 25) & 0x1;
+ u8 bit_s = (insn >> 20) & 1;
+ u8 rn = (insn >> 16) & 0xf;
+ u8 rd = (insn >> 12) & 0xf;
+ u8 immed = insn & 0xff;
const char* opname = opcode_names[opcode];
switch (opcode) {
@@ -279,14 +457,14 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn)
opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed);
}
- uint8_t shift_is_reg = (insn >> 4) & 1;
- uint8_t rotate = (insn >> 8) & 0xf;
- uint8_t rm = insn & 0xf;
- uint8_t shift_type = (insn >> 5) & 0x3;
- uint8_t rs = (insn >> 8) & 0xf;
- uint8_t shift_amount = (insn >> 7) & 0x1f;
- uint32_t rotated_val = immed;
- uint8_t rotate2 = rotate << 1;
+ u8 shift_is_reg = (insn >> 4) & 1;
+ u8 rotate = (insn >> 8) & 0xf;
+ u8 rm = insn & 0xf;
+ u8 shift_type = (insn >> 5) & 0x3;
+ u8 rs = (insn >> 8) & 0xf;
+ u8 shift_amount = (insn >> 7) & 0x1f;
+ u32 rotated_val = immed;
+ u8 rotate2 = rotate << 1;
rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2));
if (!shift_is_reg && shift_type == 0 && shift_amount == 0) {
@@ -312,10 +490,10 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn)
shift_name, shift_amount);
}
-std::string ARM_Disasm::DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t insn)
+std::string ARM_Disasm::DisassembleBranch(u32 addr, Opcode opcode, u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint32_t offset = insn & 0xffffff;
+ u8 cond = (insn >> 28) & 0xf;
+ u32 offset = insn & 0xffffff;
// Sign-extend the 24-bit offset
if ((offset >> 23) & 1)
offset |= 0xff000000;
@@ -328,39 +506,71 @@ std::string ARM_Disasm::DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t
return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr);
}
-std::string ARM_Disasm::DisassembleBX(uint32_t insn)
+std::string ARM_Disasm::DisassembleBX(u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t rn = insn & 0xf;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 rn = insn & 0xf;
return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn);
}
-std::string ARM_Disasm::DisassembleBKPT(uint32_t insn)
+std::string ARM_Disasm::DisassembleBKPT(u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint32_t immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf);
+ u8 cond = (insn >> 28) & 0xf;
+ u32 immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf);
return Common::StringFromFormat("bkpt%s\t#%d", cond_to_str(cond), immed);
}
-std::string ARM_Disasm::DisassembleCLZ(uint32_t insn)
+std::string ARM_Disasm::DisassembleCLZ(u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t rd = (insn >> 12) & 0xf;
- uint8_t rm = insn & 0xf;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 rd = (insn >> 12) & 0xf;
+ u8 rm = insn & 0xf;
return Common::StringFromFormat("clz%s\tr%d, r%d", cond_to_str(cond), rd, rm);
}
-std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn)
+std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, u32 insn) {
+ u32 cond = BITS(insn, 28, 31);
+ u32 rd = BITS(insn, 16, 19);
+ u32 ra = BITS(insn, 12, 15);
+ u32 rm = BITS(insn, 8, 11);
+ u32 m = BIT(insn, 5);
+ u32 rn = BITS(insn, 0, 3);
+
+ std::string cross = "";
+ if (m) {
+ if (opcode == OP_SMMLA || opcode == OP_SMMUL || opcode == OP_SMMLS)
+ cross = "r";
+ else
+ cross = "x";
+ }
+
+ std::string ext_reg = "";
+ std::unordered_set<Opcode, std::hash<int>> with_ext_reg = {
+ OP_SMLAD, OP_SMLSD, OP_SMMLA, OP_SMMLS, OP_USADA8
+ };
+ if (with_ext_reg.find(opcode) != with_ext_reg.end())
+ ext_reg = Common::StringFromFormat(", r%u", ra);
+
+ std::string rd_low = "";
+ if (opcode == OP_SMLALD || opcode == OP_SMLSLD)
+ rd_low = Common::StringFromFormat("r%u, ", ra);
+
+ return Common::StringFromFormat("%s%s%s\t%sr%u, r%u, r%u%s", opcode_names[opcode],
+ cross.c_str(), cond_to_str(cond), rd_low.c_str(), rd, rn, rm,
+ ext_reg.c_str());
+}
+
+std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, u32 insn)
{
std::string tmp_list;
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t write_back = (insn >> 21) & 0x1;
- uint8_t bit_s = (insn >> 22) & 0x1;
- uint8_t is_up = (insn >> 23) & 0x1;
- uint8_t is_pre = (insn >> 24) & 0x1;
- uint8_t rn = (insn >> 16) & 0xf;
- uint16_t reg_list = insn & 0xffff;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 write_back = (insn >> 21) & 0x1;
+ u8 bit_s = (insn >> 22) & 0x1;
+ u8 is_up = (insn >> 23) & 0x1;
+ u8 is_pre = (insn >> 24) & 0x1;
+ u8 rn = (insn >> 16) & 0xf;
+ u16 reg_list = insn & 0xffff;
const char *opname = opcode_names[opcode];
@@ -400,18 +610,18 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn)
opname, cond_to_str(cond), addr_mode, rn, bang, tmp_list.c_str(), carret);
}
-std::string ARM_Disasm::DisassembleMem(uint32_t insn)
+std::string ARM_Disasm::DisassembleMem(u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t is_reg = (insn >> 25) & 0x1;
- uint8_t is_load = (insn >> 20) & 0x1;
- uint8_t write_back = (insn >> 21) & 0x1;
- uint8_t is_byte = (insn >> 22) & 0x1;
- uint8_t is_up = (insn >> 23) & 0x1;
- uint8_t is_pre = (insn >> 24) & 0x1;
- uint8_t rn = (insn >> 16) & 0xf;
- uint8_t rd = (insn >> 12) & 0xf;
- uint16_t offset = insn & 0xfff;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 is_reg = (insn >> 25) & 0x1;
+ u8 is_load = (insn >> 20) & 0x1;
+ u8 write_back = (insn >> 21) & 0x1;
+ u8 is_byte = (insn >> 22) & 0x1;
+ u8 is_up = (insn >> 23) & 0x1;
+ u8 is_pre = (insn >> 24) & 0x1;
+ u8 rn = (insn >> 16) & 0xf;
+ u8 rd = (insn >> 12) & 0xf;
+ u16 offset = insn & 0xfff;
const char *opname = "ldr";
if (!is_load)
@@ -448,9 +658,9 @@ std::string ARM_Disasm::DisassembleMem(uint32_t insn)
}
}
- uint8_t rm = insn & 0xf;
- uint8_t shift_type = (insn >> 5) & 0x3;
- uint8_t shift_amount = (insn >> 7) & 0x1f;
+ u8 rm = insn & 0xf;
+ u8 shift_type = (insn >> 5) & 0x3;
+ u8 shift_amount = (insn >> 7) & 0x1f;
const char *shift_name = shift_names[shift_type];
@@ -492,19 +702,19 @@ std::string ARM_Disasm::DisassembleMem(uint32_t insn)
shift_name, shift_amount);
}
-std::string ARM_Disasm::DisassembleMemHalf(uint32_t insn)
+std::string ARM_Disasm::DisassembleMemHalf(u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t is_load = (insn >> 20) & 0x1;
- uint8_t write_back = (insn >> 21) & 0x1;
- uint8_t is_immed = (insn >> 22) & 0x1;
- uint8_t is_up = (insn >> 23) & 0x1;
- uint8_t is_pre = (insn >> 24) & 0x1;
- uint8_t rn = (insn >> 16) & 0xf;
- uint8_t rd = (insn >> 12) & 0xf;
- uint8_t bits_65 = (insn >> 5) & 0x3;
- uint8_t rm = insn & 0xf;
- uint8_t offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf);
+ u8 cond = (insn >> 28) & 0xf;
+ u8 is_load = (insn >> 20) & 0x1;
+ u8 write_back = (insn >> 21) & 0x1;
+ u8 is_immed = (insn >> 22) & 0x1;
+ u8 is_up = (insn >> 23) & 0x1;
+ u8 is_pre = (insn >> 24) & 0x1;
+ u8 rn = (insn >> 16) & 0xf;
+ u8 rd = (insn >> 12) & 0xf;
+ u8 bits_65 = (insn >> 5) & 0x3;
+ u8 rm = insn & 0xf;
+ u8 offset = (((insn >> 8) & 0xf) << 4) | (insn & 0xf);
const char *opname = "ldr";
if (is_load == 0)
@@ -548,78 +758,78 @@ std::string ARM_Disasm::DisassembleMemHalf(uint32_t insn)
}
}
-std::string ARM_Disasm::DisassembleMCR(Opcode opcode, uint32_t insn)
+std::string ARM_Disasm::DisassembleMCR(Opcode opcode, u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t crn = (insn >> 16) & 0xf;
- uint8_t crd = (insn >> 12) & 0xf;
- uint8_t cpnum = (insn >> 8) & 0xf;
- uint8_t opcode2 = (insn >> 5) & 0x7;
- uint8_t crm = insn & 0xf;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 crn = (insn >> 16) & 0xf;
+ u8 crd = (insn >> 12) & 0xf;
+ u8 cpnum = (insn >> 8) & 0xf;
+ u8 opcode2 = (insn >> 5) & 0x7;
+ u8 crm = insn & 0xf;
const char *opname = opcode_names[opcode];
return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}",
opname, cond_to_str(cond), cpnum, crd, crn, crm, opcode2);
}
-std::string ARM_Disasm::DisassembleMLA(Opcode opcode, uint32_t insn)
+std::string ARM_Disasm::DisassembleMLA(Opcode opcode, u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t rd = (insn >> 16) & 0xf;
- uint8_t rn = (insn >> 12) & 0xf;
- uint8_t rs = (insn >> 8) & 0xf;
- uint8_t rm = insn & 0xf;
- uint8_t bit_s = (insn >> 20) & 1;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 rd = (insn >> 16) & 0xf;
+ u8 rn = (insn >> 12) & 0xf;
+ u8 rs = (insn >> 8) & 0xf;
+ u8 rm = insn & 0xf;
+ u8 bit_s = (insn >> 20) & 1;
const char *opname = opcode_names[opcode];
return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs, rn);
}
-std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, uint32_t insn)
+std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t rdhi = (insn >> 16) & 0xf;
- uint8_t rdlo = (insn >> 12) & 0xf;
- uint8_t rs = (insn >> 8) & 0xf;
- uint8_t rm = insn & 0xf;
- uint8_t bit_s = (insn >> 20) & 1;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 rdhi = (insn >> 16) & 0xf;
+ u8 rdlo = (insn >> 12) & 0xf;
+ u8 rs = (insn >> 8) & 0xf;
+ u8 rm = insn & 0xf;
+ u8 bit_s = (insn >> 20) & 1;
const char *opname = opcode_names[opcode];
return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
opname, cond_to_str(cond), bit_s ? "s" : "", rdlo, rdhi, rm, rs);
}
-std::string ARM_Disasm::DisassembleMUL(Opcode opcode, uint32_t insn)
+std::string ARM_Disasm::DisassembleMUL(Opcode opcode, u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t rd = (insn >> 16) & 0xf;
- uint8_t rs = (insn >> 8) & 0xf;
- uint8_t rm = insn & 0xf;
- uint8_t bit_s = (insn >> 20) & 1;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 rd = (insn >> 16) & 0xf;
+ u8 rs = (insn >> 8) & 0xf;
+ u8 rm = insn & 0xf;
+ u8 bit_s = (insn >> 20) & 1;
const char *opname = opcode_names[opcode];
return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d",
opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs);
}
-std::string ARM_Disasm::DisassembleMRS(uint32_t insn)
+std::string ARM_Disasm::DisassembleMRS(u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t rd = (insn >> 12) & 0xf;
- uint8_t ps = (insn >> 22) & 1;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 rd = (insn >> 12) & 0xf;
+ u8 ps = (insn >> 22) & 1;
return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
}
-std::string ARM_Disasm::DisassembleMSR(uint32_t insn)
+std::string ARM_Disasm::DisassembleMSR(u32 insn)
{
char flags[8];
int flag_index = 0;
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t is_immed = (insn >> 25) & 0x1;
- uint8_t pd = (insn >> 22) & 1;
- uint8_t mask = (insn >> 16) & 0xf;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 is_immed = (insn >> 25) & 0x1;
+ u8 pd = (insn >> 22) & 1;
+ u8 mask = (insn >> 16) & 0xf;
if (mask & 1)
flags[flag_index++] = 'c';
@@ -632,36 +842,76 @@ std::string ARM_Disasm::DisassembleMSR(uint32_t insn)
flags[flag_index] = 0;
if (is_immed) {
- uint32_t immed = insn & 0xff;
- uint8_t rotate = (insn >> 8) & 0xf;
- uint8_t rotate2 = rotate << 1;
- uint32_t rotated_val = (immed >> rotate2) | (immed << (32 - rotate2));
+ u32 immed = insn & 0xff;
+ u8 rotate = (insn >> 8) & 0xf;
+ u8 rotate2 = rotate << 1;
+ u32 rotated_val = (immed >> rotate2) | (immed << (32 - rotate2));
return Common::StringFromFormat("msr%s\t%s_%s, #0x%x",
cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rotated_val);
}
- uint8_t rm = insn & 0xf;
+ u8 rm = insn & 0xf;
return Common::StringFromFormat("msr%s\t%s_%s, r%d",
cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm);
}
-std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
+std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, u32 insn)
+{
+ u32 cond = BITS(insn, 28, 31);
+ return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond));
+}
+
+std::string ARM_Disasm::DisassembleParallelAddSub(Opcode opcode, u32 insn) {
+ u32 cond = BITS(insn, 28, 31);
+ u32 rn = BITS(insn, 16, 19);
+ u32 rd = BITS(insn, 12, 15);
+ u32 rm = BITS(insn, 0, 3);
+
+ return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[opcode], cond_to_str(cond),
+ rd, rn, rm);
+}
+
+std::string ARM_Disasm::DisassemblePKH(u32 insn)
+{
+ u32 cond = BITS(insn, 28, 31);
+ u32 rn = BITS(insn, 16, 19);
+ u32 rd = BITS(insn, 12, 15);
+ u32 imm5 = BITS(insn, 7, 11);
+ u32 tb = BIT(insn, 6);
+ u32 rm = BITS(insn, 0, 3);
+
+ std::string suffix = tb ? "tb" : "bt";
+ std::string shift = "";
+
+ if (tb && imm5 == 0)
+ imm5 = 32;
+
+ if (imm5 > 0) {
+ shift = tb ? ", ASR" : ", LSL";
+ shift += " #" + std::to_string(imm5);
+ }
+
+ return Common::StringFromFormat("pkh%s%s\tr%u, r%u, r%u%s", suffix.c_str(), cond_to_str(cond),
+ rd, rn, rm, shift.c_str());
+}
+
+std::string ARM_Disasm::DisassemblePLD(u32 insn)
{
- uint8_t is_reg = (insn >> 25) & 0x1;
- uint8_t is_up = (insn >> 23) & 0x1;
- uint8_t rn = (insn >> 16) & 0xf;
+ u8 is_reg = (insn >> 25) & 0x1;
+ u8 is_up = (insn >> 23) & 0x1;
+ u8 rn = (insn >> 16) & 0xf;
const char *minus = "";
if (is_up == 0)
minus = "-";
if (is_reg) {
- uint8_t rm = insn & 0xf;
+ u8 rm = insn & 0xf;
return Common::StringFromFormat("pld\t[r%d, %sr%d]", rn, minus, rm);
}
- uint16_t offset = insn & 0xfff;
+ u16 offset = insn & 0xfff;
if (offset == 0) {
return Common::StringFromFormat("pld\t[r%d]", rn);
} else {
@@ -669,27 +919,128 @@ std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
}
}
-std::string ARM_Disasm::DisassembleSWI(uint32_t insn)
+std::string ARM_Disasm::DisassembleREV(Opcode opcode, u32 insn) {
+ u32 cond = BITS(insn, 28, 31);
+ u32 rd = BITS(insn, 12, 15);
+ u32 rm = BITS(insn, 0, 3);
+
+ return Common::StringFromFormat("%s%s\tr%u, r%u", opcode_names[opcode], cond_to_str(cond),
+ rd, rm);
+}
+
+std::string ARM_Disasm::DisassembleREX(Opcode opcode, u32 insn) {
+ u32 rn = BITS(insn, 16, 19);
+ u32 rd = BITS(insn, 12, 15);
+ u32 rt = BITS(insn, 0, 3);
+ u32 cond = BITS(insn, 28, 31);
+
+ switch (opcode) {
+ case OP_STREX:
+ case OP_STREXB:
+ case OP_STREXH:
+ return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
+ cond_to_str(cond), rd, rt, rn);
+ case OP_STREXD:
+ return Common::StringFromFormat("%s%s\tr%d, r%d, r%d, [r%d]", opcode_names[opcode],
+ cond_to_str(cond), rd, rt, rt + 1, rn);
+
+ // for LDREX instructions, rd corresponds to Rt from reference manual
+ case OP_LDREX:
+ case OP_LDREXB:
+ case OP_LDREXH:
+ return Common::StringFromFormat("%s%s\tr%d, [r%d]", opcode_names[opcode],
+ cond_to_str(cond), rd, rn);
+ case OP_LDREXD:
+ return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
+ cond_to_str(cond), rd, rd + 1, rn);
+ default:
+ return opcode_names[OP_UNDEFINED];
+ }
+}
+
+std::string ARM_Disasm::DisassembleSAT(Opcode opcode, u32 insn) {
+ u32 cond = BITS(insn, 28, 31);
+ u32 sat_imm = BITS(insn, 16, 20);
+ u32 rd = BITS(insn, 12, 15);
+ u32 imm5 = BITS(insn, 7, 11);
+ u32 sh = BIT(insn, 6);
+ u32 rn = BITS(insn, 0, 3);
+
+ std::string shift_part = "";
+ bool opcode_has_shift = (opcode == OP_SSAT) || (opcode == OP_USAT);
+ if (opcode_has_shift && !(sh == 0 && imm5 == 0)) {
+ if (sh == 0)
+ shift_part += ", LSL #";
+ else
+ shift_part += ", ASR #";
+
+ if (imm5 == 0)
+ imm5 = 32;
+ shift_part += std::to_string(imm5);
+ }
+
+ if (opcode == OP_SSAT || opcode == OP_SSAT16)
+ sat_imm++;
+
+ return Common::StringFromFormat("%s%s\tr%u, #%u, r%u%s", opcode_names[opcode], cond_to_str(cond), rd,
+ sat_imm, rn, shift_part.c_str());
+}
+
+std::string ARM_Disasm::DisassembleSEL(u32 insn) {
+ u32 cond = BITS(insn, 28, 31);
+ u32 rn = BITS(insn, 16, 19);
+ u32 rd = BITS(insn, 12, 15);
+ u32 rm = BITS(insn, 0, 3);
+
+ return Common::StringFromFormat("%s%s\tr%u, r%u, r%u", opcode_names[OP_SEL], cond_to_str(cond),
+ rd, rn, rm);
+}
+
+std::string ARM_Disasm::DisassembleSWI(u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint32_t sysnum = insn & 0x00ffffff;
+ u8 cond = (insn >> 28) & 0xf;
+ u32 sysnum = insn & 0x00ffffff;
return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum);
}
-std::string ARM_Disasm::DisassembleSWP(Opcode opcode, uint32_t insn)
+std::string ARM_Disasm::DisassembleSWP(Opcode opcode, u32 insn)
{
- uint8_t cond = (insn >> 28) & 0xf;
- uint8_t rn = (insn >> 16) & 0xf;
- uint8_t rd = (insn >> 12) & 0xf;
- uint8_t rm = insn & 0xf;
+ u8 cond = (insn >> 28) & 0xf;
+ u8 rn = (insn >> 16) & 0xf;
+ u8 rd = (insn >> 12) & 0xf;
+ u8 rm = insn & 0xf;
const char *opname = opcode_names[opcode];
return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
}
-Opcode ARM_Disasm::Decode(uint32_t insn) {
- uint32_t bits27_26 = (insn >> 26) & 0x3;
+std::string ARM_Disasm::DisassembleXT(Opcode opcode, u32 insn)
+{
+ u32 cond = BITS(insn, 28, 31);
+ u32 rn = BITS(insn, 16, 19);
+ u32 rd = BITS(insn, 12, 15);
+ u32 rotate = BITS(insn, 10, 11);
+ u32 rm = BITS(insn, 0, 3);
+
+ std::string rn_part = "";
+ static std::unordered_set<Opcode, std::hash<int>> extend_with_add = {
+ OP_SXTAB, OP_SXTAB16, OP_SXTAH,
+ OP_UXTAB, OP_UXTAB16, OP_UXTAH
+ };
+ if (extend_with_add.find(opcode) != extend_with_add.end())
+ rn_part = ", r" + std::to_string(rn);
+
+ std::string rotate_part = "";
+ if (rotate != 0)
+ rotate_part = ", ROR #" + std::to_string(rotate << 3);
+
+ return Common::StringFromFormat("%s%s\tr%u%s, r%u%s", opcode_names[opcode], cond_to_str(cond),
+ rd, rn_part.c_str(), rm, rotate_part.c_str());
+}
+
+Opcode ARM_Disasm::Decode(u32 insn) {
+ u32 bits27_26 = (insn >> 26) & 0x3;
switch (bits27_26) {
case 0x0:
return Decode00(insn);
@@ -703,9 +1054,9 @@ Opcode ARM_Disasm::Decode(uint32_t insn) {
return OP_INVALID;
}
-Opcode ARM_Disasm::Decode00(uint32_t insn) {
- uint8_t bit25 = (insn >> 25) & 0x1;
- uint8_t bit4 = (insn >> 4) & 0x1;
+Opcode ARM_Disasm::Decode00(u32 insn) {
+ u8 bit25 = (insn >> 25) & 0x1;
+ u8 bit4 = (insn >> 4) & 0x1;
if (bit25 == 0 && bit4 == 1) {
if ((insn & 0x0ffffff0) == 0x012fff10) {
// Bx instruction
@@ -719,41 +1070,48 @@ Opcode ARM_Disasm::Decode00(uint32_t insn) {
// Bkpt instruction
return OP_BKPT;
}
- uint32_t bits7_4 = (insn >> 4) & 0xf;
+ u32 bits7_4 = (insn >> 4) & 0xf;
if (bits7_4 == 0x9) {
- if ((insn & 0x0ff00ff0) == 0x01000090) {
- // Swp instruction
- uint8_t bit22 = (insn >> 22) & 0x1;
- if (bit22)
- return OP_SWPB;
- return OP_SWP;
+ u32 bit24 = BIT(insn, 24);
+ if (bit24) {
+ return DecodeSyncPrimitive(insn);
}
// One of the multiply instructions
return DecodeMUL(insn);
}
- uint8_t bit7 = (insn >> 7) & 0x1;
+ u8 bit7 = (insn >> 7) & 0x1;
if (bit7 == 1) {
// One of the load/store halfword/byte instructions
return DecodeLDRH(insn);
}
}
+ u32 op1 = BITS(insn, 20, 24);
+ if (bit25 && (op1 == 0x12 || op1 == 0x16)) {
+ // One of the MSR (immediate) and hints instructions
+ return DecodeMSRImmAndHints(insn);
+ }
+
// One of the data processing instructions
return DecodeALU(insn);
}
-Opcode ARM_Disasm::Decode01(uint32_t insn) {
- uint8_t is_reg = (insn >> 25) & 0x1;
- uint8_t bit4 = (insn >> 4) & 0x1;
+Opcode ARM_Disasm::Decode01(u32 insn) {
+ u8 is_reg = (insn >> 25) & 0x1;
+ u8 bit4 = (insn >> 4) & 0x1;
if (is_reg == 1 && bit4 == 1)
- return OP_UNDEFINED;
- uint8_t is_load = (insn >> 20) & 0x1;
- uint8_t is_byte = (insn >> 22) & 0x1;
+ return DecodeMedia(insn);
+ u8 is_load = (insn >> 20) & 0x1;
+ u8 is_byte = (insn >> 22) & 0x1;
if ((insn & 0xfd70f000) == 0xf550f000) {
// Pre-load
return OP_PLD;
}
+ if (insn == 0xf57ff01f) {
+ // Clear-Exclusive
+ return OP_CLREX;
+ }
if (is_load) {
if (is_byte) {
// Load byte
@@ -770,36 +1128,28 @@ Opcode ARM_Disasm::Decode01(uint32_t insn) {
return OP_STR;
}
-Opcode ARM_Disasm::Decode10(uint32_t insn) {
- uint8_t bit25 = (insn >> 25) & 0x1;
+Opcode ARM_Disasm::Decode10(u32 insn) {
+ u8 bit25 = (insn >> 25) & 0x1;
if (bit25 == 0) {
// LDM/STM
- uint8_t is_load = (insn >> 20) & 0x1;
+ u8 is_load = (insn >> 20) & 0x1;
if (is_load)
return OP_LDM;
return OP_STM;
}
- // Branch or Branch with link
- uint8_t is_link = (insn >> 24) & 1;
- uint32_t offset = insn & 0xffffff;
- // Sign-extend the 24-bit offset
- if ((offset >> 23) & 1)
- offset |= 0xff000000;
+ // Branch with link
+ if ((insn >> 24) & 1)
+ return OP_BL;
- // Pre-compute the left-shift and the prefetch offset
- offset <<= 2;
- offset += 8;
- if (is_link == 0)
- return OP_B;
- return OP_BL;
+ return OP_B;
}
-Opcode ARM_Disasm::Decode11(uint32_t insn) {
- uint8_t bit25 = (insn >> 25) & 0x1;
+Opcode ARM_Disasm::Decode11(u32 insn) {
+ u8 bit25 = (insn >> 25) & 0x1;
if (bit25 == 0) {
// LDC, SDC
- uint8_t is_load = (insn >> 20) & 0x1;
+ u8 is_load = (insn >> 20) & 0x1;
if (is_load) {
// LDC
return OP_LDC;
@@ -808,18 +1158,18 @@ Opcode ARM_Disasm::Decode11(uint32_t insn) {
return OP_STC;
}
- uint8_t bit24 = (insn >> 24) & 0x1;
+ u8 bit24 = (insn >> 24) & 0x1;
if (bit24 == 0x1) {
// SWI
return OP_SWI;
}
- uint8_t bit4 = (insn >> 4) & 0x1;
- uint8_t cpnum = (insn >> 8) & 0xf;
+ u8 bit4 = (insn >> 4) & 0x1;
+ u8 cpnum = (insn >> 8) & 0xf;
if (cpnum == 15) {
// Special case for coprocessor 15
- uint8_t opcode = (insn >> 21) & 0x7;
+ u8 opcode = (insn >> 21) & 0x7;
if (bit4 == 0 || opcode != 0) {
// This is an unexpected bit pattern. Create an undefined
// instruction in case this is ever executed.
@@ -827,7 +1177,7 @@ Opcode ARM_Disasm::Decode11(uint32_t insn) {
}
// MRC, MCR
- uint8_t is_mrc = (insn >> 20) & 0x1;
+ u8 is_mrc = (insn >> 20) & 0x1;
if (is_mrc)
return OP_MRC;
return OP_MCR;
@@ -838,22 +1188,165 @@ Opcode ARM_Disasm::Decode11(uint32_t insn) {
return OP_CDP;
}
// MRC, MCR
- uint8_t is_mrc = (insn >> 20) & 0x1;
+ u8 is_mrc = (insn >> 20) & 0x1;
if (is_mrc)
return OP_MRC;
return OP_MCR;
}
-Opcode ARM_Disasm::DecodeMUL(uint32_t insn) {
- uint8_t bit24 = (insn >> 24) & 0x1;
+Opcode ARM_Disasm::DecodeSyncPrimitive(u32 insn) {
+ u32 op = BITS(insn, 20, 23);
+ u32 bit22 = BIT(insn, 22);
+ switch (op) {
+ case 0x0:
+ if (bit22)
+ return OP_SWPB;
+ return OP_SWP;
+ case 0x8:
+ return OP_STREX;
+ case 0x9:
+ return OP_LDREX;
+ case 0xA:
+ return OP_STREXD;
+ case 0xB:
+ return OP_LDREXD;
+ case 0xC:
+ return OP_STREXB;
+ case 0xD:
+ return OP_LDREXB;
+ case 0xE:
+ return OP_STREXH;
+ case 0xF:
+ return OP_LDREXH;
+ default:
+ return OP_UNDEFINED;
+ }
+}
+
+Opcode ARM_Disasm::DecodeParallelAddSub(u32 insn) {
+ u32 op1 = BITS(insn, 20, 21);
+ u32 op2 = BITS(insn, 5, 7);
+ u32 is_unsigned = BIT(insn, 22);
+
+ if (op1 == 0x0 || op2 == 0x5 || op2 == 0x6)
+ return OP_UNDEFINED;
+
+ // change op1 range from [1, 3] to range [0, 2]
+ op1--;
+
+ // change op2 range from [0, 4] U {7} to range [0, 5]
+ if (op2 == 0x7)
+ op2 = 0x5;
+
+ static std::vector<Opcode> opcodes = {
+ // op1 = 0
+ OP_SADD16, OP_UADD16,
+ OP_SASX, OP_UASX,
+ OP_SSAX, OP_USAX,
+ OP_SSUB16, OP_USUB16,
+ OP_SADD8, OP_UADD8,
+ OP_SSUB8, OP_USUB8,
+ // op1 = 1
+ OP_QADD16, OP_UQADD16,
+ OP_QASX, OP_UQASX,
+ OP_QSAX, OP_UQSAX,
+ OP_QSUB16, OP_UQSUB16,
+ OP_QADD8, OP_UQADD8,
+ OP_QSUB8, OP_UQSUB8,
+ // op1 = 2
+ OP_SHADD16, OP_UHADD16,
+ OP_SHASX, OP_UHASX,
+ OP_SHSAX, OP_UHSAX,
+ OP_SHSUB16, OP_UHSUB16,
+ OP_SHADD8, OP_UHADD8,
+ OP_SHSUB8, OP_UHSUB8
+ };
+
+ u32 opcode_index = op1 * 12 + op2 * 2 + is_unsigned;
+ return opcodes[opcode_index];
+}
+
+Opcode ARM_Disasm::DecodePackingSaturationReversal(u32 insn) {
+ u32 op1 = BITS(insn, 20, 22);
+ u32 a = BITS(insn, 16, 19);
+ u32 op2 = BITS(insn, 5, 7);
+
+ switch (op1) {
+ case 0x0:
+ if (BIT(op2, 0) == 0)
+ return OP_PKH;
+ if (op2 == 0x3 && a != 0xf)
+ return OP_SXTAB16;
+ if (op2 == 0x3 && a == 0xf)
+ return OP_SXTB16;
+ if (op2 == 0x5)
+ return OP_SEL;
+ break;
+ case 0x2:
+ if (BIT(op2, 0) == 0)
+ return OP_SSAT;
+ if (op2 == 0x1)
+ return OP_SSAT16;
+ if (op2 == 0x3 && a != 0xf)
+ return OP_SXTAB;
+ if (op2 == 0x3 && a == 0xf)
+ return OP_SXTB;
+ break;
+ case 0x3:
+ if (op2 == 0x1)
+ return OP_REV;
+ if (BIT(op2, 0) == 0)
+ return OP_SSAT;
+ if (op2 == 0x3 && a != 0xf)
+ return OP_SXTAH;
+ if (op2 == 0x3 && a == 0xf)
+ return OP_SXTH;
+ if (op2 == 0x5)
+ return OP_REV16;
+ break;
+ case 0x4:
+ if (op2 == 0x3 && a != 0xf)
+ return OP_UXTAB16;
+ if (op2 == 0x3 && a == 0xf)
+ return OP_UXTB16;
+ break;
+ case 0x6:
+ if (BIT(op2, 0) == 0)
+ return OP_USAT;
+ if (op2 == 0x1)
+ return OP_USAT16;
+ if (op2 == 0x3 && a != 0xf)
+ return OP_UXTAB;
+ if (op2 == 0x3 && a == 0xf)
+ return OP_UXTB;
+ break;
+ case 0x7:
+ if (BIT(op2, 0) == 0)
+ return OP_USAT;
+ if (op2 == 0x3 && a != 0xf)
+ return OP_UXTAH;
+ if (op2 == 0x3 && a == 0xf)
+ return OP_UXTH;
+ if (op2 == 0x5)
+ return OP_REVSH;
+ break;
+ default:
+ break;
+ }
+
+ return OP_UNDEFINED;
+}
+
+Opcode ARM_Disasm::DecodeMUL(u32 insn) {
+ u8 bit24 = (insn >> 24) & 0x1;
if (bit24 != 0) {
// This is an unexpected bit pattern. Create an undefined
// instruction in case this is ever executed.
return OP_UNDEFINED;
}
- uint8_t bit23 = (insn >> 23) & 0x1;
- uint8_t bit22_U = (insn >> 22) & 0x1;
- uint8_t bit21_A = (insn >> 21) & 0x1;
+ u8 bit23 = (insn >> 23) & 0x1;
+ u8 bit22_U = (insn >> 22) & 0x1;
+ u8 bit21_A = (insn >> 21) & 0x1;
if (bit23 == 0) {
// 32-bit multiply
if (bit22_U != 0) {
@@ -878,9 +1371,104 @@ Opcode ARM_Disasm::DecodeMUL(uint32_t insn) {
return OP_SMLAL;
}
-Opcode ARM_Disasm::DecodeLDRH(uint32_t insn) {
- uint8_t is_load = (insn >> 20) & 0x1;
- uint8_t bits_65 = (insn >> 5) & 0x3;
+Opcode ARM_Disasm::DecodeMSRImmAndHints(u32 insn) {
+ u32 op = BIT(insn, 22);
+ u32 op1 = BITS(insn, 16, 19);
+ u32 op2 = BITS(insn, 0, 7);
+
+ if (op == 0 && op1 == 0) {
+ switch (op2) {
+ case 0x0:
+ return OP_NOP;
+ case 0x1:
+ return OP_YIELD;
+ case 0x2:
+ return OP_WFE;
+ case 0x3:
+ return OP_WFI;
+ case 0x4:
+ return OP_SEV;
+ default:
+ return OP_UNDEFINED;
+ }
+ }
+
+ return OP_MSR;
+}
+
+Opcode ARM_Disasm::DecodeMediaMulDiv(u32 insn) {
+ u32 op1 = BITS(insn, 20, 22);
+ u32 op2_h = BITS(insn, 6, 7);
+ u32 a = BITS(insn, 12, 15);
+
+ switch (op1) {
+ case 0x0:
+ if (op2_h == 0x0) {
+ if (a != 0xf)
+ return OP_SMLAD;
+ else
+ return OP_SMUAD;
+ } else if (op2_h == 0x1) {
+ if (a != 0xf)
+ return OP_SMLSD;
+ else
+ return OP_SMUSD;
+ }
+ break;
+ case 0x4:
+ if (op2_h == 0x0)
+ return OP_SMLALD;
+ else if (op2_h == 0x1)
+ return OP_SMLSLD;
+ break;
+ case 0x5:
+ if (op2_h == 0x0) {
+ if (a != 0xf)
+ return OP_SMMLA;
+ else
+ return OP_SMMUL;
+ } else if (op2_h == 0x3) {
+ return OP_SMMLS;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return OP_UNDEFINED;
+}
+
+Opcode ARM_Disasm::DecodeMedia(u32 insn) {
+ u32 op1 = BITS(insn, 20, 24);
+ u32 rd = BITS(insn, 12, 15);
+ u32 op2 = BITS(insn, 5, 7);
+
+ switch (BITS(op1, 3, 4)) {
+ case 0x0:
+ // unsigned and signed parallel addition and subtraction
+ return DecodeParallelAddSub(insn);
+ case 0x1:
+ // Packing, unpacking, saturation, and reversal
+ return DecodePackingSaturationReversal(insn);
+ case 0x2:
+ // Signed multiply, signed and unsigned divide
+ return DecodeMediaMulDiv(insn);
+ case 0x3:
+ if (op2 == 0 && rd == 0xf)
+ return OP_USAD8;
+ if (op2 == 0 && rd != 0xf)
+ return OP_USADA8;
+ break;
+ default:
+ break;
+ }
+
+ return OP_UNDEFINED;
+}
+
+Opcode ARM_Disasm::DecodeLDRH(u32 insn) {
+ u8 is_load = (insn >> 20) & 0x1;
+ u8 bits_65 = (insn >> 5) & 0x3;
if (is_load) {
if (bits_65 == 0x1) {
// Load unsigned halfword
@@ -908,12 +1496,12 @@ Opcode ARM_Disasm::DecodeLDRH(uint32_t insn) {
return OP_STRH;
}
-Opcode ARM_Disasm::DecodeALU(uint32_t insn) {
- uint8_t is_immed = (insn >> 25) & 0x1;
- uint8_t opcode = (insn >> 21) & 0xf;
- uint8_t bit_s = (insn >> 20) & 1;
- uint8_t shift_is_reg = (insn >> 4) & 1;
- uint8_t bit7 = (insn >> 7) & 1;
+Opcode ARM_Disasm::DecodeALU(u32 insn) {
+ u8 is_immed = (insn >> 25) & 0x1;
+ u8 opcode = (insn >> 21) & 0xf;
+ u8 bit_s = (insn >> 20) & 1;
+ u8 shift_is_reg = (insn >> 4) & 1;
+ u8 bit7 = (insn >> 7) & 1;
if (!is_immed && shift_is_reg && (bit7 != 0)) {
// This is an unexpected bit pattern. Create an undefined
// instruction in case this is ever executed.
diff --git a/src/core/arm/disassembler/arm_disasm.h b/src/core/arm/disassembler/arm_disasm.h
index f94bd4669..53d9c6a74 100644
--- a/src/core/arm/disassembler/arm_disasm.h
+++ b/src/core/arm/disassembler/arm_disasm.h
@@ -2,9 +2,10 @@
#pragma once
-#include <cstdint>
#include <string>
+#include "common/common_types.h"
+
// Note: this list of opcodes must match the list used to initialize
// the opflags[] array in opcode.cpp.
enum Opcode {
@@ -20,6 +21,7 @@ enum Opcode {
OP_BLX,
OP_BX,
OP_CDP,
+ OP_CLREX,
OP_CLZ,
OP_CMN,
OP_CMP,
@@ -29,6 +31,10 @@ enum Opcode {
OP_LDR,
OP_LDRB,
OP_LDRBT,
+ OP_LDREX,
+ OP_LDREXB,
+ OP_LDREXD,
+ OP_LDREXH,
OP_LDRH,
OP_LDRSB,
OP_LDRSH,
@@ -41,28 +47,105 @@ enum Opcode {
OP_MSR,
OP_MUL,
OP_MVN,
+ OP_NOP,
OP_ORR,
+ OP_PKH,
OP_PLD,
+ OP_QADD16,
+ OP_QADD8,
+ OP_QASX,
+ OP_QSAX,
+ OP_QSUB16,
+ OP_QSUB8,
+ OP_REV,
+ OP_REV16,
+ OP_REVSH,
OP_RSB,
OP_RSC,
+ OP_SADD16,
+ OP_SADD8,
+ OP_SASX,
OP_SBC,
+ OP_SEL,
+ OP_SEV,
+ OP_SHADD16,
+ OP_SHADD8,
+ OP_SHASX,
+ OP_SHSAX,
+ OP_SHSUB16,
+ OP_SHSUB8,
+ OP_SMLAD,
OP_SMLAL,
+ OP_SMLALD,
+ OP_SMLSD,
+ OP_SMLSLD,
+ OP_SMMLA,
+ OP_SMMLS,
+ OP_SMMUL,
+ OP_SMUAD,
OP_SMULL,
+ OP_SMUSD,
+ OP_SSAT,
+ OP_SSAT16,
+ OP_SSAX,
+ OP_SSUB16,
+ OP_SSUB8,
OP_STC,
OP_STM,
OP_STR,
OP_STRB,
OP_STRBT,
+ OP_STREX,
+ OP_STREXB,
+ OP_STREXD,
+ OP_STREXH,
OP_STRH,
OP_STRT,
OP_SUB,
OP_SWI,
OP_SWP,
OP_SWPB,
+ OP_SXTAB,
+ OP_SXTAB16,
+ OP_SXTAH,
+ OP_SXTB,
+ OP_SXTB16,
+ OP_SXTH,
OP_TEQ,
OP_TST,
+ OP_UADD16,
+ OP_UADD8,
+ OP_UASX,
+ OP_UHADD16,
+ OP_UHADD8,
+ OP_UHASX,
+ OP_UHSAX,
+ OP_UHSUB16,
+ OP_UHSUB8,
OP_UMLAL,
OP_UMULL,
+ OP_UQADD16,
+ OP_UQADD8,
+ OP_UQASX,
+ OP_UQSAX,
+ OP_UQSUB16,
+ OP_UQSUB8,
+ OP_USAD8,
+ OP_USADA8,
+ OP_USAT,
+ OP_USAT16,
+ OP_USAX,
+ OP_USUB16,
+ OP_USUB8,
+ OP_UXTAB,
+ OP_UXTAB16,
+ OP_UXTAH,
+ OP_UXTB,
+ OP_UXTB16,
+ OP_UXTH,
+ OP_WFE,
+ OP_WFI,
+ OP_YIELD,
// Define thumb opcodes
OP_THUMB_UNDEFINED,
@@ -109,33 +192,48 @@ enum Opcode {
class ARM_Disasm {
public:
- static std::string Disassemble(uint32_t addr, uint32_t insn);
- static Opcode Decode(uint32_t insn);
+ static std::string Disassemble(u32 addr, u32 insn);
+ static Opcode Decode(u32 insn);
private:
- static Opcode Decode00(uint32_t insn);
- static Opcode Decode01(uint32_t insn);
- static Opcode Decode10(uint32_t insn);
- static Opcode Decode11(uint32_t insn);
- static Opcode DecodeMUL(uint32_t insn);
- static Opcode DecodeLDRH(uint32_t insn);
- static Opcode DecodeALU(uint32_t insn);
+ static Opcode Decode00(u32 insn);
+ static Opcode Decode01(u32 insn);
+ static Opcode Decode10(u32 insn);
+ static Opcode Decode11(u32 insn);
+ static Opcode DecodeSyncPrimitive(u32 insn);
+ static Opcode DecodeParallelAddSub(u32 insn);
+ static Opcode DecodePackingSaturationReversal(u32 insn);
+ static Opcode DecodeMUL(u32 insn);
+ static Opcode DecodeMSRImmAndHints(u32 insn);
+ static Opcode DecodeMediaMulDiv(u32 insn);
+ static Opcode DecodeMedia(u32 insn);
+ static Opcode DecodeLDRH(u32 insn);
+ static Opcode DecodeALU(u32 insn);
- static std::string DisassembleALU(Opcode opcode, uint32_t insn);
- static std::string DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t insn);
- static std::string DisassembleBX(uint32_t insn);
- static std::string DisassembleBKPT(uint32_t insn);
- static std::string DisassembleCLZ(uint32_t insn);
- static std::string DisassembleMemblock(Opcode opcode, uint32_t insn);
- static std::string DisassembleMem(uint32_t insn);
- static std::string DisassembleMemHalf(uint32_t insn);
- static std::string DisassembleMCR(Opcode opcode, uint32_t insn);
- static std::string DisassembleMLA(Opcode opcode, uint32_t insn);
- static std::string DisassembleUMLAL(Opcode opcode, uint32_t insn);
- static std::string DisassembleMUL(Opcode opcode, uint32_t insn);
- static std::string DisassembleMRS(uint32_t insn);
- static std::string DisassembleMSR(uint32_t insn);
- static std::string DisassemblePLD(uint32_t insn);
- static std::string DisassembleSWI(uint32_t insn);
- static std::string DisassembleSWP(Opcode opcode, uint32_t insn);
+ static std::string DisassembleALU(Opcode opcode, u32 insn);
+ static std::string DisassembleBranch(u32 addr, Opcode opcode, u32 insn);
+ static std::string DisassembleBX(u32 insn);
+ static std::string DisassembleBKPT(u32 insn);
+ static std::string DisassembleCLZ(u32 insn);
+ static std::string DisassembleMediaMulDiv(Opcode opcode, u32 insn);
+ static std::string DisassembleMemblock(Opcode opcode, u32 insn);
+ static std::string DisassembleMem(u32 insn);
+ static std::string DisassembleMemHalf(u32 insn);
+ static std::string DisassembleMCR(Opcode opcode, u32 insn);
+ static std::string DisassembleMLA(Opcode opcode, u32 insn);
+ static std::string DisassembleUMLAL(Opcode opcode, u32 insn);
+ static std::string DisassembleMUL(Opcode opcode, u32 insn);
+ static std::string DisassembleMRS(u32 insn);
+ static std::string DisassembleMSR(u32 insn);
+ static std::string DisassembleNoOperands(Opcode opcode, u32 insn);
+ static std::string DisassembleParallelAddSub(Opcode opcode, u32 insn);
+ static std::string DisassemblePKH(u32 insn);
+ static std::string DisassemblePLD(u32 insn);
+ static std::string DisassembleREV(Opcode opcode, u32 insn);
+ static std::string DisassembleREX(Opcode opcode, u32 insn);
+ static std::string DisassembleSAT(Opcode opcode, u32 insn);
+ static std::string DisassembleSEL(u32 insn);
+ static std::string DisassembleSWI(u32 insn);
+ static std::string DisassembleSWP(Opcode opcode, u32 insn);
+ static std::string DisassembleXT(Opcode opcode, u32 insn);
};
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index c665f706f..f3be2c857 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -40,6 +40,22 @@ void ARM_DynCom::SetReg(int index, u32 value) {
state->Reg[index] = value;
}
+u32 ARM_DynCom::GetVFPReg(int index) const {
+ return state->ExtReg[index];
+}
+
+void ARM_DynCom::SetVFPReg(int index, u32 value) {
+ state->ExtReg[index] = value;
+}
+
+u32 ARM_DynCom::GetVFPSystemReg(VFPSystemRegister reg) const {
+ return state->VFP[reg];
+}
+
+void ARM_DynCom::SetVFPSystemReg(VFPSystemRegister reg, u32 value) {
+ state->VFP[reg] = value;
+}
+
u32 ARM_DynCom::GetCPSR() const {
return state->Cpsr;
}
diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h
index 87ab6908a..3664fd728 100644
--- a/src/core/arm/dyncom/arm_dyncom.h
+++ b/src/core/arm/dyncom/arm_dyncom.h
@@ -25,6 +25,10 @@ public:
u32 GetPC() const override;
u32 GetReg(int index) const override;
void SetReg(int index, u32 value) override;
+ u32 GetVFPReg(int index) const override;
+ void SetVFPReg(int index, u32 value) override;
+ u32 GetVFPSystemReg(VFPSystemRegister reg) const override;
+ void SetVFPSystemReg(VFPSystemRegister reg, u32 value) override;
u32 GetCPSR() const override;
void SetCPSR(u32 cpsr) override;
u32 GetCP15Register(CP15Register reg) override;
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index b88b74752..422e80b50 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -7,6 +7,7 @@
#include <algorithm>
#include <cstdio>
+#include "common/common_types.h"
#include "common/logging/log.h"
#include "common/profiler.h"
@@ -759,8 +760,8 @@ struct bx_inst {
struct blx_inst {
union {
- int32_t signed_immed_24;
- uint32_t Rm;
+ s32 signed_immed_24;
+ u32 Rm;
} val;
unsigned int inst;
};
@@ -3544,7 +3545,7 @@ static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
size++;
// If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction
if (cpu->TFlag) {
- uint32_t arm_inst;
+ u32 arm_inst;
ThumbDecodeStatus state = DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base);
// We have translated the Thumb branch instruction in the Thumb decoder
@@ -4215,8 +4216,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
CPS_INST:
{
cps_inst *inst_cream = (cps_inst *)inst_base->component;
- uint32_t aif_val = 0;
- uint32_t aif_mask = 0;
+ u32 aif_val = 0;
+ u32 aif_mask = 0;
if (cpu->InAPrivilegedMode()) {
if (inst_cream->imod1) {
if (inst_cream->A) {
@@ -4710,11 +4711,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
mla_inst* inst_cream = (mla_inst*)inst_base->component;
- uint64_t rm = RM;
- uint64_t rs = RS;
- uint64_t rn = RN;
+ u64 rm = RM;
+ u64 rs = RS;
+ u64 rn = RN;
- RD = static_cast<uint32_t>((rm * rs + rn) & 0xffffffff);
+ RD = static_cast<u32>((rm * rs + rn) & 0xffffffff);
if (inst_cream->S) {
UPDATE_NFLAG(RD);
UPDATE_ZFLAG(RD);
@@ -4819,7 +4820,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
{
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
msr_inst* inst_cream = (msr_inst*)inst_base->component;
- const uint32_t UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020;
+ const u32 UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020;
unsigned int inst = inst_cream->inst;
unsigned int operand;
@@ -4829,9 +4830,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
} else {
operand = cpu->Reg[BITS(inst, 0, 3)];
}
- uint32_t byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0)
+ u32 byte_mask = (BIT(inst, 16) ? 0xff : 0) | (BIT(inst, 17) ? 0xff00 : 0)
| (BIT(inst, 18) ? 0xff0000 : 0) | (BIT(inst, 19) ? 0xff000000 : 0);
- uint32_t mask = 0;
+ u32 mask = 0;
if (!inst_cream->R) {
if (cpu->InAPrivilegedMode()) {
if ((operand & StateMask) != 0) {
@@ -4864,9 +4865,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
mul_inst* inst_cream = (mul_inst*)inst_base->component;
- uint64_t rm = RM;
- uint64_t rs = RS;
- RD = static_cast<uint32_t>((rm * rs) & 0xffffffff);
+ u64 rm = RM;
+ u64 rs = RS;
+ RD = static_cast<u32>((rm * rs) & 0xffffffff);
if (inst_cream->S) {
UPDATE_NFLAG(RD);
UPDATE_ZFLAG(RD);
@@ -5532,7 +5533,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
{
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
smla_inst* inst_cream = (smla_inst*)inst_base->component;
- int32_t operand1, operand2;
+ s32 operand1, operand2;
if (inst_cream->x == 0)
operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15);
else
@@ -5771,7 +5772,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
{
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
smul_inst* inst_cream = (smul_inst*)inst_base->component;
- uint32_t operand1, operand2;
+ u32 operand1, operand2;
if (inst_cream->x == 0)
operand1 = (BIT(RM, 15)) ? (BITS(RM, 0, 15) | 0xffff0000) : BITS(RM, 0, 15);
else
@@ -5792,15 +5793,15 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
{
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
umull_inst* inst_cream = (umull_inst*)inst_base->component;
- int64_t rm = RM;
- int64_t rs = RS;
+ s64 rm = RM;
+ s64 rs = RS;
if (BIT(rm, 31)) {
rm |= 0xffffffff00000000LL;
}
if (BIT(rs, 31)) {
rs |= 0xffffffff00000000LL;
}
- int64_t rst = rm * rs;
+ s64 rst = rm * rs;
RDHI = BITS(rst, 32, 63);
RDLO = BITS(rst, 0, 31);
diff --git a/src/core/arm/skyeye_common/arm_regformat.h b/src/core/arm/skyeye_common/arm_regformat.h
index d1c721809..38fa97ab9 100644
--- a/src/core/arm/skyeye_common/arm_regformat.h
+++ b/src/core/arm/skyeye_common/arm_regformat.h
@@ -55,7 +55,7 @@ enum {
};
// VFP system registers
-enum {
+enum VFPSystemRegister {
VFP_FPSID,
VFP_FPSCR,
VFP_FPEXC,
diff --git a/src/core/arm/skyeye_common/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp
index 26f303de4..0537135e2 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfp.cpp
@@ -21,6 +21,7 @@
/* Note: this file handles interface with arm core and vfp registers */
#include "common/common_funcs.h"
+#include "common/common_types.h"
#include "common/logging/log.h"
#include "core/arm/skyeye_common/armstate.h"
@@ -110,30 +111,30 @@ void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m)
}
/* Miscellaneous functions */
-int32_t vfp_get_float(ARMul_State* state, unsigned int reg)
+s32 vfp_get_float(ARMul_State* state, unsigned int reg)
{
LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
return state->ExtReg[reg];
}
-void vfp_put_float(ARMul_State* state, int32_t val, unsigned int reg)
+void vfp_put_float(ARMul_State* state, s32 val, unsigned int reg)
{
LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]\n", reg, val);
state->ExtReg[reg] = val;
}
-uint64_t vfp_get_double(ARMul_State* state, unsigned int reg)
+u64 vfp_get_double(ARMul_State* state, unsigned int reg)
{
- uint64_t result = ((uint64_t) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
+ u64 result = ((u64) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]\n", reg * 2 + 1, reg * 2, result);
return result;
}
-void vfp_put_double(ARMul_State* state, uint64_t val, unsigned int reg)
+void vfp_put_double(ARMul_State* state, u64 val, unsigned int reg)
{
- LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg * 2 + 1, reg * 2, (uint32_t)(val >> 32), (uint32_t)(val & 0xffffffff));
- state->ExtReg[reg*2] = (uint32_t) (val & 0xffffffff);
- state->ExtReg[reg*2+1] = (uint32_t) (val>>32);
+ LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg * 2 + 1, reg * 2, (u32)(val >> 32), (u32)(val & 0xffffffff));
+ state->ExtReg[reg*2] = (u32) (val & 0xffffffff);
+ state->ExtReg[reg*2+1] = (u32) (val>>32);
}
/*
diff --git a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
index 1d844a66e..47a9fe804 100644
--- a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
@@ -51,6 +51,7 @@
* ===========================================================================
*/
+#include <algorithm>
#include "common/logging/log.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
#include "core/arm/skyeye_common/vfp/vfp_helper.h"
@@ -785,9 +786,7 @@ u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,struct vfp_dou
* This ensures that NaN propagation works correctly.
*/
if (vdn->exponent < vdm->exponent) {
- struct vfp_double *t = vdn;
- vdn = vdm;
- vdm = t;
+ std::swap(vdm, vdn);
}
/*
@@ -843,9 +842,7 @@ vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn,
* This ensures that NaN propagation works correctly.
*/
if (vdn->exponent < vdm->exponent) {
- struct vfp_double *t = vdn;
- vdn = vdm;
- vdm = t;
+ std::swap(vdm, vdn);
LOG_TRACE(Core_ARM11, "VFP: swapping M <-> N\n");
}
diff --git a/src/core/arm/skyeye_common/vfp/vfpsingle.cpp b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
index e5d339252..0fb3c3bf1 100644
--- a/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
@@ -51,6 +51,7 @@
* ===========================================================================
*/
+#include <algorithm>
#include <cinttypes>
#include "common/common_funcs.h"
@@ -815,9 +816,7 @@ vfp_single_add(struct vfp_single *vsd, struct vfp_single *vsn,
* This ensures that NaN propagation works correctly.
*/
if (vsn->exponent < vsm->exponent) {
- struct vfp_single *t = vsn;
- vsn = vsm;
- vsm = t;
+ std::swap(vsm, vsn);
}
/*
@@ -872,9 +871,7 @@ vfp_single_multiply(struct vfp_single *vsd, struct vfp_single *vsn, struct vfp_s
* This ensures that NaN propagation works correctly.
*/
if (vsn->exponent < vsm->exponent) {
- struct vfp_single *t = vsn;
- vsn = vsm;
- vsm = t;
+ std::swap(vsm, vsn);
LOG_TRACE(Core_ARM11, "swapping M <-> N");
}
diff --git a/src/core/settings.h b/src/core/settings.h
index 2775ee257..6ca0e1afc 100644
--- a/src/core/settings.h
+++ b/src/core/settings.h
@@ -53,6 +53,7 @@ struct Values {
// Renderer
bool use_hw_renderer;
+ bool use_shader_jit;
float bg_red;
float bg_green;
diff --git a/src/core/tracer/citrace.h b/src/core/tracer/citrace.h
index 5deb6ce9e..709abdfb3 100644
--- a/src/core/tracer/citrace.h
+++ b/src/core/tracer/citrace.h
@@ -4,7 +4,7 @@
#pragma once
-#include <cstdint>
+#include "common/common_types.h"
namespace CiTrace {
@@ -17,38 +17,38 @@ struct CTHeader {
return "CiTr";
}
- static uint32_t ExpectedVersion() {
+ static u32 ExpectedVersion() {
return 1;
}
char magic[4];
- uint32_t version;
- uint32_t header_size;
+ u32 version;
+ u32 header_size;
struct {
// NOTE: Register range sizes are technically hardware-constants, but the actual limits
// aren't known. Hence we store the presumed limits along the offsets.
- // Sizes are given in uint32_t units.
- uint32_t gpu_registers;
- uint32_t gpu_registers_size;
- uint32_t lcd_registers;
- uint32_t lcd_registers_size;
- uint32_t pica_registers;
- uint32_t pica_registers_size;
- uint32_t default_attributes;
- uint32_t default_attributes_size;
- uint32_t vs_program_binary;
- uint32_t vs_program_binary_size;
- uint32_t vs_swizzle_data;
- uint32_t vs_swizzle_data_size;
- uint32_t vs_float_uniforms;
- uint32_t vs_float_uniforms_size;
- uint32_t gs_program_binary;
- uint32_t gs_program_binary_size;
- uint32_t gs_swizzle_data;
- uint32_t gs_swizzle_data_size;
- uint32_t gs_float_uniforms;
- uint32_t gs_float_uniforms_size;
+ // Sizes are given in u32 units.
+ u32 gpu_registers;
+ u32 gpu_registers_size;
+ u32 lcd_registers;
+ u32 lcd_registers_size;
+ u32 pica_registers;
+ u32 pica_registers_size;
+ u32 default_attributes;
+ u32 default_attributes_size;
+ u32 vs_program_binary;
+ u32 vs_program_binary_size;
+ u32 vs_swizzle_data;
+ u32 vs_swizzle_data_size;
+ u32 vs_float_uniforms;
+ u32 vs_float_uniforms_size;
+ u32 gs_program_binary;
+ u32 gs_program_binary_size;
+ u32 gs_swizzle_data;
+ u32 gs_swizzle_data_size;
+ u32 gs_float_uniforms;
+ u32 gs_float_uniforms_size;
// Other things we might want to store here:
// - Initial framebuffer data, maybe even a full copy of FCRAM/VRAM
@@ -56,27 +56,27 @@ struct CTHeader {
// - Lookup tables for procedural textures
} initial_state_offsets;
- uint32_t stream_offset;
- uint32_t stream_size;
+ u32 stream_offset;
+ u32 stream_size;
};
-enum CTStreamElementType : uint32_t {
+enum CTStreamElementType : u32 {
FrameMarker = 0xE1,
MemoryLoad = 0xE2,
RegisterWrite = 0xE3,
};
struct CTMemoryLoad {
- uint32_t file_offset;
- uint32_t size;
- uint32_t physical_address;
- uint32_t pad;
+ u32 file_offset;
+ u32 size;
+ u32 physical_address;
+ u32 pad;
};
struct CTRegisterWrite {
- uint32_t physical_address;
+ u32 physical_address;
- enum : uint32_t {
+ enum : u32 {
SIZE_8 = 0xD1,
SIZE_16 = 0xD2,
SIZE_32 = 0xD3,
@@ -84,7 +84,7 @@ struct CTRegisterWrite {
} size;
// TODO: Make it clearer which bits of this member are used for sizes other than 32 bits
- uint64_t value;
+ u64 value;
};
struct CTStreamElement {
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-18 09:06:33 +0000