From 16bbc4f81b89462ff1c9e9364e0ca7ee1289c3b3 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Sun, 1 Jun 2014 00:08:00 +0200 Subject: GPU: Add display transfer configuration. --- src/core/hw/gpu.cpp | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'src/core/hw/gpu.cpp') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index f0ca4eada..a400338b5 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -108,6 +108,31 @@ inline void Read(T &var, const u32 addr) { var = g_regs.framebuffer_sub_right_1; break; + case Registers::DisplayInputBufferAddr: + var = g_regs.display_transfer.input_address; + break; + + case Registers::DisplayOutputBufferAddr: + var = g_regs.display_transfer.output_address; + break; + + case Registers::DisplayOutputBufferSize: + var = g_regs.display_transfer.output_size; + break; + + case Registers::DisplayInputBufferSize: + var = g_regs.display_transfer.input_size; + break; + + case Registers::DisplayTransferFlags: + var = g_regs.display_transfer.flags; + break; + + // Not sure if this is supposed to be readable + case Registers::DisplayTriggerTransfer: + var = g_regs.display_transfer.trigger; + break; + case Registers::CommandListSize: var = g_regs.command_list_size; break; @@ -129,6 +154,33 @@ inline void Read(T &var, const u32 addr) { template inline void Write(u32 addr, const T data) { switch (static_cast(addr)) { + case Registers::DisplayInputBufferAddr: + g_regs.display_transfer.input_address = data; + break; + + case Registers::DisplayOutputBufferAddr: + g_regs.display_transfer.output_address = data; + break; + + case Registers::DisplayOutputBufferSize: + g_regs.display_transfer.output_size = data; + break; + + case Registers::DisplayInputBufferSize: + g_regs.display_transfer.input_size = data; + break; + + case Registers::DisplayTransferFlags: + g_regs.display_transfer.flags = data; + break; + + case Registers::DisplayTriggerTransfer: + g_regs.display_transfer.trigger = data; + if (g_regs.display_transfer.trigger & 1) { + // TODO: Perform display transfer! + } + break; + case Registers::CommandListSize: g_regs.command_list_size = data; break; -- cgit v1.2.3 From bbc6f314eb56ab1cf0a4b800750130de515cdd0f Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:01:14 +0200 Subject: GPU: Properly implement display transfers. --- src/core/hw/gpu.cpp | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'src/core/hw/gpu.cpp') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index a400338b5..e05e1b023 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -177,7 +177,25 @@ inline void Write(u32 addr, const T data) { case Registers::DisplayTriggerTransfer: g_regs.display_transfer.trigger = data; if (g_regs.display_transfer.trigger & 1) { - // TODO: Perform display transfer! + u8* source_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalInputAddress()); + u8* dest_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalOutputAddress()); + + + // TODO: Perform display transfer correctly! + for (int y = 0; y < g_regs.display_transfer.output_height; ++y) { + // TODO: Copy size is just guesswork! + memcpy(dest_pointer + y * g_regs.display_transfer.output_width * 4, + source_pointer + y * g_regs.display_transfer.input_width * 4, + g_regs.display_transfer.output_width * 4); + } + + // Clear previous contents until we implement proper buffer clearing + memset(source_pointer, 0x20, g_regs.display_transfer.input_width*g_regs.display_transfer.input_height*4); + DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", + g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4, + g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height, + g_regs.display_transfer.GetPhysicalOutputAddress(), (int)g_regs.display_transfer.output_width, (int)g_regs.display_transfer.output_height, + (int)g_regs.display_transfer.output_format); } break; -- cgit v1.2.3 From 0b4055c1520fbe7f697d2f1f93a85b559504cca4 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:10:08 +0200 Subject: GPU: Add proper framebuffer register handling. --- src/core/hw/gpu.cpp | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) (limited to 'src/core/hw/gpu.cpp') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index e05e1b023..fad3439c8 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -84,6 +84,10 @@ const u8* GetFramebufferPointer(const u32 address) { template inline void Read(T &var, const u32 addr) { switch (addr) { + case Registers::FramebufferTopSize: + var = g_regs.top_framebuffer.size; + break; + case Registers::FramebufferTopLeft1: var = g_regs.framebuffer_top_left_1; break; @@ -92,6 +96,18 @@ inline void Read(T &var, const u32 addr) { var = g_regs.framebuffer_top_left_2; break; + case Registers::FramebufferTopFormat: + var = g_regs.top_framebuffer.format; + break; + + case Registers::FramebufferTopSwapBuffers: + var = g_regs.top_framebuffer.active_fb; + break; + + case Registers::FramebufferTopStride: + var = g_regs.top_framebuffer.stride; + break; + case Registers::FramebufferTopRight1: var = g_regs.framebuffer_top_right_1; break; @@ -100,6 +116,10 @@ inline void Read(T &var, const u32 addr) { var = g_regs.framebuffer_top_right_2; break; + case Registers::FramebufferSubSize: + var = g_regs.sub_framebuffer.size; + break; + case Registers::FramebufferSubLeft1: var = g_regs.framebuffer_sub_left_1; break; @@ -108,6 +128,26 @@ inline void Read(T &var, const u32 addr) { var = g_regs.framebuffer_sub_right_1; break; + case Registers::FramebufferSubFormat: + var = g_regs.sub_framebuffer.format; + break; + + case Registers::FramebufferSubSwapBuffers: + var = g_regs.sub_framebuffer.active_fb; + break; + + case Registers::FramebufferSubStride: + var = g_regs.sub_framebuffer.stride; + break; + + case Registers::FramebufferSubLeft2: + var = g_regs.framebuffer_sub_left_2; + break; + + case Registers::FramebufferSubRight2: + var = g_regs.framebuffer_sub_right_2; + break; + case Registers::DisplayInputBufferAddr: var = g_regs.display_transfer.input_address; break; @@ -154,6 +194,17 @@ inline void Read(T &var, const u32 addr) { template inline void Write(u32 addr, const T data) { switch (static_cast(addr)) { + // TODO: Framebuffer registers!! + case Registers::FramebufferTopSwapBuffers: + g_regs.top_framebuffer.active_fb = data; + // TODO: Not sure if this should only be done upon a change! + break; + + case Registers::FramebufferSubSwapBuffers: + g_regs.sub_framebuffer.active_fb = data; + // TODO: Not sure if this should only be done upon a change! + break; + case Registers::DisplayInputBufferAddr: g_regs.display_transfer.input_address = data; break; @@ -195,7 +246,7 @@ inline void Write(u32 addr, const T data) { g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4, g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height, g_regs.display_transfer.GetPhysicalOutputAddress(), (int)g_regs.display_transfer.output_width, (int)g_regs.display_transfer.output_height, - (int)g_regs.display_transfer.output_format); + (int)g_regs.display_transfer.output_format.Value()); } break; -- cgit v1.2.3 From baf0aa04f50dff257b57fa78786e53b97c1e6abb Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Wed, 4 Jun 2014 18:30:23 +0200 Subject: GPU: Emulate memory fills. --- src/core/hw/gpu.cpp | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) (limited to 'src/core/hw/gpu.cpp') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index fad3439c8..230a12d46 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -84,6 +84,26 @@ const u8* GetFramebufferPointer(const u32 address) { template inline void Read(T &var, const u32 addr) { switch (addr) { + case Registers::MemoryFillStart1: + case Registers::MemoryFillStart2: + var = g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start; + break; + + case Registers::MemoryFillEnd1: + case Registers::MemoryFillEnd2: + var = g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end; + break; + + case Registers::MemoryFillSize1: + case Registers::MemoryFillSize2: + var = g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size; + break; + + case Registers::MemoryFillValue1: + case Registers::MemoryFillValue2: + var = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10].value; + break; + case Registers::FramebufferTopSize: var = g_regs.top_framebuffer.size; break; @@ -194,6 +214,40 @@ inline void Read(T &var, const u32 addr) { template inline void Write(u32 addr, const T data) { switch (static_cast(addr)) { + case Registers::MemoryFillStart1: + case Registers::MemoryFillStart2: + g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start = data; + break; + + case Registers::MemoryFillEnd1: + case Registers::MemoryFillEnd2: + g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end = data; + break; + + case Registers::MemoryFillSize1: + case Registers::MemoryFillSize2: + g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size = data; + break; + + case Registers::MemoryFillValue1: + case Registers::MemoryFillValue2: + { + Registers::MemoryFillConfig& config = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10]; + config.value = data; + + // TODO: Not sure if this check should be done at GSP level instead + if (config.address_start) { + // TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all + u32* start = (u32*)Memory::GetPointer(config.GetStartAddress()); + u32* end = (u32*)Memory::GetPointer(config.GetEndAddress()); + for (u32* ptr = start; ptr < end; ++ptr) + *ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation + + DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress()); + } + break; + } + // TODO: Framebuffer registers!! case Registers::FramebufferTopSwapBuffers: g_regs.top_framebuffer.active_fb = data; @@ -240,8 +294,6 @@ inline void Write(u32 addr, const T data) { g_regs.display_transfer.output_width * 4); } - // Clear previous contents until we implement proper buffer clearing - memset(source_pointer, 0x20, g_regs.display_transfer.input_width*g_regs.display_transfer.input_height*4); DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4, g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height, -- cgit v1.2.3 From 46950ee4de0b1f2c30c26467b60e38c6a38d19b8 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:14:15 +0200 Subject: GPU: Initialize GPU registers to some sensible default state. --- src/core/hw/gpu.cpp | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'src/core/hw/gpu.cpp') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index 230a12d46..0ee6b7c3b 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -353,7 +353,22 @@ void Update() { /// Initialize hardware void Init() { g_last_ticks = Core::g_app_core->GetTicks(); - SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM); +// SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM); + SetFramebufferLocation(FRAMEBUFFER_LOCATION_VRAM); + + // TODO: Width should be 240 instead? + g_regs.top_framebuffer.width = 480; + g_regs.top_framebuffer.height = 400; + g_regs.top_framebuffer.stride = 480*3; + g_regs.top_framebuffer.color_format = Registers::FramebufferFormat::RGB8; + g_regs.top_framebuffer.active_fb = 0; + + g_regs.sub_framebuffer.width = 480; + g_regs.sub_framebuffer.height = 400; + g_regs.sub_framebuffer.stride = 480*3; + g_regs.sub_framebuffer.color_format = Registers::FramebufferFormat::RGB8; + g_regs.sub_framebuffer.active_fb = 0; + NOTICE_LOG(GPU, "initialized OK"); } -- cgit v1.2.3 From 9d618d0b705e3b8de5594512a555f469631e274b Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:29:12 +0200 Subject: GPU: Interface cleanup. --- src/core/hw/gpu.cpp | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) (limited to 'src/core/hw/gpu.cpp') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index 0ee6b7c3b..49fc574bc 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -53,10 +53,10 @@ void SetFramebufferLocation(const FramebufferLocation mode) { * Gets the location of the framebuffers * @return Location of framebuffers as FramebufferLocation enum */ -const FramebufferLocation GetFramebufferLocation() { - if ((g_regs.framebuffer_top_right_1 & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) { +FramebufferLocation GetFramebufferLocation(u32 address) { + if ((address & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) { return FRAMEBUFFER_LOCATION_VRAM; - } else if ((g_regs.framebuffer_top_right_1 & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) { + } else if ((address & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) { return FRAMEBUFFER_LOCATION_FCRAM; } else { ERROR_LOG(GPU, "unknown framebuffer location!"); @@ -64,21 +64,26 @@ const FramebufferLocation GetFramebufferLocation() { return FRAMEBUFFER_LOCATION_UNKNOWN; } +u32 GetFramebufferAddr(const u32 address) { + switch (GetFramebufferLocation(address)) { + case FRAMEBUFFER_LOCATION_FCRAM: + return Memory::VirtualAddressFromPhysical_FCRAM(address); + case FRAMEBUFFER_LOCATION_VRAM: + return Memory::VirtualAddressFromPhysical_VRAM(address); + default: + ERROR_LOG(GPU, "unknown framebuffer location"); + } + return 0; +} + /** * Gets a read-only pointer to a framebuffer in memory * @param address Physical address of framebuffer * @return Returns const pointer to raw framebuffer */ const u8* GetFramebufferPointer(const u32 address) { - switch (GetFramebufferLocation()) { - case FRAMEBUFFER_LOCATION_FCRAM: - return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_FCRAM(address)); - case FRAMEBUFFER_LOCATION_VRAM: - return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_VRAM(address)); - default: - ERROR_LOG(GPU, "unknown framebuffer location"); - } - return NULL; + u32 addr = GetFramebufferAddr(address); + return (addr != 0) ? Memory::GetPointer(addr) : nullptr; } template -- cgit v1.2.3 From 357d893b2642e91d5c44a7da7ccdcbe837f46b0a Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:48:01 +0200 Subject: GPU: Make framebuffer code format-aware. --- src/core/hw/gpu.cpp | 53 +++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 47 insertions(+), 6 deletions(-) (limited to 'src/core/hw/gpu.cpp') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index 49fc574bc..31989f445 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -290,13 +290,54 @@ inline void Write(u32 addr, const T data) { u8* source_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalInputAddress()); u8* dest_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalOutputAddress()); - - // TODO: Perform display transfer correctly! for (int y = 0; y < g_regs.display_transfer.output_height; ++y) { - // TODO: Copy size is just guesswork! - memcpy(dest_pointer + y * g_regs.display_transfer.output_width * 4, - source_pointer + y * g_regs.display_transfer.input_width * 4, - g_regs.display_transfer.output_width * 4); + // TODO: Why does the register seem to hold twice the framebuffer width? + for (int x = 0; x < g_regs.display_transfer.output_width / 2; ++x) { + int source[4] = { 0, 0, 0, 0}; // rgba; + + switch (g_regs.display_transfer.input_format) { + case Registers::FramebufferFormat::RGBA8: + { + // TODO: Most likely got the component order messed up. + u8* srcptr = source_pointer + x * 4 + y * g_regs.display_transfer.input_width * 4 / 2; + source[0] = srcptr[0]; // blue + source[1] = srcptr[1]; // green + source[2] = srcptr[2]; // red + source[3] = srcptr[3]; // alpha + break; + } + + default: + ERROR_LOG(GPU, "Unknown source framebuffer format %x", (int)g_regs.display_transfer.input_format.Value()); + break; + } + + switch (g_regs.display_transfer.output_format) { + /*case Registers::FramebufferFormat::RGBA8: + { + // TODO: Untested + u8* dstptr = (u32*)(dest_pointer + x * 4 + y * g_regs.display_transfer.output_width * 4); + dstptr[0] = source[0]; + dstptr[1] = source[1]; + dstptr[2] = source[2]; + dstptr[3] = source[3]; + break; + }*/ + + case Registers::FramebufferFormat::RGB8: + { + u8* dstptr = dest_pointer + x * 3 + y * g_regs.display_transfer.output_width * 3 / 2; + dstptr[0] = source[0]; // blue + dstptr[1] = source[1]; // green + dstptr[2] = source[2]; // red + break; + } + + default: + ERROR_LOG(GPU, "Unknown destination framebuffer format %x", static_cast(g_regs.display_transfer.output_format.Value())); + break; + } + } } DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", -- cgit v1.2.3 From 75775e9ef41248592cb2c27ae69737e46499e705 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Wed, 16 Jul 2014 11:24:09 +0200 Subject: GPU: Make use of RegisterSet. --- src/core/hw/gpu.cpp | 342 ++++++++++++++++------------------------------------ 1 file changed, 101 insertions(+), 241 deletions(-) (limited to 'src/core/hw/gpu.cpp') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index 31989f445..372e4f4cc 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -15,38 +15,48 @@ namespace GPU { -Registers g_regs; +RegisterSet g_regs; u64 g_last_ticks = 0; ///< Last CPU ticks /** * Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM - * @param + * @param */ void SetFramebufferLocation(const FramebufferLocation mode) { switch (mode) { case FRAMEBUFFER_LOCATION_FCRAM: - g_regs.framebuffer_top_left_1 = PADDR_TOP_LEFT_FRAME1; - g_regs.framebuffer_top_left_2 = PADDR_TOP_LEFT_FRAME2; - g_regs.framebuffer_top_right_1 = PADDR_TOP_RIGHT_FRAME1; - g_regs.framebuffer_top_right_2 = PADDR_TOP_RIGHT_FRAME2; - g_regs.framebuffer_sub_left_1 = PADDR_SUB_FRAME1; - //g_regs.framebuffer_sub_left_2 = unknown; - g_regs.framebuffer_sub_right_1 = PADDR_SUB_FRAME2; - //g_regs.framebufferr_sub_right_2 = unknown; + { + auto& framebuffer_top = g_regs.Get(); + auto& framebuffer_sub = g_regs.Get(); + + framebuffer_top.data.address_left1 = PADDR_TOP_LEFT_FRAME1; + framebuffer_top.data.address_left2 = PADDR_TOP_LEFT_FRAME2; + framebuffer_top.data.address_right1 = PADDR_TOP_RIGHT_FRAME1; + framebuffer_top.data.address_right2 = PADDR_TOP_RIGHT_FRAME2; + framebuffer_sub.data.address_left1 = PADDR_SUB_FRAME1; + //framebuffer_sub.data.address_left2 = unknown; + framebuffer_sub.data.address_right1 = PADDR_SUB_FRAME2; + //framebuffer_sub.data.address_right2 = unknown; break; + } case FRAMEBUFFER_LOCATION_VRAM: - g_regs.framebuffer_top_left_1 = PADDR_VRAM_TOP_LEFT_FRAME1; - g_regs.framebuffer_top_left_2 = PADDR_VRAM_TOP_LEFT_FRAME2; - g_regs.framebuffer_top_right_1 = PADDR_VRAM_TOP_RIGHT_FRAME1; - g_regs.framebuffer_top_right_2 = PADDR_VRAM_TOP_RIGHT_FRAME2; - g_regs.framebuffer_sub_left_1 = PADDR_VRAM_SUB_FRAME1; - //g_regs.framebuffer_sub_left_2 = unknown; - g_regs.framebuffer_sub_right_1 = PADDR_VRAM_SUB_FRAME2; - //g_regs.framebufferr_sub_right_2 = unknown; + { + auto& framebuffer_top = g_regs.Get(); + auto& framebuffer_sub = g_regs.Get(); + + framebuffer_top.data.address_left1 = PADDR_VRAM_TOP_LEFT_FRAME1; + framebuffer_top.data.address_left2 = PADDR_VRAM_TOP_LEFT_FRAME2; + framebuffer_top.data.address_right1 = PADDR_VRAM_TOP_RIGHT_FRAME1; + framebuffer_top.data.address_right2 = PADDR_VRAM_TOP_RIGHT_FRAME2; + framebuffer_sub.data.address_left1 = PADDR_VRAM_SUB_FRAME1; + //framebuffer_sub.data.address_left2 = unknown; + framebuffer_sub.data.address_right1 = PADDR_VRAM_SUB_FRAME2; + //framebuffer_sub.data.address_right2 = unknown; break; } + } } /** @@ -87,219 +97,73 @@ const u8* GetFramebufferPointer(const u32 address) { } template -inline void Read(T &var, const u32 addr) { - switch (addr) { - case Registers::MemoryFillStart1: - case Registers::MemoryFillStart2: - var = g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start; - break; - - case Registers::MemoryFillEnd1: - case Registers::MemoryFillEnd2: - var = g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end; - break; - - case Registers::MemoryFillSize1: - case Registers::MemoryFillSize2: - var = g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size; - break; - - case Registers::MemoryFillValue1: - case Registers::MemoryFillValue2: - var = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10].value; - break; - - case Registers::FramebufferTopSize: - var = g_regs.top_framebuffer.size; - break; - - case Registers::FramebufferTopLeft1: - var = g_regs.framebuffer_top_left_1; - break; - - case Registers::FramebufferTopLeft2: - var = g_regs.framebuffer_top_left_2; - break; - - case Registers::FramebufferTopFormat: - var = g_regs.top_framebuffer.format; - break; - - case Registers::FramebufferTopSwapBuffers: - var = g_regs.top_framebuffer.active_fb; - break; - - case Registers::FramebufferTopStride: - var = g_regs.top_framebuffer.stride; - break; - - case Registers::FramebufferTopRight1: - var = g_regs.framebuffer_top_right_1; - break; - - case Registers::FramebufferTopRight2: - var = g_regs.framebuffer_top_right_2; - break; - - case Registers::FramebufferSubSize: - var = g_regs.sub_framebuffer.size; - break; - - case Registers::FramebufferSubLeft1: - var = g_regs.framebuffer_sub_left_1; - break; - - case Registers::FramebufferSubRight1: - var = g_regs.framebuffer_sub_right_1; - break; - - case Registers::FramebufferSubFormat: - var = g_regs.sub_framebuffer.format; - break; - - case Registers::FramebufferSubSwapBuffers: - var = g_regs.sub_framebuffer.active_fb; - break; - - case Registers::FramebufferSubStride: - var = g_regs.sub_framebuffer.stride; - break; - - case Registers::FramebufferSubLeft2: - var = g_regs.framebuffer_sub_left_2; - break; - - case Registers::FramebufferSubRight2: - var = g_regs.framebuffer_sub_right_2; - break; - - case Registers::DisplayInputBufferAddr: - var = g_regs.display_transfer.input_address; - break; +inline void Read(T &var, const u32 raw_addr) { + u32 addr = raw_addr - 0x1EF00000; + int index = addr / 4; - case Registers::DisplayOutputBufferAddr: - var = g_regs.display_transfer.output_address; - break; - - case Registers::DisplayOutputBufferSize: - var = g_regs.display_transfer.output_size; - break; - - case Registers::DisplayInputBufferSize: - var = g_regs.display_transfer.input_size; - break; - - case Registers::DisplayTransferFlags: - var = g_regs.display_transfer.flags; - break; - - // Not sure if this is supposed to be readable - case Registers::DisplayTriggerTransfer: - var = g_regs.display_transfer.trigger; - break; - - case Registers::CommandListSize: - var = g_regs.command_list_size; - break; - - case Registers::CommandListAddress: - var = g_regs.command_list_address; - break; - - case Registers::ProcessCommandList: - var = g_regs.command_processing_enabled; - break; - - default: + // Reads other than u32 are untested, so I'd rather have them abort than silently fail + if (index >= Regs::NumIds || !std::is_same::value) + { ERROR_LOG(GPU, "unknown Read%d @ 0x%08X", sizeof(var) * 8, addr); - break; + return; } + + var = g_regs[static_cast(addr / 4)]; } template inline void Write(u32 addr, const T data) { - switch (static_cast(addr)) { - case Registers::MemoryFillStart1: - case Registers::MemoryFillStart2: - g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start = data; - break; + addr -= 0x1EF00000; + int index = addr / 4; - case Registers::MemoryFillEnd1: - case Registers::MemoryFillEnd2: - g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end = data; - break; + // Writes other than u32 are untested, so I'd rather have them abort than silently fail + if (index >= Regs::NumIds || !std::is_same::value) + { + ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr); + return; + } - case Registers::MemoryFillSize1: - case Registers::MemoryFillSize2: - g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size = data; - break; + g_regs[static_cast(index)] = data; + + switch (static_cast(index)) { - case Registers::MemoryFillValue1: - case Registers::MemoryFillValue2: + // Memory fills are triggered once the fill value is written. + // NOTE: This is not verified. + case Regs::MemoryFill + 3: + case Regs::MemoryFill + 7: { - Registers::MemoryFillConfig& config = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10]; - config.value = data; + const auto& config = g_regs.Get(static_cast(index - 3)); // TODO: Not sure if this check should be done at GSP level instead - if (config.address_start) { + if (config.data.address_start) { // TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all - u32* start = (u32*)Memory::GetPointer(config.GetStartAddress()); - u32* end = (u32*)Memory::GetPointer(config.GetEndAddress()); + u32* start = (u32*)Memory::GetPointer(config.data.GetStartAddress()); + u32* end = (u32*)Memory::GetPointer(config.data.GetEndAddress()); for (u32* ptr = start; ptr < end; ++ptr) - *ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation + *ptr = bswap32(config.data.value); // TODO: This is just a workaround to missing framebuffer format emulation - DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress()); + DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.data.GetStartAddress(), config.data.GetEndAddress()); } break; } - // TODO: Framebuffer registers!! - case Registers::FramebufferTopSwapBuffers: - g_regs.top_framebuffer.active_fb = data; - // TODO: Not sure if this should only be done upon a change! - break; - - case Registers::FramebufferSubSwapBuffers: - g_regs.sub_framebuffer.active_fb = data; - // TODO: Not sure if this should only be done upon a change! - break; - - case Registers::DisplayInputBufferAddr: - g_regs.display_transfer.input_address = data; - break; - - case Registers::DisplayOutputBufferAddr: - g_regs.display_transfer.output_address = data; - break; - - case Registers::DisplayOutputBufferSize: - g_regs.display_transfer.output_size = data; - break; - - case Registers::DisplayInputBufferSize: - g_regs.display_transfer.input_size = data; - break; - - case Registers::DisplayTransferFlags: - g_regs.display_transfer.flags = data; - break; - - case Registers::DisplayTriggerTransfer: - g_regs.display_transfer.trigger = data; - if (g_regs.display_transfer.trigger & 1) { - u8* source_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalInputAddress()); - u8* dest_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalOutputAddress()); + case Regs::DisplayTransfer + 6: + { + const auto& config = g_regs.Get(); + if (config.data.trigger & 1) { + u8* source_pointer = Memory::GetPointer(config.data.GetPhysicalInputAddress()); + u8* dest_pointer = Memory::GetPointer(config.data.GetPhysicalOutputAddress()); - for (int y = 0; y < g_regs.display_transfer.output_height; ++y) { + for (int y = 0; y < config.data.output_height; ++y) { // TODO: Why does the register seem to hold twice the framebuffer width? - for (int x = 0; x < g_regs.display_transfer.output_width / 2; ++x) { + for (int x = 0; x < config.data.output_width / 2; ++x) { int source[4] = { 0, 0, 0, 0}; // rgba; - switch (g_regs.display_transfer.input_format) { - case Registers::FramebufferFormat::RGBA8: + switch (config.data.input_format) { + case Regs::FramebufferFormat::RGBA8: { // TODO: Most likely got the component order messed up. - u8* srcptr = source_pointer + x * 4 + y * g_regs.display_transfer.input_width * 4 / 2; + u8* srcptr = source_pointer + x * 4 + y * config.data.input_width * 4 / 2; source[0] = srcptr[0]; // blue source[1] = srcptr[1]; // green source[2] = srcptr[2]; // red @@ -308,15 +172,15 @@ inline void Write(u32 addr, const T data) { } default: - ERROR_LOG(GPU, "Unknown source framebuffer format %x", (int)g_regs.display_transfer.input_format.Value()); + ERROR_LOG(GPU, "Unknown source framebuffer format %x", config.data.input_format.Value()); break; } - switch (g_regs.display_transfer.output_format) { - /*case Registers::FramebufferFormat::RGBA8: + switch (config.data.output_format) { + /*case Regs::FramebufferFormat::RGBA8: { // TODO: Untested - u8* dstptr = (u32*)(dest_pointer + x * 4 + y * g_regs.display_transfer.output_width * 4); + u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.data.output_width * 4); dstptr[0] = source[0]; dstptr[1] = source[1]; dstptr[2] = source[2]; @@ -324,9 +188,9 @@ inline void Write(u32 addr, const T data) { break; }*/ - case Registers::FramebufferFormat::RGB8: + case Regs::FramebufferFormat::RGB8: { - u8* dstptr = dest_pointer + x * 3 + y * g_regs.display_transfer.output_width * 3 / 2; + u8* dstptr = dest_pointer + x * 3 + y * config.data.output_width * 3 / 2; dstptr[0] = source[0]; // blue dstptr[1] = source[1]; // green dstptr[2] = source[2]; // red @@ -334,40 +198,34 @@ inline void Write(u32 addr, const T data) { } default: - ERROR_LOG(GPU, "Unknown destination framebuffer format %x", static_cast(g_regs.display_transfer.output_format.Value())); + ERROR_LOG(GPU, "Unknown destination framebuffer format %x", config.data.output_format.Value()); break; } } } DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", - g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4, - g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height, - g_regs.display_transfer.GetPhysicalOutputAddress(), (int)g_regs.display_transfer.output_width, (int)g_regs.display_transfer.output_height, - (int)g_regs.display_transfer.output_format.Value()); + config.data.output_height * config.data.output_width * 4, + config.data.GetPhysicalInputAddress(), (int)config.data.input_width, (int)config.data.input_height, + config.data.GetPhysicalOutputAddress(), (int)config.data.output_width, (int)config.data.output_height, + config.data.output_format.Value()); } break; + } - case Registers::CommandListSize: - g_regs.command_list_size = data; - break; - - case Registers::CommandListAddress: - g_regs.command_list_address = data; - break; - - case Registers::ProcessCommandList: - g_regs.command_processing_enabled = data; - if (g_regs.command_processing_enabled & 1) + case Regs::CommandProcessor + 4: + { + const auto& config = g_regs.Get(); + if (config.data.trigger & 1) { - // u32* buffer = (u32*)Memory::GetPointer(g_regs.command_list_address << 3); - ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", g_regs.command_list_size, g_regs.command_list_address << 3); + // u32* buffer = (u32*)Memory::GetPointer(config.data.address << 3); + ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", config.data.size, config.data.address << 3); // TODO: Process command list! } break; + } default: - ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr); break; } } @@ -402,18 +260,20 @@ void Init() { // SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM); SetFramebufferLocation(FRAMEBUFFER_LOCATION_VRAM); + auto& framebuffer_top = g_regs.Get(); + auto& framebuffer_sub = g_regs.Get(); // TODO: Width should be 240 instead? - g_regs.top_framebuffer.width = 480; - g_regs.top_framebuffer.height = 400; - g_regs.top_framebuffer.stride = 480*3; - g_regs.top_framebuffer.color_format = Registers::FramebufferFormat::RGB8; - g_regs.top_framebuffer.active_fb = 0; - - g_regs.sub_framebuffer.width = 480; - g_regs.sub_framebuffer.height = 400; - g_regs.sub_framebuffer.stride = 480*3; - g_regs.sub_framebuffer.color_format = Registers::FramebufferFormat::RGB8; - g_regs.sub_framebuffer.active_fb = 0; + framebuffer_top.data.width = 480; + framebuffer_top.data.height = 400; + framebuffer_top.data.stride = 480*3; + framebuffer_top.data.color_format = Regs::FramebufferFormat::RGB8; + framebuffer_top.data.active_fb = 0; + + framebuffer_sub.data.width = 480; + framebuffer_sub.data.height = 400; + framebuffer_sub.data.stride = 480*3; + framebuffer_sub.data.color_format = Regs::FramebufferFormat::RGB8; + framebuffer_sub.data.active_fb = 0; NOTICE_LOG(GPU, "initialized OK"); } -- cgit v1.2.3 From 246cb75584af281596b938f898e8a3aedbcdb62a Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Wed, 16 Jul 2014 11:27:58 +0200 Subject: RegisterSet: Simplify code by using structs for register definition instead of unions. --- src/core/hw/gpu.cpp | 102 ++++++++++++++++++++++++++-------------------------- 1 file changed, 51 insertions(+), 51 deletions(-) (limited to 'src/core/hw/gpu.cpp') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index 372e4f4cc..edffa25c5 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -30,14 +30,14 @@ void SetFramebufferLocation(const FramebufferLocation mode) { auto& framebuffer_top = g_regs.Get(); auto& framebuffer_sub = g_regs.Get(); - framebuffer_top.data.address_left1 = PADDR_TOP_LEFT_FRAME1; - framebuffer_top.data.address_left2 = PADDR_TOP_LEFT_FRAME2; - framebuffer_top.data.address_right1 = PADDR_TOP_RIGHT_FRAME1; - framebuffer_top.data.address_right2 = PADDR_TOP_RIGHT_FRAME2; - framebuffer_sub.data.address_left1 = PADDR_SUB_FRAME1; - //framebuffer_sub.data.address_left2 = unknown; - framebuffer_sub.data.address_right1 = PADDR_SUB_FRAME2; - //framebuffer_sub.data.address_right2 = unknown; + framebuffer_top.address_left1 = PADDR_TOP_LEFT_FRAME1; + framebuffer_top.address_left2 = PADDR_TOP_LEFT_FRAME2; + framebuffer_top.address_right1 = PADDR_TOP_RIGHT_FRAME1; + framebuffer_top.address_right2 = PADDR_TOP_RIGHT_FRAME2; + framebuffer_sub.address_left1 = PADDR_SUB_FRAME1; + //framebuffer_sub.address_left2 = unknown; + framebuffer_sub.address_right1 = PADDR_SUB_FRAME2; + //framebuffer_sub.address_right2 = unknown; break; } @@ -46,14 +46,14 @@ void SetFramebufferLocation(const FramebufferLocation mode) { auto& framebuffer_top = g_regs.Get(); auto& framebuffer_sub = g_regs.Get(); - framebuffer_top.data.address_left1 = PADDR_VRAM_TOP_LEFT_FRAME1; - framebuffer_top.data.address_left2 = PADDR_VRAM_TOP_LEFT_FRAME2; - framebuffer_top.data.address_right1 = PADDR_VRAM_TOP_RIGHT_FRAME1; - framebuffer_top.data.address_right2 = PADDR_VRAM_TOP_RIGHT_FRAME2; - framebuffer_sub.data.address_left1 = PADDR_VRAM_SUB_FRAME1; - //framebuffer_sub.data.address_left2 = unknown; - framebuffer_sub.data.address_right1 = PADDR_VRAM_SUB_FRAME2; - //framebuffer_sub.data.address_right2 = unknown; + framebuffer_top.address_left1 = PADDR_VRAM_TOP_LEFT_FRAME1; + framebuffer_top.address_left2 = PADDR_VRAM_TOP_LEFT_FRAME2; + framebuffer_top.address_right1 = PADDR_VRAM_TOP_RIGHT_FRAME1; + framebuffer_top.address_right2 = PADDR_VRAM_TOP_RIGHT_FRAME2; + framebuffer_sub.address_left1 = PADDR_VRAM_SUB_FRAME1; + //framebuffer_sub.address_left2 = unknown; + framebuffer_sub.address_right1 = PADDR_VRAM_SUB_FRAME2; + //framebuffer_sub.address_right2 = unknown; break; } } @@ -135,14 +135,14 @@ inline void Write(u32 addr, const T data) { const auto& config = g_regs.Get(static_cast(index - 3)); // TODO: Not sure if this check should be done at GSP level instead - if (config.data.address_start) { + if (config.address_start) { // TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all - u32* start = (u32*)Memory::GetPointer(config.data.GetStartAddress()); - u32* end = (u32*)Memory::GetPointer(config.data.GetEndAddress()); + u32* start = (u32*)Memory::GetPointer(config.GetStartAddress()); + u32* end = (u32*)Memory::GetPointer(config.GetEndAddress()); for (u32* ptr = start; ptr < end; ++ptr) - *ptr = bswap32(config.data.value); // TODO: This is just a workaround to missing framebuffer format emulation + *ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation - DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.data.GetStartAddress(), config.data.GetEndAddress()); + DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress()); } break; } @@ -150,20 +150,20 @@ inline void Write(u32 addr, const T data) { case Regs::DisplayTransfer + 6: { const auto& config = g_regs.Get(); - if (config.data.trigger & 1) { - u8* source_pointer = Memory::GetPointer(config.data.GetPhysicalInputAddress()); - u8* dest_pointer = Memory::GetPointer(config.data.GetPhysicalOutputAddress()); + if (config.trigger & 1) { + u8* source_pointer = Memory::GetPointer(config.GetPhysicalInputAddress()); + u8* dest_pointer = Memory::GetPointer(config.GetPhysicalOutputAddress()); - for (int y = 0; y < config.data.output_height; ++y) { + for (int y = 0; y < config.output_height; ++y) { // TODO: Why does the register seem to hold twice the framebuffer width? - for (int x = 0; x < config.data.output_width / 2; ++x) { + for (int x = 0; x < config.output_width / 2; ++x) { int source[4] = { 0, 0, 0, 0}; // rgba; - switch (config.data.input_format) { + switch (config.input_format) { case Regs::FramebufferFormat::RGBA8: { // TODO: Most likely got the component order messed up. - u8* srcptr = source_pointer + x * 4 + y * config.data.input_width * 4 / 2; + u8* srcptr = source_pointer + x * 4 + y * config.input_width * 4 / 2; source[0] = srcptr[0]; // blue source[1] = srcptr[1]; // green source[2] = srcptr[2]; // red @@ -172,15 +172,15 @@ inline void Write(u32 addr, const T data) { } default: - ERROR_LOG(GPU, "Unknown source framebuffer format %x", config.data.input_format.Value()); + ERROR_LOG(GPU, "Unknown source framebuffer format %x", config.input_format.Value()); break; } - switch (config.data.output_format) { + switch (config.output_format) { /*case Regs::FramebufferFormat::RGBA8: { // TODO: Untested - u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.data.output_width * 4); + u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4); dstptr[0] = source[0]; dstptr[1] = source[1]; dstptr[2] = source[2]; @@ -190,7 +190,7 @@ inline void Write(u32 addr, const T data) { case Regs::FramebufferFormat::RGB8: { - u8* dstptr = dest_pointer + x * 3 + y * config.data.output_width * 3 / 2; + u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3 / 2; dstptr[0] = source[0]; // blue dstptr[1] = source[1]; // green dstptr[2] = source[2]; // red @@ -198,17 +198,17 @@ inline void Write(u32 addr, const T data) { } default: - ERROR_LOG(GPU, "Unknown destination framebuffer format %x", config.data.output_format.Value()); + ERROR_LOG(GPU, "Unknown destination framebuffer format %x", config.output_format.Value()); break; } } } DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", - config.data.output_height * config.data.output_width * 4, - config.data.GetPhysicalInputAddress(), (int)config.data.input_width, (int)config.data.input_height, - config.data.GetPhysicalOutputAddress(), (int)config.data.output_width, (int)config.data.output_height, - config.data.output_format.Value()); + config.output_height * config.output_width * 4, + config.GetPhysicalInputAddress(), (int)config.input_width, (int)config.input_height, + config.GetPhysicalOutputAddress(), (int)config.output_width, (int)config.output_height, + config.output_format.Value()); } break; } @@ -216,10 +216,10 @@ inline void Write(u32 addr, const T data) { case Regs::CommandProcessor + 4: { const auto& config = g_regs.Get(); - if (config.data.trigger & 1) + if (config.trigger & 1) { - // u32* buffer = (u32*)Memory::GetPointer(config.data.address << 3); - ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", config.data.size, config.data.address << 3); + // u32* buffer = (u32*)Memory::GetPointer(config.address << 3); + ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", config.size, config.address << 3); // TODO: Process command list! } break; @@ -263,17 +263,17 @@ void Init() { auto& framebuffer_top = g_regs.Get(); auto& framebuffer_sub = g_regs.Get(); // TODO: Width should be 240 instead? - framebuffer_top.data.width = 480; - framebuffer_top.data.height = 400; - framebuffer_top.data.stride = 480*3; - framebuffer_top.data.color_format = Regs::FramebufferFormat::RGB8; - framebuffer_top.data.active_fb = 0; - - framebuffer_sub.data.width = 480; - framebuffer_sub.data.height = 400; - framebuffer_sub.data.stride = 480*3; - framebuffer_sub.data.color_format = Regs::FramebufferFormat::RGB8; - framebuffer_sub.data.active_fb = 0; + framebuffer_top.width = 480; + framebuffer_top.height = 400; + framebuffer_top.stride = 480*3; + framebuffer_top.color_format = Regs::FramebufferFormat::RGB8; + framebuffer_top.active_fb = 0; + + framebuffer_sub.width = 480; + framebuffer_sub.height = 400; + framebuffer_sub.stride = 480*3; + framebuffer_sub.color_format = Regs::FramebufferFormat::RGB8; + framebuffer_sub.active_fb = 0; NOTICE_LOG(GPU, "initialized OK"); } -- cgit v1.2.3 From 2eb61dafc0c957ad1591150ff1f8cd002b8851bb Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Tue, 22 Jul 2014 13:29:25 +0200 Subject: GPU: Clarify display transfer code. Also makes the illogical component order more obvious. --- src/core/hw/gpu.cpp | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) (limited to 'src/core/hw/gpu.cpp') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index edffa25c5..d18ff7625 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -157,17 +157,19 @@ inline void Write(u32 addr, const T data) { for (int y = 0; y < config.output_height; ++y) { // TODO: Why does the register seem to hold twice the framebuffer width? for (int x = 0; x < config.output_width / 2; ++x) { - int source[4] = { 0, 0, 0, 0}; // rgba; + struct { + int r, g, b, a; + } source_color = { 0, 0, 0, 0 }; switch (config.input_format) { case Regs::FramebufferFormat::RGBA8: { // TODO: Most likely got the component order messed up. u8* srcptr = source_pointer + x * 4 + y * config.input_width * 4 / 2; - source[0] = srcptr[0]; // blue - source[1] = srcptr[1]; // green - source[2] = srcptr[2]; // red - source[3] = srcptr[3]; // alpha + source_color.r = srcptr[0]; // blue + source_color.g = srcptr[1]; // green + source_color.b = srcptr[2]; // red + source_color.a = srcptr[3]; // alpha break; } @@ -181,19 +183,20 @@ inline void Write(u32 addr, const T data) { { // TODO: Untested u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4); - dstptr[0] = source[0]; - dstptr[1] = source[1]; - dstptr[2] = source[2]; - dstptr[3] = source[3]; + dstptr[0] = source_color.r; + dstptr[1] = source_color.g; + dstptr[2] = source_color.b; + dstptr[3] = source_color.a; break; }*/ case Regs::FramebufferFormat::RGB8: { + // TODO: Most likely got the component order messed up. u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3 / 2; - dstptr[0] = source[0]; // blue - dstptr[1] = source[1]; // green - dstptr[2] = source[2]; // red + dstptr[0] = source_color.r; // blue + dstptr[1] = source_color.g; // green + dstptr[2] = source_color.b; // red break; } -- cgit v1.2.3 From 9fd2537e933b5d36c898d662e29ea57f7ce61e49 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Tue, 22 Jul 2014 23:07:32 +0200 Subject: Use uniform formatting when printing hexadecimal numbers. --- src/core/hw/gpu.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/core/hw/gpu.cpp') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index d18ff7625..c00be2a83 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -142,7 +142,7 @@ inline void Write(u32 addr, const T data) { for (u32* ptr = start; ptr < end; ++ptr) *ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation - DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress()); + DEBUG_LOG(GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress()); } break; } @@ -207,7 +207,7 @@ inline void Write(u32 addr, const T data) { } } - DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", + DEBUG_LOG(GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%dx%d)-> 0x%08x(%dx%d), dst format %x", config.output_height * config.output_width * 4, config.GetPhysicalInputAddress(), (int)config.input_width, (int)config.input_height, config.GetPhysicalOutputAddress(), (int)config.output_width, (int)config.output_height, @@ -222,7 +222,7 @@ inline void Write(u32 addr, const T data) { if (config.trigger & 1) { // u32* buffer = (u32*)Memory::GetPointer(config.address << 3); - ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", config.size, config.address << 3); + ERROR_LOG(GPU, "Beginning 0x%08x bytes of commands from address 0x%08x", config.size, config.address << 3); // TODO: Process command list! } break; -- cgit v1.2.3