From 994d29f416ce8d74560650be7a70e9a028c425c9 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 18:47:09 +0200 Subject: Use a more compatible choice of initial framebuffer addresses. --- src/core/hw/gpu.h | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) (limited to 'src/core/hw/gpu.h') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 3314ba989..0c7dffec3 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -51,23 +51,35 @@ enum { TOP_WIDTH = 400, BOTTOM_WIDTH = 320, - // Physical addresses in FCRAM used by ARM9 applications - these are correct for real hardware - PADDR_FRAMEBUFFER_SEL = 0x20184E59, - PADDR_TOP_LEFT_FRAME1 = 0x20184E60, + // Physical addresses in FCRAM (chosen arbitrarily) + PADDR_TOP_LEFT_FRAME1 = 0x201D4C00, + PADDR_TOP_LEFT_FRAME2 = 0x202D4C00, + PADDR_TOP_RIGHT_FRAME1 = 0x203D4C00, + PADDR_TOP_RIGHT_FRAME2 = 0x204D4C00, + PADDR_SUB_FRAME1 = 0x205D4C00, + PADDR_SUB_FRAME2 = 0x206D4C00, + // Physical addresses in FCRAM used by ARM9 applications +/* PADDR_TOP_LEFT_FRAME1 = 0x20184E60, PADDR_TOP_LEFT_FRAME2 = 0x201CB370, PADDR_TOP_RIGHT_FRAME1 = 0x20282160, PADDR_TOP_RIGHT_FRAME2 = 0x202C8670, PADDR_SUB_FRAME1 = 0x202118E0, - PADDR_SUB_FRAME2 = 0x20249CF0, - - // Physical addresses in VRAM - I'm not sure how these are actually allocated (so not real) - PADDR_VRAM_FRAMEBUFFER_SEL = 0x18184E59, - PADDR_VRAM_TOP_LEFT_FRAME1 = 0x18184E60, - PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370, + PADDR_SUB_FRAME2 = 0x20249CF0,*/ + + // Physical addresses in VRAM + // TODO: These should just be deduced from the ones above + PADDR_VRAM_TOP_LEFT_FRAME1 = 0x181D4C00, + PADDR_VRAM_TOP_LEFT_FRAME2 = 0x182D4C00, + PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x183D4C00, + PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x184D4C00, + PADDR_VRAM_SUB_FRAME1 = 0x185D4C00, + PADDR_VRAM_SUB_FRAME2 = 0x186D4C00, + // Physical addresses in VRAM used by ARM9 applications +/* PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370, PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x18282160, PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x182C8670, PADDR_VRAM_SUB_FRAME1 = 0x182118E0, - PADDR_VRAM_SUB_FRAME2 = 0x18249CF0, + PADDR_VRAM_SUB_FRAME2 = 0x18249CF0,*/ }; /// Framebuffer location -- cgit v1.2.3 From ec9511e1db1f7ff0c2a8f86916937ea5736cdcf6 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Sun, 1 Jun 2014 00:22:40 +0200 Subject: GSP: HLE GXCommandId::SET_DISPLAY_TRANSFER and GXCommandId::SET_TEXTURE_COPY. --- src/core/hw/gpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/core/hw/gpu.h') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 0c7dffec3..58058d732 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -22,6 +22,14 @@ struct Registers { FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer + DisplayInputBufferAddr = 0x1EF00C00, + DisplayOutputBufferAddr = 0x1EF00C04, + DisplayOutputBufferSize = 0x1EF00C08, + DisplayInputBufferSize = 0x1EF00C0C, + DisplayTransferFlags = 0x1EF00C10, + // Unknown?? + DisplayTriggerTransfer = 0x1EF00C18, + CommandListSize = 0x1EF018E0, CommandListAddress = 0x1EF018E8, ProcessCommandList = 0x1EF018F0, -- cgit v1.2.3 From 16bbc4f81b89462ff1c9e9364e0ca7ee1289c3b3 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Sun, 1 Jun 2014 00:08:00 +0200 Subject: GPU: Add display transfer configuration. --- src/core/hw/gpu.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'src/core/hw/gpu.h') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 58058d732..29eb7ed81 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -5,6 +5,7 @@ #pragma once #include "common/common_types.h" +#include "common/bit_field.h" namespace GPU { @@ -44,6 +45,45 @@ struct Registers { u32 framebuffer_sub_right_1; u32 framebuffer_sub_right_2; + struct { + u32 input_address; + u32 output_address; + + inline u32 GetPhysicalInputAddress() const { + return input_address * 8; + } + + inline u32 GetPhysicalOutputAddress() const { + return output_address * 8; + } + + union { + u32 output_size; + + BitField< 0, 16, u32> output_width; + BitField<16, 16, u32> output_height; + }; + + union { + u32 input_size; + + BitField< 0, 16, u32> input_width; + BitField<16, 16, u32> input_height; + }; + + union { + u32 flags; + + BitField< 0, 1, u32> flip_data; + BitField< 8, 3, u32> input_format; + BitField<12, 3, u32> output_format; + BitField<16, 1, u32> output_tiled; + }; + + u32 unknown; + u32 trigger; + } display_transfer; + u32 command_list_size; u32 command_list_address; u32 command_processing_enabled; -- cgit v1.2.3 From 0b4055c1520fbe7f697d2f1f93a85b559504cca4 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:10:08 +0200 Subject: GPU: Add proper framebuffer register handling. --- src/core/hw/gpu.h | 63 ++++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 53 insertions(+), 10 deletions(-) (limited to 'src/core/hw/gpu.h') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 29eb7ed81..50c360814 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -14,14 +14,23 @@ static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of i struct Registers { enum Id : u32 { - FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left - FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left - FramebufferTopRight1 = 0x1EF00494, // Main LCD, first framebuffer for 3D right - FramebufferTopRight2 = 0x1EF00498, // Main LCD, second framebuffer for 3D right - FramebufferSubLeft1 = 0x1EF00568, // Sub LCD, first framebuffer - FramebufferSubLeft2 = 0x1EF0056C, // Sub LCD, second framebuffer - FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer - FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer + FramebufferTopSize = 0x1EF0045C, + FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left + FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left + FramebufferTopFormat = 0x1EF00470, + FramebufferTopSwapBuffers = 0x1EF00478, + FramebufferTopStride = 0x1EF00490, // framebuffer row stride? + FramebufferTopRight1 = 0x1EF00494, // Main LCD, first framebuffer for 3D right + FramebufferTopRight2 = 0x1EF00498, // Main LCD, second framebuffer for 3D right + + FramebufferSubSize = 0x1EF0055C, + FramebufferSubLeft1 = 0x1EF00568, // Sub LCD, first framebuffer + FramebufferSubLeft2 = 0x1EF0056C, // Sub LCD, second framebuffer + FramebufferSubFormat = 0x1EF00570, + FramebufferSubSwapBuffers = 0x1EF00578, + FramebufferSubStride = 0x1EF00590, // framebuffer row stride? + FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer + FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer DisplayInputBufferAddr = 0x1EF00C00, DisplayOutputBufferAddr = 0x1EF00C04, @@ -36,6 +45,15 @@ struct Registers { ProcessCommandList = 0x1EF018F0, }; + enum class FramebufferFormat : u32 { + RGBA8 = 0, + RGB8 = 1, + RGB565 = 2, + RGB5A1 = 3, + RGBA4 = 4, + }; + + // TODO: Move these into the framebuffer struct u32 framebuffer_top_left_1; u32 framebuffer_top_left_2; u32 framebuffer_top_right_1; @@ -45,6 +63,31 @@ struct Registers { u32 framebuffer_sub_right_1; u32 framebuffer_sub_right_2; + struct FrameBufferConfig { + union { + u32 size; + + BitField< 0, 16, u32> width; + BitField<16, 16, u32> height; + }; + + union { + u32 format; + + BitField< 0, 3, FramebufferFormat> color_format; + }; + + union { + u32 active_fb; + + BitField<0, 1, u32> second_fb_active; + }; + + u32 stride; + }; + FrameBufferConfig top_framebuffer; + FrameBufferConfig sub_framebuffer; + struct { u32 input_address; u32 output_address; @@ -75,8 +118,8 @@ struct Registers { u32 flags; BitField< 0, 1, u32> flip_data; - BitField< 8, 3, u32> input_format; - BitField<12, 3, u32> output_format; + BitField< 8, 3, FramebufferFormat> input_format; + BitField<12, 3, FramebufferFormat> output_format; BitField<16, 1, u32> output_tiled; }; -- cgit v1.2.3 From baf0aa04f50dff257b57fa78786e53b97c1e6abb Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Wed, 4 Jun 2014 18:30:23 +0200 Subject: GPU: Emulate memory fills. --- src/core/hw/gpu.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'src/core/hw/gpu.h') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 50c360814..47d7fcb26 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -14,6 +14,15 @@ static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of i struct Registers { enum Id : u32 { + MemoryFillStart1 = 0x1EF00010, + MemoryFillEnd1 = 0x1EF00014, + MemoryFillSize1 = 0x1EF00018, + MemoryFillValue1 = 0x1EF0001C, + MemoryFillStart2 = 0x1EF00020, + MemoryFillEnd2 = 0x1EF00024, + MemoryFillSize2 = 0x1EF00028, + MemoryFillValue2 = 0x1EF0002C, + FramebufferTopSize = 0x1EF0045C, FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left @@ -53,6 +62,23 @@ struct Registers { RGBA4 = 4, }; + struct MemoryFillConfig { + u32 address_start; + u32 address_end; // ? + u32 size; + u32 value; // ? + + inline u32 GetStartAddress() const { + return address_start * 8; + } + + inline u32 GetEndAddress() const { + return address_end * 8; + } + }; + + MemoryFillConfig memory_fill[2]; + // TODO: Move these into the framebuffer struct u32 framebuffer_top_left_1; u32 framebuffer_top_left_2; -- cgit v1.2.3 From 9d618d0b705e3b8de5594512a555f469631e274b Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:29:12 +0200 Subject: GPU: Interface cleanup. --- src/core/hw/gpu.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/core/hw/gpu.h') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 47d7fcb26..b66cf4a37 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -219,10 +219,12 @@ void SetFramebufferLocation(const FramebufferLocation mode); */ const u8* GetFramebufferPointer(const u32 address); +u32 GetFramebufferAddr(const u32 address); + /** * Gets the location of the framebuffers */ -const FramebufferLocation GetFramebufferLocation(); +FramebufferLocation GetFramebufferLocation(u32 address); template inline void Read(T &var, const u32 addr); -- cgit v1.2.3 From 75775e9ef41248592cb2c27ae69737e46499e705 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Wed, 16 Jul 2014 11:24:09 +0200 Subject: GPU: Make use of RegisterSet. --- src/core/hw/gpu.h | 136 ++++++++++++++++++++++++++++-------------------------- 1 file changed, 71 insertions(+), 65 deletions(-) (limited to 'src/core/hw/gpu.h') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index b66cf4a37..ce524bd02 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -6,54 +6,31 @@ #include "common/common_types.h" #include "common/bit_field.h" +#include "common/register_set.h" namespace GPU { static const u32 kFrameCycles = 268123480 / 60; ///< 268MHz / 60 frames per second static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of instructions/frame -struct Registers { +// MMIO region 0x1EFxxxxx +struct Regs { enum Id : u32 { - MemoryFillStart1 = 0x1EF00010, - MemoryFillEnd1 = 0x1EF00014, - MemoryFillSize1 = 0x1EF00018, - MemoryFillValue1 = 0x1EF0001C, - MemoryFillStart2 = 0x1EF00020, - MemoryFillEnd2 = 0x1EF00024, - MemoryFillSize2 = 0x1EF00028, - MemoryFillValue2 = 0x1EF0002C, - - FramebufferTopSize = 0x1EF0045C, - FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left - FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left - FramebufferTopFormat = 0x1EF00470, - FramebufferTopSwapBuffers = 0x1EF00478, - FramebufferTopStride = 0x1EF00490, // framebuffer row stride? - FramebufferTopRight1 = 0x1EF00494, // Main LCD, first framebuffer for 3D right - FramebufferTopRight2 = 0x1EF00498, // Main LCD, second framebuffer for 3D right - - FramebufferSubSize = 0x1EF0055C, - FramebufferSubLeft1 = 0x1EF00568, // Sub LCD, first framebuffer - FramebufferSubLeft2 = 0x1EF0056C, // Sub LCD, second framebuffer - FramebufferSubFormat = 0x1EF00570, - FramebufferSubSwapBuffers = 0x1EF00578, - FramebufferSubStride = 0x1EF00590, // framebuffer row stride? - FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer - FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer - - DisplayInputBufferAddr = 0x1EF00C00, - DisplayOutputBufferAddr = 0x1EF00C04, - DisplayOutputBufferSize = 0x1EF00C08, - DisplayInputBufferSize = 0x1EF00C0C, - DisplayTransferFlags = 0x1EF00C10, - // Unknown?? - DisplayTriggerTransfer = 0x1EF00C18, - - CommandListSize = 0x1EF018E0, - CommandListAddress = 0x1EF018E8, - ProcessCommandList = 0x1EF018F0, + MemoryFill = 0x00004, // + 5,6,7; second block at 8-11 + + FramebufferTop = 0x00117, // + 11a,11b,11c,11d(?),11e...126 + FramebufferBottom = 0x00157, // + 15a,15b,15c,15d(?),15e...166 + + DisplayTransfer = 0x00300, // + 301,302,303,304,305,306 + + CommandProcessor = 0x00638, // + 63a,63c + + NumIds = 0x01000 }; + template + union Struct; + enum class FramebufferFormat : u32 { RGBA8 = 0, RGB8 = 1, @@ -62,7 +39,11 @@ struct Registers { RGBA4 = 4, }; - struct MemoryFillConfig { +}; + +template<> +union Regs::Struct { + struct { u32 address_start; u32 address_end; // ? u32 size; @@ -75,21 +56,15 @@ struct Registers { inline u32 GetEndAddress() const { return address_end * 8; } - }; - - MemoryFillConfig memory_fill[2]; + } data; +}; +static_assert(sizeof(Regs::Struct) == 0x10, "Structure size and register block length don't match"); - // TODO: Move these into the framebuffer struct - u32 framebuffer_top_left_1; - u32 framebuffer_top_left_2; - u32 framebuffer_top_right_1; - u32 framebuffer_top_right_2; - u32 framebuffer_sub_left_1; - u32 framebuffer_sub_left_2; - u32 framebuffer_sub_right_1; - u32 framebuffer_sub_right_2; +template<> +union Regs::Struct { + using Format = Regs::FramebufferFormat; - struct FrameBufferConfig { + struct { union { u32 size; @@ -97,22 +72,43 @@ struct Registers { BitField<16, 16, u32> height; }; + u32 pad0[2]; + + u32 address_left1; + u32 address_left2; + union { u32 format; - BitField< 0, 3, FramebufferFormat> color_format; + BitField< 0, 3, Format> color_format; }; + u32 pad1; + union { u32 active_fb; BitField<0, 1, u32> second_fb_active; }; + u32 pad2[5]; + u32 stride; - }; - FrameBufferConfig top_framebuffer; - FrameBufferConfig sub_framebuffer; + + u32 address_right1; + u32 address_right2; + } data; +}; +template<> +union Regs::Struct { + using Type = decltype(Regs::Struct::data); + Type data; +}; +static_assert(sizeof(Regs::Struct) == 0x40, "Structure size and register block length don't match"); + +template<> +union Regs::Struct { + using Format = Regs::FramebufferFormat; struct { u32 input_address; @@ -144,21 +140,31 @@ struct Registers { u32 flags; BitField< 0, 1, u32> flip_data; - BitField< 8, 3, FramebufferFormat> input_format; - BitField<12, 3, FramebufferFormat> output_format; + BitField< 8, 3, Format> input_format; + BitField<12, 3, Format> output_format; BitField<16, 1, u32> output_tiled; }; u32 unknown; u32 trigger; - } display_transfer; + } data; +}; +static_assert(sizeof(Regs::Struct) == 0x1C, "Structure size and register block length don't match"); - u32 command_list_size; - u32 command_list_address; - u32 command_processing_enabled; +template<> +union Regs::Struct { + struct { + u32 size; + u32 pad0; + u32 address; + u32 pad1; + u32 trigger; + } data; }; +static_assert(sizeof(Regs::Struct) == 0x14, "Structure size and register block length don't match"); + -extern Registers g_regs; +extern RegisterSet g_regs; enum { TOP_ASPECT_X = 0x5, @@ -208,7 +214,7 @@ enum FramebufferLocation { /** * Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM - * @param + * @param */ void SetFramebufferLocation(const FramebufferLocation mode); -- cgit v1.2.3 From 246cb75584af281596b938f898e8a3aedbcdb62a Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Wed, 16 Jul 2014 11:27:58 +0200 Subject: RegisterSet: Simplify code by using structs for register definition instead of unions. --- src/core/hw/gpu.h | 154 +++++++++++++++++++++++++----------------------------- 1 file changed, 72 insertions(+), 82 deletions(-) (limited to 'src/core/hw/gpu.h') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index ce524bd02..4ef0a047f 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -29,7 +29,7 @@ struct Regs { }; template - union Struct; + struct Struct; enum class FramebufferFormat : u32 { RGBA8 = 0, @@ -38,128 +38,118 @@ struct Regs { RGB5A1 = 3, RGBA4 = 4, }; - }; template<> -union Regs::Struct { - struct { - u32 address_start; - u32 address_end; // ? - u32 size; - u32 value; // ? - - inline u32 GetStartAddress() const { - return address_start * 8; - } - - inline u32 GetEndAddress() const { - return address_end * 8; - } - } data; +struct Regs::Struct { + u32 address_start; + u32 address_end; // ? + u32 size; + u32 value; // ? + + inline u32 GetStartAddress() const { + return address_start * 8; + } + + inline u32 GetEndAddress() const { + return address_end * 8; + } }; static_assert(sizeof(Regs::Struct) == 0x10, "Structure size and register block length don't match"); template<> -union Regs::Struct { +struct Regs::Struct { using Format = Regs::FramebufferFormat; - struct { - union { - u32 size; + union { + u32 size; - BitField< 0, 16, u32> width; - BitField<16, 16, u32> height; - }; + BitField< 0, 16, u32> width; + BitField<16, 16, u32> height; + }; - u32 pad0[2]; + u32 pad0[2]; - u32 address_left1; - u32 address_left2; + u32 address_left1; + u32 address_left2; - union { - u32 format; + union { + u32 format; - BitField< 0, 3, Format> color_format; - }; + BitField< 0, 3, Format> color_format; + }; - u32 pad1; + u32 pad1; - union { - u32 active_fb; + union { + u32 active_fb; - BitField<0, 1, u32> second_fb_active; - }; + BitField<0, 1, u32> second_fb_active; + }; - u32 pad2[5]; + u32 pad2[5]; - u32 stride; + u32 stride; - u32 address_right1; - u32 address_right2; - } data; + u32 address_right1; + u32 address_right2; }; + template<> -union Regs::Struct { - using Type = decltype(Regs::Struct::data); - Type data; +struct Regs::Struct : public Regs::Struct { }; static_assert(sizeof(Regs::Struct) == 0x40, "Structure size and register block length don't match"); template<> -union Regs::Struct { +struct Regs::Struct { using Format = Regs::FramebufferFormat; - struct { - u32 input_address; - u32 output_address; + u32 input_address; + u32 output_address; - inline u32 GetPhysicalInputAddress() const { - return input_address * 8; - } + inline u32 GetPhysicalInputAddress() const { + return input_address * 8; + } - inline u32 GetPhysicalOutputAddress() const { - return output_address * 8; - } + inline u32 GetPhysicalOutputAddress() const { + return output_address * 8; + } - union { - u32 output_size; + union { + u32 output_size; - BitField< 0, 16, u32> output_width; - BitField<16, 16, u32> output_height; - }; + BitField< 0, 16, u32> output_width; + BitField<16, 16, u32> output_height; + }; - union { - u32 input_size; + union { + u32 input_size; - BitField< 0, 16, u32> input_width; - BitField<16, 16, u32> input_height; - }; + BitField< 0, 16, u32> input_width; + BitField<16, 16, u32> input_height; + }; - union { - u32 flags; + union { + u32 flags; - BitField< 0, 1, u32> flip_data; - BitField< 8, 3, Format> input_format; - BitField<12, 3, Format> output_format; - BitField<16, 1, u32> output_tiled; - }; + BitField< 0, 1, u32> flip_data; + BitField< 8, 3, Format> input_format; + BitField<12, 3, Format> output_format; + BitField<16, 1, u32> output_tiled; + }; - u32 unknown; - u32 trigger; - } data; + u32 unknown; + u32 trigger; }; static_assert(sizeof(Regs::Struct) == 0x1C, "Structure size and register block length don't match"); template<> -union Regs::Struct { - struct { - u32 size; - u32 pad0; - u32 address; - u32 pad1; - u32 trigger; - } data; +struct Regs::Struct { + u32 size; + u32 pad0; + u32 address; + u32 pad1; + u32 trigger; }; static_assert(sizeof(Regs::Struct) == 0x14, "Structure size and register block length don't match"); -- cgit v1.2.3 From 61e2ffd4483bf2da0862e32449caa9f1cecc5b72 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Tue, 22 Jul 2014 13:21:57 +0200 Subject: GPU: Add documentation. --- src/core/hw/gpu.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'src/core/hw/gpu.h') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 4ef0a047f..3078e4142 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -84,11 +84,14 @@ struct Regs::Struct { union { u32 active_fb; + // 0: Use parameters ending with "1" + // 1: Use parameters ending with "2" BitField<0, 1, u32> second_fb_active; }; u32 pad2[5]; + // Distance between two pixel rows, in bytes u32 stride; u32 address_right1; @@ -132,23 +135,32 @@ struct Regs::Struct { union { u32 flags; - BitField< 0, 1, u32> flip_data; + BitField< 0, 1, u32> flip_data; // flips input data horizontally (TODO) if true BitField< 8, 3, Format> input_format; BitField<12, 3, Format> output_format; - BitField<16, 1, u32> output_tiled; + BitField<16, 1, u32> output_tiled; // stores output in a tiled format }; u32 unknown; + + // it seems that writing to this field triggers the display transfer u32 trigger; }; static_assert(sizeof(Regs::Struct) == 0x1C, "Structure size and register block length don't match"); template<> struct Regs::Struct { + // command list size u32 size; + u32 pad0; + + // command list address u32 address; + u32 pad1; + + // it seems that writing to this field triggers command list processing u32 trigger; }; static_assert(sizeof(Regs::Struct) == 0x14, "Structure size and register block length don't match"); -- cgit v1.2.3 From afcb250b3140fa2f37efa800f5346aabbde5db2a Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Tue, 22 Jul 2014 13:49:25 +0200 Subject: Fix a few warnings. Templates shouldn't be marked as inline if they aren't defined in the header. --- src/core/hw/gpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/core/hw/gpu.h') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 3078e4142..42f18a0e7 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -235,10 +235,10 @@ u32 GetFramebufferAddr(const u32 address); FramebufferLocation GetFramebufferLocation(u32 address); template -inline void Read(T &var, const u32 addr); +void Read(T &var, const u32 addr); template -inline void Write(u32 addr, const T data); +void Write(u32 addr, const T data); /// Update hardware void Update(); -- cgit v1.2.3