From 994d29f416ce8d74560650be7a70e9a028c425c9 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 18:47:09 +0200 Subject: Use a more compatible choice of initial framebuffer addresses. --- src/core/hw/gpu.h | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 3314ba989..0c7dffec3 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -51,23 +51,35 @@ enum { TOP_WIDTH = 400, BOTTOM_WIDTH = 320, - // Physical addresses in FCRAM used by ARM9 applications - these are correct for real hardware - PADDR_FRAMEBUFFER_SEL = 0x20184E59, - PADDR_TOP_LEFT_FRAME1 = 0x20184E60, + // Physical addresses in FCRAM (chosen arbitrarily) + PADDR_TOP_LEFT_FRAME1 = 0x201D4C00, + PADDR_TOP_LEFT_FRAME2 = 0x202D4C00, + PADDR_TOP_RIGHT_FRAME1 = 0x203D4C00, + PADDR_TOP_RIGHT_FRAME2 = 0x204D4C00, + PADDR_SUB_FRAME1 = 0x205D4C00, + PADDR_SUB_FRAME2 = 0x206D4C00, + // Physical addresses in FCRAM used by ARM9 applications +/* PADDR_TOP_LEFT_FRAME1 = 0x20184E60, PADDR_TOP_LEFT_FRAME2 = 0x201CB370, PADDR_TOP_RIGHT_FRAME1 = 0x20282160, PADDR_TOP_RIGHT_FRAME2 = 0x202C8670, PADDR_SUB_FRAME1 = 0x202118E0, - PADDR_SUB_FRAME2 = 0x20249CF0, - - // Physical addresses in VRAM - I'm not sure how these are actually allocated (so not real) - PADDR_VRAM_FRAMEBUFFER_SEL = 0x18184E59, - PADDR_VRAM_TOP_LEFT_FRAME1 = 0x18184E60, - PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370, + PADDR_SUB_FRAME2 = 0x20249CF0,*/ + + // Physical addresses in VRAM + // TODO: These should just be deduced from the ones above + PADDR_VRAM_TOP_LEFT_FRAME1 = 0x181D4C00, + PADDR_VRAM_TOP_LEFT_FRAME2 = 0x182D4C00, + PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x183D4C00, + PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x184D4C00, + PADDR_VRAM_SUB_FRAME1 = 0x185D4C00, + PADDR_VRAM_SUB_FRAME2 = 0x186D4C00, + // Physical addresses in VRAM used by ARM9 applications +/* PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370, PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x18282160, PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x182C8670, PADDR_VRAM_SUB_FRAME1 = 0x182118E0, - PADDR_VRAM_SUB_FRAME2 = 0x18249CF0, + PADDR_VRAM_SUB_FRAME2 = 0x18249CF0,*/ }; /// Framebuffer location -- cgit v1.2.3 From ec9511e1db1f7ff0c2a8f86916937ea5736cdcf6 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Sun, 1 Jun 2014 00:22:40 +0200 Subject: GSP: HLE GXCommandId::SET_DISPLAY_TRANSFER and GXCommandId::SET_TEXTURE_COPY. --- src/core/hw/gpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 0c7dffec3..58058d732 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -22,6 +22,14 @@ struct Registers { FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer + DisplayInputBufferAddr = 0x1EF00C00, + DisplayOutputBufferAddr = 0x1EF00C04, + DisplayOutputBufferSize = 0x1EF00C08, + DisplayInputBufferSize = 0x1EF00C0C, + DisplayTransferFlags = 0x1EF00C10, + // Unknown?? + DisplayTriggerTransfer = 0x1EF00C18, + CommandListSize = 0x1EF018E0, CommandListAddress = 0x1EF018E8, ProcessCommandList = 0x1EF018F0, -- cgit v1.2.3 From 16bbc4f81b89462ff1c9e9364e0ca7ee1289c3b3 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Sun, 1 Jun 2014 00:08:00 +0200 Subject: GPU: Add display transfer configuration. --- src/core/hw/gpu.cpp | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++ src/core/hw/gpu.h | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index f0ca4eada..a400338b5 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -108,6 +108,31 @@ inline void Read(T &var, const u32 addr) { var = g_regs.framebuffer_sub_right_1; break; + case Registers::DisplayInputBufferAddr: + var = g_regs.display_transfer.input_address; + break; + + case Registers::DisplayOutputBufferAddr: + var = g_regs.display_transfer.output_address; + break; + + case Registers::DisplayOutputBufferSize: + var = g_regs.display_transfer.output_size; + break; + + case Registers::DisplayInputBufferSize: + var = g_regs.display_transfer.input_size; + break; + + case Registers::DisplayTransferFlags: + var = g_regs.display_transfer.flags; + break; + + // Not sure if this is supposed to be readable + case Registers::DisplayTriggerTransfer: + var = g_regs.display_transfer.trigger; + break; + case Registers::CommandListSize: var = g_regs.command_list_size; break; @@ -129,6 +154,33 @@ inline void Read(T &var, const u32 addr) { template inline void Write(u32 addr, const T data) { switch (static_cast(addr)) { + case Registers::DisplayInputBufferAddr: + g_regs.display_transfer.input_address = data; + break; + + case Registers::DisplayOutputBufferAddr: + g_regs.display_transfer.output_address = data; + break; + + case Registers::DisplayOutputBufferSize: + g_regs.display_transfer.output_size = data; + break; + + case Registers::DisplayInputBufferSize: + g_regs.display_transfer.input_size = data; + break; + + case Registers::DisplayTransferFlags: + g_regs.display_transfer.flags = data; + break; + + case Registers::DisplayTriggerTransfer: + g_regs.display_transfer.trigger = data; + if (g_regs.display_transfer.trigger & 1) { + // TODO: Perform display transfer! + } + break; + case Registers::CommandListSize: g_regs.command_list_size = data; break; diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 58058d732..29eb7ed81 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -5,6 +5,7 @@ #pragma once #include "common/common_types.h" +#include "common/bit_field.h" namespace GPU { @@ -44,6 +45,45 @@ struct Registers { u32 framebuffer_sub_right_1; u32 framebuffer_sub_right_2; + struct { + u32 input_address; + u32 output_address; + + inline u32 GetPhysicalInputAddress() const { + return input_address * 8; + } + + inline u32 GetPhysicalOutputAddress() const { + return output_address * 8; + } + + union { + u32 output_size; + + BitField< 0, 16, u32> output_width; + BitField<16, 16, u32> output_height; + }; + + union { + u32 input_size; + + BitField< 0, 16, u32> input_width; + BitField<16, 16, u32> input_height; + }; + + union { + u32 flags; + + BitField< 0, 1, u32> flip_data; + BitField< 8, 3, u32> input_format; + BitField<12, 3, u32> output_format; + BitField<16, 1, u32> output_tiled; + }; + + u32 unknown; + u32 trigger; + } display_transfer; + u32 command_list_size; u32 command_list_address; u32 command_processing_enabled; -- cgit v1.2.3 From bbc6f314eb56ab1cf0a4b800750130de515cdd0f Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:01:14 +0200 Subject: GPU: Properly implement display transfers. --- src/core/hw/gpu.cpp | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index a400338b5..e05e1b023 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -177,7 +177,25 @@ inline void Write(u32 addr, const T data) { case Registers::DisplayTriggerTransfer: g_regs.display_transfer.trigger = data; if (g_regs.display_transfer.trigger & 1) { - // TODO: Perform display transfer! + u8* source_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalInputAddress()); + u8* dest_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalOutputAddress()); + + + // TODO: Perform display transfer correctly! + for (int y = 0; y < g_regs.display_transfer.output_height; ++y) { + // TODO: Copy size is just guesswork! + memcpy(dest_pointer + y * g_regs.display_transfer.output_width * 4, + source_pointer + y * g_regs.display_transfer.input_width * 4, + g_regs.display_transfer.output_width * 4); + } + + // Clear previous contents until we implement proper buffer clearing + memset(source_pointer, 0x20, g_regs.display_transfer.input_width*g_regs.display_transfer.input_height*4); + DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", + g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4, + g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height, + g_regs.display_transfer.GetPhysicalOutputAddress(), (int)g_regs.display_transfer.output_width, (int)g_regs.display_transfer.output_height, + (int)g_regs.display_transfer.output_format); } break; -- cgit v1.2.3 From 0b4055c1520fbe7f697d2f1f93a85b559504cca4 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:10:08 +0200 Subject: GPU: Add proper framebuffer register handling. --- src/core/hw/gpu.cpp | 53 +++++++++++++++++++++++++++++++++++++++++++- src/core/hw/gpu.h | 63 ++++++++++++++++++++++++++++++++++++++++++++--------- 2 files changed, 105 insertions(+), 11 deletions(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index e05e1b023..fad3439c8 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -84,6 +84,10 @@ const u8* GetFramebufferPointer(const u32 address) { template inline void Read(T &var, const u32 addr) { switch (addr) { + case Registers::FramebufferTopSize: + var = g_regs.top_framebuffer.size; + break; + case Registers::FramebufferTopLeft1: var = g_regs.framebuffer_top_left_1; break; @@ -92,6 +96,18 @@ inline void Read(T &var, const u32 addr) { var = g_regs.framebuffer_top_left_2; break; + case Registers::FramebufferTopFormat: + var = g_regs.top_framebuffer.format; + break; + + case Registers::FramebufferTopSwapBuffers: + var = g_regs.top_framebuffer.active_fb; + break; + + case Registers::FramebufferTopStride: + var = g_regs.top_framebuffer.stride; + break; + case Registers::FramebufferTopRight1: var = g_regs.framebuffer_top_right_1; break; @@ -100,6 +116,10 @@ inline void Read(T &var, const u32 addr) { var = g_regs.framebuffer_top_right_2; break; + case Registers::FramebufferSubSize: + var = g_regs.sub_framebuffer.size; + break; + case Registers::FramebufferSubLeft1: var = g_regs.framebuffer_sub_left_1; break; @@ -108,6 +128,26 @@ inline void Read(T &var, const u32 addr) { var = g_regs.framebuffer_sub_right_1; break; + case Registers::FramebufferSubFormat: + var = g_regs.sub_framebuffer.format; + break; + + case Registers::FramebufferSubSwapBuffers: + var = g_regs.sub_framebuffer.active_fb; + break; + + case Registers::FramebufferSubStride: + var = g_regs.sub_framebuffer.stride; + break; + + case Registers::FramebufferSubLeft2: + var = g_regs.framebuffer_sub_left_2; + break; + + case Registers::FramebufferSubRight2: + var = g_regs.framebuffer_sub_right_2; + break; + case Registers::DisplayInputBufferAddr: var = g_regs.display_transfer.input_address; break; @@ -154,6 +194,17 @@ inline void Read(T &var, const u32 addr) { template inline void Write(u32 addr, const T data) { switch (static_cast(addr)) { + // TODO: Framebuffer registers!! + case Registers::FramebufferTopSwapBuffers: + g_regs.top_framebuffer.active_fb = data; + // TODO: Not sure if this should only be done upon a change! + break; + + case Registers::FramebufferSubSwapBuffers: + g_regs.sub_framebuffer.active_fb = data; + // TODO: Not sure if this should only be done upon a change! + break; + case Registers::DisplayInputBufferAddr: g_regs.display_transfer.input_address = data; break; @@ -195,7 +246,7 @@ inline void Write(u32 addr, const T data) { g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4, g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height, g_regs.display_transfer.GetPhysicalOutputAddress(), (int)g_regs.display_transfer.output_width, (int)g_regs.display_transfer.output_height, - (int)g_regs.display_transfer.output_format); + (int)g_regs.display_transfer.output_format.Value()); } break; diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 29eb7ed81..50c360814 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -14,14 +14,23 @@ static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of i struct Registers { enum Id : u32 { - FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left - FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left - FramebufferTopRight1 = 0x1EF00494, // Main LCD, first framebuffer for 3D right - FramebufferTopRight2 = 0x1EF00498, // Main LCD, second framebuffer for 3D right - FramebufferSubLeft1 = 0x1EF00568, // Sub LCD, first framebuffer - FramebufferSubLeft2 = 0x1EF0056C, // Sub LCD, second framebuffer - FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer - FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer + FramebufferTopSize = 0x1EF0045C, + FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left + FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left + FramebufferTopFormat = 0x1EF00470, + FramebufferTopSwapBuffers = 0x1EF00478, + FramebufferTopStride = 0x1EF00490, // framebuffer row stride? + FramebufferTopRight1 = 0x1EF00494, // Main LCD, first framebuffer for 3D right + FramebufferTopRight2 = 0x1EF00498, // Main LCD, second framebuffer for 3D right + + FramebufferSubSize = 0x1EF0055C, + FramebufferSubLeft1 = 0x1EF00568, // Sub LCD, first framebuffer + FramebufferSubLeft2 = 0x1EF0056C, // Sub LCD, second framebuffer + FramebufferSubFormat = 0x1EF00570, + FramebufferSubSwapBuffers = 0x1EF00578, + FramebufferSubStride = 0x1EF00590, // framebuffer row stride? + FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer + FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer DisplayInputBufferAddr = 0x1EF00C00, DisplayOutputBufferAddr = 0x1EF00C04, @@ -36,6 +45,15 @@ struct Registers { ProcessCommandList = 0x1EF018F0, }; + enum class FramebufferFormat : u32 { + RGBA8 = 0, + RGB8 = 1, + RGB565 = 2, + RGB5A1 = 3, + RGBA4 = 4, + }; + + // TODO: Move these into the framebuffer struct u32 framebuffer_top_left_1; u32 framebuffer_top_left_2; u32 framebuffer_top_right_1; @@ -45,6 +63,31 @@ struct Registers { u32 framebuffer_sub_right_1; u32 framebuffer_sub_right_2; + struct FrameBufferConfig { + union { + u32 size; + + BitField< 0, 16, u32> width; + BitField<16, 16, u32> height; + }; + + union { + u32 format; + + BitField< 0, 3, FramebufferFormat> color_format; + }; + + union { + u32 active_fb; + + BitField<0, 1, u32> second_fb_active; + }; + + u32 stride; + }; + FrameBufferConfig top_framebuffer; + FrameBufferConfig sub_framebuffer; + struct { u32 input_address; u32 output_address; @@ -75,8 +118,8 @@ struct Registers { u32 flags; BitField< 0, 1, u32> flip_data; - BitField< 8, 3, u32> input_format; - BitField<12, 3, u32> output_format; + BitField< 8, 3, FramebufferFormat> input_format; + BitField<12, 3, FramebufferFormat> output_format; BitField<16, 1, u32> output_tiled; }; -- cgit v1.2.3 From baf0aa04f50dff257b57fa78786e53b97c1e6abb Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Wed, 4 Jun 2014 18:30:23 +0200 Subject: GPU: Emulate memory fills. --- src/core/hw/gpu.cpp | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++-- src/core/hw/gpu.h | 26 +++++++++++++++++++++++++ 2 files changed, 80 insertions(+), 2 deletions(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index fad3439c8..230a12d46 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -84,6 +84,26 @@ const u8* GetFramebufferPointer(const u32 address) { template inline void Read(T &var, const u32 addr) { switch (addr) { + case Registers::MemoryFillStart1: + case Registers::MemoryFillStart2: + var = g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start; + break; + + case Registers::MemoryFillEnd1: + case Registers::MemoryFillEnd2: + var = g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end; + break; + + case Registers::MemoryFillSize1: + case Registers::MemoryFillSize2: + var = g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size; + break; + + case Registers::MemoryFillValue1: + case Registers::MemoryFillValue2: + var = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10].value; + break; + case Registers::FramebufferTopSize: var = g_regs.top_framebuffer.size; break; @@ -194,6 +214,40 @@ inline void Read(T &var, const u32 addr) { template inline void Write(u32 addr, const T data) { switch (static_cast(addr)) { + case Registers::MemoryFillStart1: + case Registers::MemoryFillStart2: + g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start = data; + break; + + case Registers::MemoryFillEnd1: + case Registers::MemoryFillEnd2: + g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end = data; + break; + + case Registers::MemoryFillSize1: + case Registers::MemoryFillSize2: + g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size = data; + break; + + case Registers::MemoryFillValue1: + case Registers::MemoryFillValue2: + { + Registers::MemoryFillConfig& config = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10]; + config.value = data; + + // TODO: Not sure if this check should be done at GSP level instead + if (config.address_start) { + // TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all + u32* start = (u32*)Memory::GetPointer(config.GetStartAddress()); + u32* end = (u32*)Memory::GetPointer(config.GetEndAddress()); + for (u32* ptr = start; ptr < end; ++ptr) + *ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation + + DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress()); + } + break; + } + // TODO: Framebuffer registers!! case Registers::FramebufferTopSwapBuffers: g_regs.top_framebuffer.active_fb = data; @@ -240,8 +294,6 @@ inline void Write(u32 addr, const T data) { g_regs.display_transfer.output_width * 4); } - // Clear previous contents until we implement proper buffer clearing - memset(source_pointer, 0x20, g_regs.display_transfer.input_width*g_regs.display_transfer.input_height*4); DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4, g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height, diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 50c360814..47d7fcb26 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -14,6 +14,15 @@ static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of i struct Registers { enum Id : u32 { + MemoryFillStart1 = 0x1EF00010, + MemoryFillEnd1 = 0x1EF00014, + MemoryFillSize1 = 0x1EF00018, + MemoryFillValue1 = 0x1EF0001C, + MemoryFillStart2 = 0x1EF00020, + MemoryFillEnd2 = 0x1EF00024, + MemoryFillSize2 = 0x1EF00028, + MemoryFillValue2 = 0x1EF0002C, + FramebufferTopSize = 0x1EF0045C, FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left @@ -53,6 +62,23 @@ struct Registers { RGBA4 = 4, }; + struct MemoryFillConfig { + u32 address_start; + u32 address_end; // ? + u32 size; + u32 value; // ? + + inline u32 GetStartAddress() const { + return address_start * 8; + } + + inline u32 GetEndAddress() const { + return address_end * 8; + } + }; + + MemoryFillConfig memory_fill[2]; + // TODO: Move these into the framebuffer struct u32 framebuffer_top_left_1; u32 framebuffer_top_left_2; -- cgit v1.2.3 From 46950ee4de0b1f2c30c26467b60e38c6a38d19b8 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:14:15 +0200 Subject: GPU: Initialize GPU registers to some sensible default state. --- src/core/hw/gpu.cpp | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index 230a12d46..0ee6b7c3b 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -353,7 +353,22 @@ void Update() { /// Initialize hardware void Init() { g_last_ticks = Core::g_app_core->GetTicks(); - SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM); +// SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM); + SetFramebufferLocation(FRAMEBUFFER_LOCATION_VRAM); + + // TODO: Width should be 240 instead? + g_regs.top_framebuffer.width = 480; + g_regs.top_framebuffer.height = 400; + g_regs.top_framebuffer.stride = 480*3; + g_regs.top_framebuffer.color_format = Registers::FramebufferFormat::RGB8; + g_regs.top_framebuffer.active_fb = 0; + + g_regs.sub_framebuffer.width = 480; + g_regs.sub_framebuffer.height = 400; + g_regs.sub_framebuffer.stride = 480*3; + g_regs.sub_framebuffer.color_format = Registers::FramebufferFormat::RGB8; + g_regs.sub_framebuffer.active_fb = 0; + NOTICE_LOG(GPU, "initialized OK"); } -- cgit v1.2.3 From 9d618d0b705e3b8de5594512a555f469631e274b Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:29:12 +0200 Subject: GPU: Interface cleanup. --- src/core/hw/gpu.cpp | 29 +++++++++++++++++------------ src/core/hw/gpu.h | 4 +++- 2 files changed, 20 insertions(+), 13 deletions(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index 0ee6b7c3b..49fc574bc 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -53,10 +53,10 @@ void SetFramebufferLocation(const FramebufferLocation mode) { * Gets the location of the framebuffers * @return Location of framebuffers as FramebufferLocation enum */ -const FramebufferLocation GetFramebufferLocation() { - if ((g_regs.framebuffer_top_right_1 & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) { +FramebufferLocation GetFramebufferLocation(u32 address) { + if ((address & ~Memory::VRAM_MASK) == Memory::VRAM_PADDR) { return FRAMEBUFFER_LOCATION_VRAM; - } else if ((g_regs.framebuffer_top_right_1 & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) { + } else if ((address & ~Memory::FCRAM_MASK) == Memory::FCRAM_PADDR) { return FRAMEBUFFER_LOCATION_FCRAM; } else { ERROR_LOG(GPU, "unknown framebuffer location!"); @@ -64,21 +64,26 @@ const FramebufferLocation GetFramebufferLocation() { return FRAMEBUFFER_LOCATION_UNKNOWN; } +u32 GetFramebufferAddr(const u32 address) { + switch (GetFramebufferLocation(address)) { + case FRAMEBUFFER_LOCATION_FCRAM: + return Memory::VirtualAddressFromPhysical_FCRAM(address); + case FRAMEBUFFER_LOCATION_VRAM: + return Memory::VirtualAddressFromPhysical_VRAM(address); + default: + ERROR_LOG(GPU, "unknown framebuffer location"); + } + return 0; +} + /** * Gets a read-only pointer to a framebuffer in memory * @param address Physical address of framebuffer * @return Returns const pointer to raw framebuffer */ const u8* GetFramebufferPointer(const u32 address) { - switch (GetFramebufferLocation()) { - case FRAMEBUFFER_LOCATION_FCRAM: - return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_FCRAM(address)); - case FRAMEBUFFER_LOCATION_VRAM: - return (const u8*)Memory::GetPointer(Memory::VirtualAddressFromPhysical_VRAM(address)); - default: - ERROR_LOG(GPU, "unknown framebuffer location"); - } - return NULL; + u32 addr = GetFramebufferAddr(address); + return (addr != 0) ? Memory::GetPointer(addr) : nullptr; } template diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 47d7fcb26..b66cf4a37 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -219,10 +219,12 @@ void SetFramebufferLocation(const FramebufferLocation mode); */ const u8* GetFramebufferPointer(const u32 address); +u32 GetFramebufferAddr(const u32 address); + /** * Gets the location of the framebuffers */ -const FramebufferLocation GetFramebufferLocation(); +FramebufferLocation GetFramebufferLocation(u32 address); template inline void Read(T &var, const u32 addr); -- cgit v1.2.3 From 357d893b2642e91d5c44a7da7ccdcbe837f46b0a Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 11 Jul 2014 19:48:01 +0200 Subject: GPU: Make framebuffer code format-aware. --- src/core/hw/gpu.cpp | 53 +++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 47 insertions(+), 6 deletions(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index 49fc574bc..31989f445 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -290,13 +290,54 @@ inline void Write(u32 addr, const T data) { u8* source_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalInputAddress()); u8* dest_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalOutputAddress()); - - // TODO: Perform display transfer correctly! for (int y = 0; y < g_regs.display_transfer.output_height; ++y) { - // TODO: Copy size is just guesswork! - memcpy(dest_pointer + y * g_regs.display_transfer.output_width * 4, - source_pointer + y * g_regs.display_transfer.input_width * 4, - g_regs.display_transfer.output_width * 4); + // TODO: Why does the register seem to hold twice the framebuffer width? + for (int x = 0; x < g_regs.display_transfer.output_width / 2; ++x) { + int source[4] = { 0, 0, 0, 0}; // rgba; + + switch (g_regs.display_transfer.input_format) { + case Registers::FramebufferFormat::RGBA8: + { + // TODO: Most likely got the component order messed up. + u8* srcptr = source_pointer + x * 4 + y * g_regs.display_transfer.input_width * 4 / 2; + source[0] = srcptr[0]; // blue + source[1] = srcptr[1]; // green + source[2] = srcptr[2]; // red + source[3] = srcptr[3]; // alpha + break; + } + + default: + ERROR_LOG(GPU, "Unknown source framebuffer format %x", (int)g_regs.display_transfer.input_format.Value()); + break; + } + + switch (g_regs.display_transfer.output_format) { + /*case Registers::FramebufferFormat::RGBA8: + { + // TODO: Untested + u8* dstptr = (u32*)(dest_pointer + x * 4 + y * g_regs.display_transfer.output_width * 4); + dstptr[0] = source[0]; + dstptr[1] = source[1]; + dstptr[2] = source[2]; + dstptr[3] = source[3]; + break; + }*/ + + case Registers::FramebufferFormat::RGB8: + { + u8* dstptr = dest_pointer + x * 3 + y * g_regs.display_transfer.output_width * 3 / 2; + dstptr[0] = source[0]; // blue + dstptr[1] = source[1]; // green + dstptr[2] = source[2]; // red + break; + } + + default: + ERROR_LOG(GPU, "Unknown destination framebuffer format %x", static_cast(g_regs.display_transfer.output_format.Value())); + break; + } + } } DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", -- cgit v1.2.3 From 75775e9ef41248592cb2c27ae69737e46499e705 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Wed, 16 Jul 2014 11:24:09 +0200 Subject: GPU: Make use of RegisterSet. --- src/core/hw/gpu.cpp | 342 ++++++++++++++++------------------------------------ src/core/hw/gpu.h | 136 +++++++++++---------- 2 files changed, 172 insertions(+), 306 deletions(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index 31989f445..372e4f4cc 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -15,38 +15,48 @@ namespace GPU { -Registers g_regs; +RegisterSet g_regs; u64 g_last_ticks = 0; ///< Last CPU ticks /** * Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM - * @param + * @param */ void SetFramebufferLocation(const FramebufferLocation mode) { switch (mode) { case FRAMEBUFFER_LOCATION_FCRAM: - g_regs.framebuffer_top_left_1 = PADDR_TOP_LEFT_FRAME1; - g_regs.framebuffer_top_left_2 = PADDR_TOP_LEFT_FRAME2; - g_regs.framebuffer_top_right_1 = PADDR_TOP_RIGHT_FRAME1; - g_regs.framebuffer_top_right_2 = PADDR_TOP_RIGHT_FRAME2; - g_regs.framebuffer_sub_left_1 = PADDR_SUB_FRAME1; - //g_regs.framebuffer_sub_left_2 = unknown; - g_regs.framebuffer_sub_right_1 = PADDR_SUB_FRAME2; - //g_regs.framebufferr_sub_right_2 = unknown; + { + auto& framebuffer_top = g_regs.Get(); + auto& framebuffer_sub = g_regs.Get(); + + framebuffer_top.data.address_left1 = PADDR_TOP_LEFT_FRAME1; + framebuffer_top.data.address_left2 = PADDR_TOP_LEFT_FRAME2; + framebuffer_top.data.address_right1 = PADDR_TOP_RIGHT_FRAME1; + framebuffer_top.data.address_right2 = PADDR_TOP_RIGHT_FRAME2; + framebuffer_sub.data.address_left1 = PADDR_SUB_FRAME1; + //framebuffer_sub.data.address_left2 = unknown; + framebuffer_sub.data.address_right1 = PADDR_SUB_FRAME2; + //framebuffer_sub.data.address_right2 = unknown; break; + } case FRAMEBUFFER_LOCATION_VRAM: - g_regs.framebuffer_top_left_1 = PADDR_VRAM_TOP_LEFT_FRAME1; - g_regs.framebuffer_top_left_2 = PADDR_VRAM_TOP_LEFT_FRAME2; - g_regs.framebuffer_top_right_1 = PADDR_VRAM_TOP_RIGHT_FRAME1; - g_regs.framebuffer_top_right_2 = PADDR_VRAM_TOP_RIGHT_FRAME2; - g_regs.framebuffer_sub_left_1 = PADDR_VRAM_SUB_FRAME1; - //g_regs.framebuffer_sub_left_2 = unknown; - g_regs.framebuffer_sub_right_1 = PADDR_VRAM_SUB_FRAME2; - //g_regs.framebufferr_sub_right_2 = unknown; + { + auto& framebuffer_top = g_regs.Get(); + auto& framebuffer_sub = g_regs.Get(); + + framebuffer_top.data.address_left1 = PADDR_VRAM_TOP_LEFT_FRAME1; + framebuffer_top.data.address_left2 = PADDR_VRAM_TOP_LEFT_FRAME2; + framebuffer_top.data.address_right1 = PADDR_VRAM_TOP_RIGHT_FRAME1; + framebuffer_top.data.address_right2 = PADDR_VRAM_TOP_RIGHT_FRAME2; + framebuffer_sub.data.address_left1 = PADDR_VRAM_SUB_FRAME1; + //framebuffer_sub.data.address_left2 = unknown; + framebuffer_sub.data.address_right1 = PADDR_VRAM_SUB_FRAME2; + //framebuffer_sub.data.address_right2 = unknown; break; } + } } /** @@ -87,219 +97,73 @@ const u8* GetFramebufferPointer(const u32 address) { } template -inline void Read(T &var, const u32 addr) { - switch (addr) { - case Registers::MemoryFillStart1: - case Registers::MemoryFillStart2: - var = g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start; - break; - - case Registers::MemoryFillEnd1: - case Registers::MemoryFillEnd2: - var = g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end; - break; - - case Registers::MemoryFillSize1: - case Registers::MemoryFillSize2: - var = g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size; - break; - - case Registers::MemoryFillValue1: - case Registers::MemoryFillValue2: - var = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10].value; - break; - - case Registers::FramebufferTopSize: - var = g_regs.top_framebuffer.size; - break; - - case Registers::FramebufferTopLeft1: - var = g_regs.framebuffer_top_left_1; - break; - - case Registers::FramebufferTopLeft2: - var = g_regs.framebuffer_top_left_2; - break; - - case Registers::FramebufferTopFormat: - var = g_regs.top_framebuffer.format; - break; - - case Registers::FramebufferTopSwapBuffers: - var = g_regs.top_framebuffer.active_fb; - break; - - case Registers::FramebufferTopStride: - var = g_regs.top_framebuffer.stride; - break; - - case Registers::FramebufferTopRight1: - var = g_regs.framebuffer_top_right_1; - break; - - case Registers::FramebufferTopRight2: - var = g_regs.framebuffer_top_right_2; - break; - - case Registers::FramebufferSubSize: - var = g_regs.sub_framebuffer.size; - break; - - case Registers::FramebufferSubLeft1: - var = g_regs.framebuffer_sub_left_1; - break; - - case Registers::FramebufferSubRight1: - var = g_regs.framebuffer_sub_right_1; - break; - - case Registers::FramebufferSubFormat: - var = g_regs.sub_framebuffer.format; - break; - - case Registers::FramebufferSubSwapBuffers: - var = g_regs.sub_framebuffer.active_fb; - break; - - case Registers::FramebufferSubStride: - var = g_regs.sub_framebuffer.stride; - break; - - case Registers::FramebufferSubLeft2: - var = g_regs.framebuffer_sub_left_2; - break; - - case Registers::FramebufferSubRight2: - var = g_regs.framebuffer_sub_right_2; - break; - - case Registers::DisplayInputBufferAddr: - var = g_regs.display_transfer.input_address; - break; +inline void Read(T &var, const u32 raw_addr) { + u32 addr = raw_addr - 0x1EF00000; + int index = addr / 4; - case Registers::DisplayOutputBufferAddr: - var = g_regs.display_transfer.output_address; - break; - - case Registers::DisplayOutputBufferSize: - var = g_regs.display_transfer.output_size; - break; - - case Registers::DisplayInputBufferSize: - var = g_regs.display_transfer.input_size; - break; - - case Registers::DisplayTransferFlags: - var = g_regs.display_transfer.flags; - break; - - // Not sure if this is supposed to be readable - case Registers::DisplayTriggerTransfer: - var = g_regs.display_transfer.trigger; - break; - - case Registers::CommandListSize: - var = g_regs.command_list_size; - break; - - case Registers::CommandListAddress: - var = g_regs.command_list_address; - break; - - case Registers::ProcessCommandList: - var = g_regs.command_processing_enabled; - break; - - default: + // Reads other than u32 are untested, so I'd rather have them abort than silently fail + if (index >= Regs::NumIds || !std::is_same::value) + { ERROR_LOG(GPU, "unknown Read%d @ 0x%08X", sizeof(var) * 8, addr); - break; + return; } + + var = g_regs[static_cast(addr / 4)]; } template inline void Write(u32 addr, const T data) { - switch (static_cast(addr)) { - case Registers::MemoryFillStart1: - case Registers::MemoryFillStart2: - g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start = data; - break; + addr -= 0x1EF00000; + int index = addr / 4; - case Registers::MemoryFillEnd1: - case Registers::MemoryFillEnd2: - g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end = data; - break; + // Writes other than u32 are untested, so I'd rather have them abort than silently fail + if (index >= Regs::NumIds || !std::is_same::value) + { + ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr); + return; + } - case Registers::MemoryFillSize1: - case Registers::MemoryFillSize2: - g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size = data; - break; + g_regs[static_cast(index)] = data; + + switch (static_cast(index)) { - case Registers::MemoryFillValue1: - case Registers::MemoryFillValue2: + // Memory fills are triggered once the fill value is written. + // NOTE: This is not verified. + case Regs::MemoryFill + 3: + case Regs::MemoryFill + 7: { - Registers::MemoryFillConfig& config = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10]; - config.value = data; + const auto& config = g_regs.Get(static_cast(index - 3)); // TODO: Not sure if this check should be done at GSP level instead - if (config.address_start) { + if (config.data.address_start) { // TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all - u32* start = (u32*)Memory::GetPointer(config.GetStartAddress()); - u32* end = (u32*)Memory::GetPointer(config.GetEndAddress()); + u32* start = (u32*)Memory::GetPointer(config.data.GetStartAddress()); + u32* end = (u32*)Memory::GetPointer(config.data.GetEndAddress()); for (u32* ptr = start; ptr < end; ++ptr) - *ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation + *ptr = bswap32(config.data.value); // TODO: This is just a workaround to missing framebuffer format emulation - DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress()); + DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.data.GetStartAddress(), config.data.GetEndAddress()); } break; } - // TODO: Framebuffer registers!! - case Registers::FramebufferTopSwapBuffers: - g_regs.top_framebuffer.active_fb = data; - // TODO: Not sure if this should only be done upon a change! - break; - - case Registers::FramebufferSubSwapBuffers: - g_regs.sub_framebuffer.active_fb = data; - // TODO: Not sure if this should only be done upon a change! - break; - - case Registers::DisplayInputBufferAddr: - g_regs.display_transfer.input_address = data; - break; - - case Registers::DisplayOutputBufferAddr: - g_regs.display_transfer.output_address = data; - break; - - case Registers::DisplayOutputBufferSize: - g_regs.display_transfer.output_size = data; - break; - - case Registers::DisplayInputBufferSize: - g_regs.display_transfer.input_size = data; - break; - - case Registers::DisplayTransferFlags: - g_regs.display_transfer.flags = data; - break; - - case Registers::DisplayTriggerTransfer: - g_regs.display_transfer.trigger = data; - if (g_regs.display_transfer.trigger & 1) { - u8* source_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalInputAddress()); - u8* dest_pointer = Memory::GetPointer(g_regs.display_transfer.GetPhysicalOutputAddress()); + case Regs::DisplayTransfer + 6: + { + const auto& config = g_regs.Get(); + if (config.data.trigger & 1) { + u8* source_pointer = Memory::GetPointer(config.data.GetPhysicalInputAddress()); + u8* dest_pointer = Memory::GetPointer(config.data.GetPhysicalOutputAddress()); - for (int y = 0; y < g_regs.display_transfer.output_height; ++y) { + for (int y = 0; y < config.data.output_height; ++y) { // TODO: Why does the register seem to hold twice the framebuffer width? - for (int x = 0; x < g_regs.display_transfer.output_width / 2; ++x) { + for (int x = 0; x < config.data.output_width / 2; ++x) { int source[4] = { 0, 0, 0, 0}; // rgba; - switch (g_regs.display_transfer.input_format) { - case Registers::FramebufferFormat::RGBA8: + switch (config.data.input_format) { + case Regs::FramebufferFormat::RGBA8: { // TODO: Most likely got the component order messed up. - u8* srcptr = source_pointer + x * 4 + y * g_regs.display_transfer.input_width * 4 / 2; + u8* srcptr = source_pointer + x * 4 + y * config.data.input_width * 4 / 2; source[0] = srcptr[0]; // blue source[1] = srcptr[1]; // green source[2] = srcptr[2]; // red @@ -308,15 +172,15 @@ inline void Write(u32 addr, const T data) { } default: - ERROR_LOG(GPU, "Unknown source framebuffer format %x", (int)g_regs.display_transfer.input_format.Value()); + ERROR_LOG(GPU, "Unknown source framebuffer format %x", config.data.input_format.Value()); break; } - switch (g_regs.display_transfer.output_format) { - /*case Registers::FramebufferFormat::RGBA8: + switch (config.data.output_format) { + /*case Regs::FramebufferFormat::RGBA8: { // TODO: Untested - u8* dstptr = (u32*)(dest_pointer + x * 4 + y * g_regs.display_transfer.output_width * 4); + u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.data.output_width * 4); dstptr[0] = source[0]; dstptr[1] = source[1]; dstptr[2] = source[2]; @@ -324,9 +188,9 @@ inline void Write(u32 addr, const T data) { break; }*/ - case Registers::FramebufferFormat::RGB8: + case Regs::FramebufferFormat::RGB8: { - u8* dstptr = dest_pointer + x * 3 + y * g_regs.display_transfer.output_width * 3 / 2; + u8* dstptr = dest_pointer + x * 3 + y * config.data.output_width * 3 / 2; dstptr[0] = source[0]; // blue dstptr[1] = source[1]; // green dstptr[2] = source[2]; // red @@ -334,40 +198,34 @@ inline void Write(u32 addr, const T data) { } default: - ERROR_LOG(GPU, "Unknown destination framebuffer format %x", static_cast(g_regs.display_transfer.output_format.Value())); + ERROR_LOG(GPU, "Unknown destination framebuffer format %x", config.data.output_format.Value()); break; } } } DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", - g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4, - g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height, - g_regs.display_transfer.GetPhysicalOutputAddress(), (int)g_regs.display_transfer.output_width, (int)g_regs.display_transfer.output_height, - (int)g_regs.display_transfer.output_format.Value()); + config.data.output_height * config.data.output_width * 4, + config.data.GetPhysicalInputAddress(), (int)config.data.input_width, (int)config.data.input_height, + config.data.GetPhysicalOutputAddress(), (int)config.data.output_width, (int)config.data.output_height, + config.data.output_format.Value()); } break; + } - case Registers::CommandListSize: - g_regs.command_list_size = data; - break; - - case Registers::CommandListAddress: - g_regs.command_list_address = data; - break; - - case Registers::ProcessCommandList: - g_regs.command_processing_enabled = data; - if (g_regs.command_processing_enabled & 1) + case Regs::CommandProcessor + 4: + { + const auto& config = g_regs.Get(); + if (config.data.trigger & 1) { - // u32* buffer = (u32*)Memory::GetPointer(g_regs.command_list_address << 3); - ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", g_regs.command_list_size, g_regs.command_list_address << 3); + // u32* buffer = (u32*)Memory::GetPointer(config.data.address << 3); + ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", config.data.size, config.data.address << 3); // TODO: Process command list! } break; + } default: - ERROR_LOG(GPU, "unknown Write%d 0x%08X @ 0x%08X", sizeof(data) * 8, data, addr); break; } } @@ -402,18 +260,20 @@ void Init() { // SetFramebufferLocation(FRAMEBUFFER_LOCATION_FCRAM); SetFramebufferLocation(FRAMEBUFFER_LOCATION_VRAM); + auto& framebuffer_top = g_regs.Get(); + auto& framebuffer_sub = g_regs.Get(); // TODO: Width should be 240 instead? - g_regs.top_framebuffer.width = 480; - g_regs.top_framebuffer.height = 400; - g_regs.top_framebuffer.stride = 480*3; - g_regs.top_framebuffer.color_format = Registers::FramebufferFormat::RGB8; - g_regs.top_framebuffer.active_fb = 0; - - g_regs.sub_framebuffer.width = 480; - g_regs.sub_framebuffer.height = 400; - g_regs.sub_framebuffer.stride = 480*3; - g_regs.sub_framebuffer.color_format = Registers::FramebufferFormat::RGB8; - g_regs.sub_framebuffer.active_fb = 0; + framebuffer_top.data.width = 480; + framebuffer_top.data.height = 400; + framebuffer_top.data.stride = 480*3; + framebuffer_top.data.color_format = Regs::FramebufferFormat::RGB8; + framebuffer_top.data.active_fb = 0; + + framebuffer_sub.data.width = 480; + framebuffer_sub.data.height = 400; + framebuffer_sub.data.stride = 480*3; + framebuffer_sub.data.color_format = Regs::FramebufferFormat::RGB8; + framebuffer_sub.data.active_fb = 0; NOTICE_LOG(GPU, "initialized OK"); } diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index b66cf4a37..ce524bd02 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -6,54 +6,31 @@ #include "common/common_types.h" #include "common/bit_field.h" +#include "common/register_set.h" namespace GPU { static const u32 kFrameCycles = 268123480 / 60; ///< 268MHz / 60 frames per second static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of instructions/frame -struct Registers { +// MMIO region 0x1EFxxxxx +struct Regs { enum Id : u32 { - MemoryFillStart1 = 0x1EF00010, - MemoryFillEnd1 = 0x1EF00014, - MemoryFillSize1 = 0x1EF00018, - MemoryFillValue1 = 0x1EF0001C, - MemoryFillStart2 = 0x1EF00020, - MemoryFillEnd2 = 0x1EF00024, - MemoryFillSize2 = 0x1EF00028, - MemoryFillValue2 = 0x1EF0002C, - - FramebufferTopSize = 0x1EF0045C, - FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left - FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left - FramebufferTopFormat = 0x1EF00470, - FramebufferTopSwapBuffers = 0x1EF00478, - FramebufferTopStride = 0x1EF00490, // framebuffer row stride? - FramebufferTopRight1 = 0x1EF00494, // Main LCD, first framebuffer for 3D right - FramebufferTopRight2 = 0x1EF00498, // Main LCD, second framebuffer for 3D right - - FramebufferSubSize = 0x1EF0055C, - FramebufferSubLeft1 = 0x1EF00568, // Sub LCD, first framebuffer - FramebufferSubLeft2 = 0x1EF0056C, // Sub LCD, second framebuffer - FramebufferSubFormat = 0x1EF00570, - FramebufferSubSwapBuffers = 0x1EF00578, - FramebufferSubStride = 0x1EF00590, // framebuffer row stride? - FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer - FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer - - DisplayInputBufferAddr = 0x1EF00C00, - DisplayOutputBufferAddr = 0x1EF00C04, - DisplayOutputBufferSize = 0x1EF00C08, - DisplayInputBufferSize = 0x1EF00C0C, - DisplayTransferFlags = 0x1EF00C10, - // Unknown?? - DisplayTriggerTransfer = 0x1EF00C18, - - CommandListSize = 0x1EF018E0, - CommandListAddress = 0x1EF018E8, - ProcessCommandList = 0x1EF018F0, + MemoryFill = 0x00004, // + 5,6,7; second block at 8-11 + + FramebufferTop = 0x00117, // + 11a,11b,11c,11d(?),11e...126 + FramebufferBottom = 0x00157, // + 15a,15b,15c,15d(?),15e...166 + + DisplayTransfer = 0x00300, // + 301,302,303,304,305,306 + + CommandProcessor = 0x00638, // + 63a,63c + + NumIds = 0x01000 }; + template + union Struct; + enum class FramebufferFormat : u32 { RGBA8 = 0, RGB8 = 1, @@ -62,7 +39,11 @@ struct Registers { RGBA4 = 4, }; - struct MemoryFillConfig { +}; + +template<> +union Regs::Struct { + struct { u32 address_start; u32 address_end; // ? u32 size; @@ -75,21 +56,15 @@ struct Registers { inline u32 GetEndAddress() const { return address_end * 8; } - }; - - MemoryFillConfig memory_fill[2]; + } data; +}; +static_assert(sizeof(Regs::Struct) == 0x10, "Structure size and register block length don't match"); - // TODO: Move these into the framebuffer struct - u32 framebuffer_top_left_1; - u32 framebuffer_top_left_2; - u32 framebuffer_top_right_1; - u32 framebuffer_top_right_2; - u32 framebuffer_sub_left_1; - u32 framebuffer_sub_left_2; - u32 framebuffer_sub_right_1; - u32 framebuffer_sub_right_2; +template<> +union Regs::Struct { + using Format = Regs::FramebufferFormat; - struct FrameBufferConfig { + struct { union { u32 size; @@ -97,22 +72,43 @@ struct Registers { BitField<16, 16, u32> height; }; + u32 pad0[2]; + + u32 address_left1; + u32 address_left2; + union { u32 format; - BitField< 0, 3, FramebufferFormat> color_format; + BitField< 0, 3, Format> color_format; }; + u32 pad1; + union { u32 active_fb; BitField<0, 1, u32> second_fb_active; }; + u32 pad2[5]; + u32 stride; - }; - FrameBufferConfig top_framebuffer; - FrameBufferConfig sub_framebuffer; + + u32 address_right1; + u32 address_right2; + } data; +}; +template<> +union Regs::Struct { + using Type = decltype(Regs::Struct::data); + Type data; +}; +static_assert(sizeof(Regs::Struct) == 0x40, "Structure size and register block length don't match"); + +template<> +union Regs::Struct { + using Format = Regs::FramebufferFormat; struct { u32 input_address; @@ -144,21 +140,31 @@ struct Registers { u32 flags; BitField< 0, 1, u32> flip_data; - BitField< 8, 3, FramebufferFormat> input_format; - BitField<12, 3, FramebufferFormat> output_format; + BitField< 8, 3, Format> input_format; + BitField<12, 3, Format> output_format; BitField<16, 1, u32> output_tiled; }; u32 unknown; u32 trigger; - } display_transfer; + } data; +}; +static_assert(sizeof(Regs::Struct) == 0x1C, "Structure size and register block length don't match"); - u32 command_list_size; - u32 command_list_address; - u32 command_processing_enabled; +template<> +union Regs::Struct { + struct { + u32 size; + u32 pad0; + u32 address; + u32 pad1; + u32 trigger; + } data; }; +static_assert(sizeof(Regs::Struct) == 0x14, "Structure size and register block length don't match"); + -extern Registers g_regs; +extern RegisterSet g_regs; enum { TOP_ASPECT_X = 0x5, @@ -208,7 +214,7 @@ enum FramebufferLocation { /** * Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM - * @param + * @param */ void SetFramebufferLocation(const FramebufferLocation mode); -- cgit v1.2.3 From 246cb75584af281596b938f898e8a3aedbcdb62a Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Wed, 16 Jul 2014 11:27:58 +0200 Subject: RegisterSet: Simplify code by using structs for register definition instead of unions. --- src/core/hw/gpu.cpp | 102 +++++++++++++++++----------------- src/core/hw/gpu.h | 154 ++++++++++++++++++++++++---------------------------- 2 files changed, 123 insertions(+), 133 deletions(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index 372e4f4cc..edffa25c5 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -30,14 +30,14 @@ void SetFramebufferLocation(const FramebufferLocation mode) { auto& framebuffer_top = g_regs.Get(); auto& framebuffer_sub = g_regs.Get(); - framebuffer_top.data.address_left1 = PADDR_TOP_LEFT_FRAME1; - framebuffer_top.data.address_left2 = PADDR_TOP_LEFT_FRAME2; - framebuffer_top.data.address_right1 = PADDR_TOP_RIGHT_FRAME1; - framebuffer_top.data.address_right2 = PADDR_TOP_RIGHT_FRAME2; - framebuffer_sub.data.address_left1 = PADDR_SUB_FRAME1; - //framebuffer_sub.data.address_left2 = unknown; - framebuffer_sub.data.address_right1 = PADDR_SUB_FRAME2; - //framebuffer_sub.data.address_right2 = unknown; + framebuffer_top.address_left1 = PADDR_TOP_LEFT_FRAME1; + framebuffer_top.address_left2 = PADDR_TOP_LEFT_FRAME2; + framebuffer_top.address_right1 = PADDR_TOP_RIGHT_FRAME1; + framebuffer_top.address_right2 = PADDR_TOP_RIGHT_FRAME2; + framebuffer_sub.address_left1 = PADDR_SUB_FRAME1; + //framebuffer_sub.address_left2 = unknown; + framebuffer_sub.address_right1 = PADDR_SUB_FRAME2; + //framebuffer_sub.address_right2 = unknown; break; } @@ -46,14 +46,14 @@ void SetFramebufferLocation(const FramebufferLocation mode) { auto& framebuffer_top = g_regs.Get(); auto& framebuffer_sub = g_regs.Get(); - framebuffer_top.data.address_left1 = PADDR_VRAM_TOP_LEFT_FRAME1; - framebuffer_top.data.address_left2 = PADDR_VRAM_TOP_LEFT_FRAME2; - framebuffer_top.data.address_right1 = PADDR_VRAM_TOP_RIGHT_FRAME1; - framebuffer_top.data.address_right2 = PADDR_VRAM_TOP_RIGHT_FRAME2; - framebuffer_sub.data.address_left1 = PADDR_VRAM_SUB_FRAME1; - //framebuffer_sub.data.address_left2 = unknown; - framebuffer_sub.data.address_right1 = PADDR_VRAM_SUB_FRAME2; - //framebuffer_sub.data.address_right2 = unknown; + framebuffer_top.address_left1 = PADDR_VRAM_TOP_LEFT_FRAME1; + framebuffer_top.address_left2 = PADDR_VRAM_TOP_LEFT_FRAME2; + framebuffer_top.address_right1 = PADDR_VRAM_TOP_RIGHT_FRAME1; + framebuffer_top.address_right2 = PADDR_VRAM_TOP_RIGHT_FRAME2; + framebuffer_sub.address_left1 = PADDR_VRAM_SUB_FRAME1; + //framebuffer_sub.address_left2 = unknown; + framebuffer_sub.address_right1 = PADDR_VRAM_SUB_FRAME2; + //framebuffer_sub.address_right2 = unknown; break; } } @@ -135,14 +135,14 @@ inline void Write(u32 addr, const T data) { const auto& config = g_regs.Get(static_cast(index - 3)); // TODO: Not sure if this check should be done at GSP level instead - if (config.data.address_start) { + if (config.address_start) { // TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all - u32* start = (u32*)Memory::GetPointer(config.data.GetStartAddress()); - u32* end = (u32*)Memory::GetPointer(config.data.GetEndAddress()); + u32* start = (u32*)Memory::GetPointer(config.GetStartAddress()); + u32* end = (u32*)Memory::GetPointer(config.GetEndAddress()); for (u32* ptr = start; ptr < end; ++ptr) - *ptr = bswap32(config.data.value); // TODO: This is just a workaround to missing framebuffer format emulation + *ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation - DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.data.GetStartAddress(), config.data.GetEndAddress()); + DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress()); } break; } @@ -150,20 +150,20 @@ inline void Write(u32 addr, const T data) { case Regs::DisplayTransfer + 6: { const auto& config = g_regs.Get(); - if (config.data.trigger & 1) { - u8* source_pointer = Memory::GetPointer(config.data.GetPhysicalInputAddress()); - u8* dest_pointer = Memory::GetPointer(config.data.GetPhysicalOutputAddress()); + if (config.trigger & 1) { + u8* source_pointer = Memory::GetPointer(config.GetPhysicalInputAddress()); + u8* dest_pointer = Memory::GetPointer(config.GetPhysicalOutputAddress()); - for (int y = 0; y < config.data.output_height; ++y) { + for (int y = 0; y < config.output_height; ++y) { // TODO: Why does the register seem to hold twice the framebuffer width? - for (int x = 0; x < config.data.output_width / 2; ++x) { + for (int x = 0; x < config.output_width / 2; ++x) { int source[4] = { 0, 0, 0, 0}; // rgba; - switch (config.data.input_format) { + switch (config.input_format) { case Regs::FramebufferFormat::RGBA8: { // TODO: Most likely got the component order messed up. - u8* srcptr = source_pointer + x * 4 + y * config.data.input_width * 4 / 2; + u8* srcptr = source_pointer + x * 4 + y * config.input_width * 4 / 2; source[0] = srcptr[0]; // blue source[1] = srcptr[1]; // green source[2] = srcptr[2]; // red @@ -172,15 +172,15 @@ inline void Write(u32 addr, const T data) { } default: - ERROR_LOG(GPU, "Unknown source framebuffer format %x", config.data.input_format.Value()); + ERROR_LOG(GPU, "Unknown source framebuffer format %x", config.input_format.Value()); break; } - switch (config.data.output_format) { + switch (config.output_format) { /*case Regs::FramebufferFormat::RGBA8: { // TODO: Untested - u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.data.output_width * 4); + u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4); dstptr[0] = source[0]; dstptr[1] = source[1]; dstptr[2] = source[2]; @@ -190,7 +190,7 @@ inline void Write(u32 addr, const T data) { case Regs::FramebufferFormat::RGB8: { - u8* dstptr = dest_pointer + x * 3 + y * config.data.output_width * 3 / 2; + u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3 / 2; dstptr[0] = source[0]; // blue dstptr[1] = source[1]; // green dstptr[2] = source[2]; // red @@ -198,17 +198,17 @@ inline void Write(u32 addr, const T data) { } default: - ERROR_LOG(GPU, "Unknown destination framebuffer format %x", config.data.output_format.Value()); + ERROR_LOG(GPU, "Unknown destination framebuffer format %x", config.output_format.Value()); break; } } } DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", - config.data.output_height * config.data.output_width * 4, - config.data.GetPhysicalInputAddress(), (int)config.data.input_width, (int)config.data.input_height, - config.data.GetPhysicalOutputAddress(), (int)config.data.output_width, (int)config.data.output_height, - config.data.output_format.Value()); + config.output_height * config.output_width * 4, + config.GetPhysicalInputAddress(), (int)config.input_width, (int)config.input_height, + config.GetPhysicalOutputAddress(), (int)config.output_width, (int)config.output_height, + config.output_format.Value()); } break; } @@ -216,10 +216,10 @@ inline void Write(u32 addr, const T data) { case Regs::CommandProcessor + 4: { const auto& config = g_regs.Get(); - if (config.data.trigger & 1) + if (config.trigger & 1) { - // u32* buffer = (u32*)Memory::GetPointer(config.data.address << 3); - ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", config.data.size, config.data.address << 3); + // u32* buffer = (u32*)Memory::GetPointer(config.address << 3); + ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", config.size, config.address << 3); // TODO: Process command list! } break; @@ -263,17 +263,17 @@ void Init() { auto& framebuffer_top = g_regs.Get(); auto& framebuffer_sub = g_regs.Get(); // TODO: Width should be 240 instead? - framebuffer_top.data.width = 480; - framebuffer_top.data.height = 400; - framebuffer_top.data.stride = 480*3; - framebuffer_top.data.color_format = Regs::FramebufferFormat::RGB8; - framebuffer_top.data.active_fb = 0; - - framebuffer_sub.data.width = 480; - framebuffer_sub.data.height = 400; - framebuffer_sub.data.stride = 480*3; - framebuffer_sub.data.color_format = Regs::FramebufferFormat::RGB8; - framebuffer_sub.data.active_fb = 0; + framebuffer_top.width = 480; + framebuffer_top.height = 400; + framebuffer_top.stride = 480*3; + framebuffer_top.color_format = Regs::FramebufferFormat::RGB8; + framebuffer_top.active_fb = 0; + + framebuffer_sub.width = 480; + framebuffer_sub.height = 400; + framebuffer_sub.stride = 480*3; + framebuffer_sub.color_format = Regs::FramebufferFormat::RGB8; + framebuffer_sub.active_fb = 0; NOTICE_LOG(GPU, "initialized OK"); } diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index ce524bd02..4ef0a047f 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -29,7 +29,7 @@ struct Regs { }; template - union Struct; + struct Struct; enum class FramebufferFormat : u32 { RGBA8 = 0, @@ -38,128 +38,118 @@ struct Regs { RGB5A1 = 3, RGBA4 = 4, }; - }; template<> -union Regs::Struct { - struct { - u32 address_start; - u32 address_end; // ? - u32 size; - u32 value; // ? - - inline u32 GetStartAddress() const { - return address_start * 8; - } - - inline u32 GetEndAddress() const { - return address_end * 8; - } - } data; +struct Regs::Struct { + u32 address_start; + u32 address_end; // ? + u32 size; + u32 value; // ? + + inline u32 GetStartAddress() const { + return address_start * 8; + } + + inline u32 GetEndAddress() const { + return address_end * 8; + } }; static_assert(sizeof(Regs::Struct) == 0x10, "Structure size and register block length don't match"); template<> -union Regs::Struct { +struct Regs::Struct { using Format = Regs::FramebufferFormat; - struct { - union { - u32 size; + union { + u32 size; - BitField< 0, 16, u32> width; - BitField<16, 16, u32> height; - }; + BitField< 0, 16, u32> width; + BitField<16, 16, u32> height; + }; - u32 pad0[2]; + u32 pad0[2]; - u32 address_left1; - u32 address_left2; + u32 address_left1; + u32 address_left2; - union { - u32 format; + union { + u32 format; - BitField< 0, 3, Format> color_format; - }; + BitField< 0, 3, Format> color_format; + }; - u32 pad1; + u32 pad1; - union { - u32 active_fb; + union { + u32 active_fb; - BitField<0, 1, u32> second_fb_active; - }; + BitField<0, 1, u32> second_fb_active; + }; - u32 pad2[5]; + u32 pad2[5]; - u32 stride; + u32 stride; - u32 address_right1; - u32 address_right2; - } data; + u32 address_right1; + u32 address_right2; }; + template<> -union Regs::Struct { - using Type = decltype(Regs::Struct::data); - Type data; +struct Regs::Struct : public Regs::Struct { }; static_assert(sizeof(Regs::Struct) == 0x40, "Structure size and register block length don't match"); template<> -union Regs::Struct { +struct Regs::Struct { using Format = Regs::FramebufferFormat; - struct { - u32 input_address; - u32 output_address; + u32 input_address; + u32 output_address; - inline u32 GetPhysicalInputAddress() const { - return input_address * 8; - } + inline u32 GetPhysicalInputAddress() const { + return input_address * 8; + } - inline u32 GetPhysicalOutputAddress() const { - return output_address * 8; - } + inline u32 GetPhysicalOutputAddress() const { + return output_address * 8; + } - union { - u32 output_size; + union { + u32 output_size; - BitField< 0, 16, u32> output_width; - BitField<16, 16, u32> output_height; - }; + BitField< 0, 16, u32> output_width; + BitField<16, 16, u32> output_height; + }; - union { - u32 input_size; + union { + u32 input_size; - BitField< 0, 16, u32> input_width; - BitField<16, 16, u32> input_height; - }; + BitField< 0, 16, u32> input_width; + BitField<16, 16, u32> input_height; + }; - union { - u32 flags; + union { + u32 flags; - BitField< 0, 1, u32> flip_data; - BitField< 8, 3, Format> input_format; - BitField<12, 3, Format> output_format; - BitField<16, 1, u32> output_tiled; - }; + BitField< 0, 1, u32> flip_data; + BitField< 8, 3, Format> input_format; + BitField<12, 3, Format> output_format; + BitField<16, 1, u32> output_tiled; + }; - u32 unknown; - u32 trigger; - } data; + u32 unknown; + u32 trigger; }; static_assert(sizeof(Regs::Struct) == 0x1C, "Structure size and register block length don't match"); template<> -union Regs::Struct { - struct { - u32 size; - u32 pad0; - u32 address; - u32 pad1; - u32 trigger; - } data; +struct Regs::Struct { + u32 size; + u32 pad0; + u32 address; + u32 pad1; + u32 trigger; }; static_assert(sizeof(Regs::Struct) == 0x14, "Structure size and register block length don't match"); -- cgit v1.2.3 From 61e2ffd4483bf2da0862e32449caa9f1cecc5b72 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Tue, 22 Jul 2014 13:21:57 +0200 Subject: GPU: Add documentation. --- src/core/hw/gpu.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 4ef0a047f..3078e4142 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -84,11 +84,14 @@ struct Regs::Struct { union { u32 active_fb; + // 0: Use parameters ending with "1" + // 1: Use parameters ending with "2" BitField<0, 1, u32> second_fb_active; }; u32 pad2[5]; + // Distance between two pixel rows, in bytes u32 stride; u32 address_right1; @@ -132,23 +135,32 @@ struct Regs::Struct { union { u32 flags; - BitField< 0, 1, u32> flip_data; + BitField< 0, 1, u32> flip_data; // flips input data horizontally (TODO) if true BitField< 8, 3, Format> input_format; BitField<12, 3, Format> output_format; - BitField<16, 1, u32> output_tiled; + BitField<16, 1, u32> output_tiled; // stores output in a tiled format }; u32 unknown; + + // it seems that writing to this field triggers the display transfer u32 trigger; }; static_assert(sizeof(Regs::Struct) == 0x1C, "Structure size and register block length don't match"); template<> struct Regs::Struct { + // command list size u32 size; + u32 pad0; + + // command list address u32 address; + u32 pad1; + + // it seems that writing to this field triggers command list processing u32 trigger; }; static_assert(sizeof(Regs::Struct) == 0x14, "Structure size and register block length don't match"); -- cgit v1.2.3 From 2eb61dafc0c957ad1591150ff1f8cd002b8851bb Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Tue, 22 Jul 2014 13:29:25 +0200 Subject: GPU: Clarify display transfer code. Also makes the illogical component order more obvious. --- src/core/hw/gpu.cpp | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index edffa25c5..d18ff7625 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -157,17 +157,19 @@ inline void Write(u32 addr, const T data) { for (int y = 0; y < config.output_height; ++y) { // TODO: Why does the register seem to hold twice the framebuffer width? for (int x = 0; x < config.output_width / 2; ++x) { - int source[4] = { 0, 0, 0, 0}; // rgba; + struct { + int r, g, b, a; + } source_color = { 0, 0, 0, 0 }; switch (config.input_format) { case Regs::FramebufferFormat::RGBA8: { // TODO: Most likely got the component order messed up. u8* srcptr = source_pointer + x * 4 + y * config.input_width * 4 / 2; - source[0] = srcptr[0]; // blue - source[1] = srcptr[1]; // green - source[2] = srcptr[2]; // red - source[3] = srcptr[3]; // alpha + source_color.r = srcptr[0]; // blue + source_color.g = srcptr[1]; // green + source_color.b = srcptr[2]; // red + source_color.a = srcptr[3]; // alpha break; } @@ -181,19 +183,20 @@ inline void Write(u32 addr, const T data) { { // TODO: Untested u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4); - dstptr[0] = source[0]; - dstptr[1] = source[1]; - dstptr[2] = source[2]; - dstptr[3] = source[3]; + dstptr[0] = source_color.r; + dstptr[1] = source_color.g; + dstptr[2] = source_color.b; + dstptr[3] = source_color.a; break; }*/ case Regs::FramebufferFormat::RGB8: { + // TODO: Most likely got the component order messed up. u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3 / 2; - dstptr[0] = source[0]; // blue - dstptr[1] = source[1]; // green - dstptr[2] = source[2]; // red + dstptr[0] = source_color.r; // blue + dstptr[1] = source_color.g; // green + dstptr[2] = source_color.b; // red break; } -- cgit v1.2.3 From afcb250b3140fa2f37efa800f5346aabbde5db2a Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Tue, 22 Jul 2014 13:49:25 +0200 Subject: Fix a few warnings. Templates shouldn't be marked as inline if they aren't defined in the header. --- src/core/hw/gpu.h | 4 ++-- src/core/hw/hw.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 3078e4142..42f18a0e7 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h @@ -235,10 +235,10 @@ u32 GetFramebufferAddr(const u32 address); FramebufferLocation GetFramebufferLocation(u32 address); template -inline void Read(T &var, const u32 addr); +void Read(T &var, const u32 addr); template -inline void Write(u32 addr, const T data); +void Write(u32 addr, const T data); /// Update hardware void Update(); diff --git a/src/core/hw/hw.h b/src/core/hw/hw.h index 92e9304ca..1055ed94f 100644 --- a/src/core/hw/hw.h +++ b/src/core/hw/hw.h @@ -9,10 +9,10 @@ namespace HW { template -inline void Read(T &var, const u32 addr); +void Read(T &var, const u32 addr); template -inline void Write(u32 addr, const T data); +void Write(u32 addr, const T data); /// Update hardware void Update(); -- cgit v1.2.3 From 9fd2537e933b5d36c898d662e29ea57f7ce61e49 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Tue, 22 Jul 2014 23:07:32 +0200 Subject: Use uniform formatting when printing hexadecimal numbers. --- src/core/hw/gpu.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/core/hw') diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp index d18ff7625..c00be2a83 100644 --- a/src/core/hw/gpu.cpp +++ b/src/core/hw/gpu.cpp @@ -142,7 +142,7 @@ inline void Write(u32 addr, const T data) { for (u32* ptr = start; ptr < end; ++ptr) *ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation - DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress()); + DEBUG_LOG(GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(), config.GetEndAddress()); } break; } @@ -207,7 +207,7 @@ inline void Write(u32 addr, const T data) { } } - DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x", + DEBUG_LOG(GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%dx%d)-> 0x%08x(%dx%d), dst format %x", config.output_height * config.output_width * 4, config.GetPhysicalInputAddress(), (int)config.input_width, (int)config.input_height, config.GetPhysicalOutputAddress(), (int)config.output_width, (int)config.output_height, @@ -222,7 +222,7 @@ inline void Write(u32 addr, const T data) { if (config.trigger & 1) { // u32* buffer = (u32*)Memory::GetPointer(config.address << 3); - ERROR_LOG(GPU, "Beginning %x bytes of commands from address %x", config.size, config.address << 3); + ERROR_LOG(GPU, "Beginning 0x%08x bytes of commands from address 0x%08x", config.size, config.address << 3); // TODO: Process command list! } break; -- cgit v1.2.3