Update SDK For E31/E51 Coreplex IP Evaluation2017-05-04T12:46:05+00:00Megan Wachsmegan@sifive.com2017-05-04T12:46:05+00:004d5cbec9118cbedf2d4ae5b54acaa22862245a4c
prci: Clean up the hfrosc-driven-pll FPU testing.2017-02-02T19:33:50+00:00Megan Wachsmegan@sifive.com2017-02-02T19:33:50+00:00557c3ed0dc025b73a919f3e2a4068808092f48c1
prci: Simplify the targeted f_cpu function by measuring HFROSC frequency first, then using it as the PLL source. This is also safer as it is less risk of using PLL out of its range.2017-02-02T17:56:52+00:00Megan Wachsmegan@sifive.com2017-02-02T17:56:52+00:002579554bb17038dffa9af57649c1e83e614efbc6
PRCI: This doesn't exist on the Arty and potentially other devices, so exclude it if there is not PRCI_BASE_ADDR on the system.2017-02-02T02:36:22+00:00Megan Wachsmegan@sifive.com2017-02-02T02:36:22+00:004c4c4cd044978d9f72a872b1b8f674cd6f061c1b
PRCI: add control for the target CPU frequency (to allow a minimum, maximum, or closest match)2017-02-02T02:03:37+00:00Megan Wachsmegan@sifive.com2017-02-02T02:03:37+00:00b003c52b0f5460c6e0e15cb29171164530490e08
Additional PRCI driver support. Make the code usable by C++ programs as well.2017-02-02T00:39:38+00:00Megan Wachsmegan@sifive.com2017-02-02T00:39:38+00:0008a72bb956a25fd94d965fb4474f3ddcca1ed1e6
add a 'driver' common PRCI functions.2017-02-01T04:25:38+00:00Megan Wachsmegan@sifive.com2017-02-01T04:25:38+00:000adc37422f48e9468d980a1d98dcc65bd7ab3043