diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-04-30 16:59:29 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-30 16:59:29 +0000 |
| commit | 0c75c6a612a1620bf1ffe82cd5c77ef9a8369045 (patch) | |
| tree | 1a11e4304b06fbee9c0e525d81c0789530dfba35 | |
| parent | a351dc8d6aaf1a10be9a08e66c78c37126833d6a (diff) | |
| parent | 8cd756c200cb13c036115a4b851b94f686cf3a3a (diff) | |
Merge pull request #235 from sifive/u54-rtl
Add Multicore Support
113 files changed, 6248 insertions, 436 deletions
diff --git a/.gitmodules b/.gitmodules index 5c6f9e1..aba5d34 100644 --- a/.gitmodules +++ b/.gitmodules @@ -43,3 +43,6 @@ [submodule "software/dhrystone"] path = software/dhrystone url = https://github.com/sifive/benchmark-dhrystone +[submodule "software/multicore-hello"] + path = software/multicore-hello + url = https://github.com/sifive/example-multicore-hello.git @@ -31,6 +31,8 @@ operating systems to RISC-V. - sifive-hifive1 - SiFive HiFive 1 Rev B - sifive-hifive1-revb + - [SiFive HiFive Unleashed](https://www.sifive.com/boards/hifive-unleashed) + - sifive-hifive-unleashed - [SiFive Freedom E310 Arty](https://github.com/sifive/freedom) - freedom-e310-arty - SiFive CoreIP RTL @@ -43,6 +45,8 @@ operating systems to RISC-V. - coreip-s54-rtl - coreip-e76-rtl - coreip-s76-rtl + - coreip-u54-rtl + - coreip-u54mc-rtl - SiFive CoreIP Arty FPGA Evaluation targets - coreip-e20-arty - coreip-e21-arty diff --git a/bsp/coreip-e20-arty/metal.default.lds b/bsp/coreip-e20-arty/metal.default.lds index 46e2407..7b20841 100644 --- a/bsp/coreip-e20-arty/metal.default.lds +++ b/bsp/coreip-e20-arty/metal.default.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e20-arty/metal.h b/bsp/coreip-e20-arty/metal.h index 36ddab0..8528cc9 100644 --- a/bsp/coreip-e20-arty/metal.h +++ b/bsp/coreip-e20-arty/metal.h @@ -5,9 +5,15 @@ #ifdef __METAL_MACHINE_MACROS +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #define __METAL_CLIC_SUBINTERRUPTS 58 #ifndef __METAL_CLIC_SUBINTERRUPTS @@ -18,9 +24,13 @@ #define METAL_MAX_CLINT_INTERRUPTS 0 +#define __METAL_CLINT_NUM_PARENTS 0 + #define __METAL_PLIC_SUBINTERRUPTS 0 #define METAL_MAX_PLIC_INTERRUPTS 0 +#define __METAL_PLIC_NUM_PARENTS 0 + #define __METAL_INTERRUPT_CONTROLLER_2000000_INTERRUPTS 3 #define __METAL_CLIC_SUBINTERRUPTS 58 @@ -45,6 +55,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,cpu.h> #include <metal/pmp.h> #include <metal/drivers/sifive,clic0.h> @@ -62,13 +73,18 @@ asm (".weak __metal_dt_clock_0"); struct __metal_driver_fixed_clock __metal_dt_clock_0; +asm (".weak __metal_dt_mem_sys_sram_0_80000000"); +struct metal_memory __metal_dt_mem_sys_sram_0_80000000; + +asm (".weak __metal_dt_mem_spi_20004000"); +struct metal_memory __metal_dt_mem_spi_20004000; + /* From cpu@0 */ asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@2000000 */ asm (".weak __metal_dt_interrupt_controller_2000000"); @@ -150,16 +166,38 @@ struct __metal_driver_fixed_clock __metal_dt_clock_0 = { .rate = 32500000UL, }; +struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = { + ._base_address = 2147483648UL, + ._size = 65536UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_20004000 = { + ._base_address = 1073741824UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From cpu@0 */ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 32000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -174,7 +212,7 @@ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .control_size = 16777216UL, .init_done = 0, .num_interrupts = METAL_MAX_CLIC_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, .interrupt_lines[1] = 7, .interrupt_lines[2] = 11, @@ -431,6 +469,13 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { }; +#define __METAL_DT_MAX_MEMORIES 2 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_sys_sram_0_80000000, + &__metal_dt_mem_spi_20004000}; + /* From serial@20000000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) @@ -438,22 +483,12 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { #define __METAL_DT_STDOUT_UART_BAUD 115200 -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e20-arty/metal.ramrodata.lds b/bsp/coreip-e20-arty/metal.ramrodata.lds index bb8171e..5fc1e00 100644 --- a/bsp/coreip-e20-arty/metal.ramrodata.lds +++ b/bsp/coreip-e20-arty/metal.ramrodata.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e20-arty/metal.scratchpad.lds b/bsp/coreip-e20-arty/metal.scratchpad.lds index 9b63e9b..4aa5569 100644 --- a/bsp/coreip-e20-arty/metal.scratchpad.lds +++ b/bsp/coreip-e20-arty/metal.scratchpad.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e20-rtl/metal.default.lds b/bsp/coreip-e20-rtl/metal.default.lds index 4900be7..73490a3 100644 --- a/bsp/coreip-e20-rtl/metal.default.lds +++ b/bsp/coreip-e20-rtl/metal.default.lds @@ -19,6 +19,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e20-rtl/metal.h b/bsp/coreip-e20-rtl/metal.h index 66d4599..094cb45 100644 --- a/bsp/coreip-e20-rtl/metal.h +++ b/bsp/coreip-e20-rtl/metal.h @@ -5,9 +5,15 @@ #ifdef __METAL_MACHINE_MACROS +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #define __METAL_CLIC_SUBINTERRUPTS 48 #ifndef __METAL_CLIC_SUBINTERRUPTS @@ -18,9 +24,13 @@ #define METAL_MAX_CLINT_INTERRUPTS 0 +#define __METAL_CLINT_NUM_PARENTS 0 + #define __METAL_PLIC_SUBINTERRUPTS 0 #define METAL_MAX_PLIC_INTERRUPTS 0 +#define __METAL_PLIC_NUM_PARENTS 0 + #define __METAL_INTERRUPT_CONTROLLER_2000000_INTERRUPTS 3 #define __METAL_CLIC_SUBINTERRUPTS 48 @@ -39,19 +49,22 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,cpu.h> #include <metal/pmp.h> #include <metal/drivers/sifive,clic0.h> #include <metal/drivers/sifive,local-external-interrupts0.h> #include <metal/drivers/sifive,test0.h> +asm (".weak __metal_dt_mem_testram_20000000"); +struct metal_memory __metal_dt_mem_testram_20000000; + /* From cpu@0 */ asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@2000000 */ asm (".weak __metal_dt_interrupt_controller_2000000"); @@ -66,16 +79,27 @@ asm (".weak __metal_dt_teststatus_4000"); struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; +struct metal_memory __metal_dt_mem_testram_20000000 = { + ._base_address = 536870912UL, + ._size = 134217728UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From cpu@0 */ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -90,7 +114,7 @@ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .control_size = 16777216UL, .init_done = 0, .num_interrupts = METAL_MAX_CLIC_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, .interrupt_lines[1] = 7, .interrupt_lines[2] = 11, @@ -151,10 +175,11 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { }; -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) +#define __METAL_DT_MAX_MEMORIES 1 -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_testram_20000000}; #define __METAL_DT_MAX_HARTS 1 @@ -162,11 +187,6 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e20-rtl/metal.ramrodata.lds b/bsp/coreip-e20-rtl/metal.ramrodata.lds index 050f35f..4feb009 100644 --- a/bsp/coreip-e20-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e20-rtl/metal.ramrodata.lds @@ -19,6 +19,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e20-rtl/metal.scratchpad.lds b/bsp/coreip-e20-rtl/metal.scratchpad.lds index 4900be7..73490a3 100644 --- a/bsp/coreip-e20-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e20-rtl/metal.scratchpad.lds @@ -19,6 +19,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e21-arty/metal.default.lds b/bsp/coreip-e21-arty/metal.default.lds index dde63b9..3358fbe 100644 --- a/bsp/coreip-e21-arty/metal.default.lds +++ b/bsp/coreip-e21-arty/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e21-arty/metal.h b/bsp/coreip-e21-arty/metal.h index 0223894..56e972a 100644 --- a/bsp/coreip-e21-arty/metal.h +++ b/bsp/coreip-e21-arty/metal.h @@ -5,9 +5,15 @@ #ifdef __METAL_MACHINE_MACROS +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #define __METAL_CLIC_SUBINTERRUPTS 153 #ifndef __METAL_CLIC_SUBINTERRUPTS @@ -18,9 +24,13 @@ #define METAL_MAX_CLINT_INTERRUPTS 0 +#define __METAL_CLINT_NUM_PARENTS 0 + #define __METAL_PLIC_SUBINTERRUPTS 0 #define METAL_MAX_PLIC_INTERRUPTS 0 +#define __METAL_PLIC_NUM_PARENTS 0 + #define __METAL_INTERRUPT_CONTROLLER_2000000_INTERRUPTS 3 #define __METAL_CLIC_SUBINTERRUPTS 153 @@ -45,6 +55,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,cpu.h> #include <metal/pmp.h> #include <metal/drivers/sifive,clic0.h> @@ -62,13 +73,21 @@ asm (".weak __metal_dt_clock_0"); struct __metal_driver_fixed_clock __metal_dt_clock_0; +asm (".weak __metal_dt_mem_sys_sram_0_80000000"); +struct metal_memory __metal_dt_mem_sys_sram_0_80000000; + +asm (".weak __metal_dt_mem_sys_sram_1_80008000"); +struct metal_memory __metal_dt_mem_sys_sram_1_80008000; + +asm (".weak __metal_dt_mem_spi_20004000"); +struct metal_memory __metal_dt_mem_spi_20004000; + /* From cpu@0 */ asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; asm (".weak __metal_dt_pmp_0"); struct metal_pmp __metal_dt_pmp_0; @@ -153,16 +172,49 @@ struct __metal_driver_fixed_clock __metal_dt_clock_0 = { .rate = 32500000UL, }; +struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = { + ._base_address = 2147483648UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = { + ._base_address = 2147516416UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_20004000 = { + ._base_address = 1073741824UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From cpu@0 */ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 32000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -182,7 +234,7 @@ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .control_size = 16777216UL, .init_done = 0, .num_interrupts = METAL_MAX_CLIC_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, .interrupt_lines[1] = 7, .interrupt_lines[2] = 11, @@ -534,6 +586,14 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { }; +#define __METAL_DT_MAX_MEMORIES 3 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_sys_sram_0_80000000, + &__metal_dt_mem_sys_sram_1_80008000, + &__metal_dt_mem_spi_20004000}; + /* From serial@20000000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) @@ -541,22 +601,12 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { #define __METAL_DT_STDOUT_UART_BAUD 115200 -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From pmp@0 */ #define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) diff --git a/bsp/coreip-e21-arty/metal.ramrodata.lds b/bsp/coreip-e21-arty/metal.ramrodata.lds index b653bbb..90b3388 100644 --- a/bsp/coreip-e21-arty/metal.ramrodata.lds +++ b/bsp/coreip-e21-arty/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -218,7 +219,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e21-arty/metal.scratchpad.lds b/bsp/coreip-e21-arty/metal.scratchpad.lds index 7541b7b..01ee127 100644 --- a/bsp/coreip-e21-arty/metal.scratchpad.lds +++ b/bsp/coreip-e21-arty/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e21-rtl/metal.default.lds b/bsp/coreip-e21-rtl/metal.default.lds index a17a5f1..a3c999a 100644 --- a/bsp/coreip-e21-rtl/metal.default.lds +++ b/bsp/coreip-e21-rtl/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e21-rtl/metal.h b/bsp/coreip-e21-rtl/metal.h index 349fdc6..7f017fd 100644 --- a/bsp/coreip-e21-rtl/metal.h +++ b/bsp/coreip-e21-rtl/metal.h @@ -5,9 +5,15 @@ #ifdef __METAL_MACHINE_MACROS +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #define __METAL_CLIC_SUBINTERRUPTS 143 #ifndef __METAL_CLIC_SUBINTERRUPTS @@ -18,9 +24,13 @@ #define METAL_MAX_CLINT_INTERRUPTS 0 +#define __METAL_CLINT_NUM_PARENTS 0 + #define __METAL_PLIC_SUBINTERRUPTS 0 #define METAL_MAX_PLIC_INTERRUPTS 0 +#define __METAL_PLIC_NUM_PARENTS 0 + #define __METAL_INTERRUPT_CONTROLLER_2000000_INTERRUPTS 3 #define __METAL_CLIC_SUBINTERRUPTS 143 @@ -39,19 +49,28 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,cpu.h> #include <metal/pmp.h> #include <metal/drivers/sifive,clic0.h> #include <metal/drivers/sifive,local-external-interrupts0.h> #include <metal/drivers/sifive,test0.h> +asm (".weak __metal_dt_mem_sys_sram_0_80000000"); +struct metal_memory __metal_dt_mem_sys_sram_0_80000000; + +asm (".weak __metal_dt_mem_sys_sram_1_80008000"); +struct metal_memory __metal_dt_mem_sys_sram_1_80008000; + +asm (".weak __metal_dt_mem_testram_20000000"); +struct metal_memory __metal_dt_mem_testram_20000000; + /* From cpu@0 */ asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; asm (".weak __metal_dt_pmp_0"); struct metal_pmp __metal_dt_pmp_0; @@ -69,16 +88,49 @@ asm (".weak __metal_dt_teststatus_4000"); struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; +struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = { + ._base_address = 2147483648UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = { + ._base_address = 2147516416UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_testram_20000000 = { + ._base_address = 536870912UL, + ._size = 134217728UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From cpu@0 */ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -98,7 +150,7 @@ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .control_size = 16777216UL, .init_done = 0, .num_interrupts = METAL_MAX_CLIC_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, .interrupt_lines[1] = 7, .interrupt_lines[2] = 11, @@ -254,10 +306,13 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { }; -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) +#define __METAL_DT_MAX_MEMORIES 3 -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_sys_sram_0_80000000, + &__metal_dt_mem_sys_sram_1_80008000, + &__metal_dt_mem_testram_20000000}; #define __METAL_DT_MAX_HARTS 1 @@ -265,11 +320,6 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From pmp@0 */ #define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) diff --git a/bsp/coreip-e21-rtl/metal.ramrodata.lds b/bsp/coreip-e21-rtl/metal.ramrodata.lds index cb1ac45..b8f126d 100644 --- a/bsp/coreip-e21-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e21-rtl/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -218,7 +219,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e21-rtl/metal.scratchpad.lds b/bsp/coreip-e21-rtl/metal.scratchpad.lds index cb5d41c..44ced9a 100644 --- a/bsp/coreip-e21-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e21-rtl/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e24-arty/metal.default.lds b/bsp/coreip-e24-arty/metal.default.lds index dde63b9..3358fbe 100644 --- a/bsp/coreip-e24-arty/metal.default.lds +++ b/bsp/coreip-e24-arty/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e24-arty/metal.h b/bsp/coreip-e24-arty/metal.h index f04b38b..13a5392 100644 --- a/bsp/coreip-e24-arty/metal.h +++ b/bsp/coreip-e24-arty/metal.h @@ -5,9 +5,15 @@ #ifdef __METAL_MACHINE_MACROS +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #define __METAL_CLIC_SUBINTERRUPTS 153 #ifndef __METAL_CLIC_SUBINTERRUPTS @@ -18,9 +24,13 @@ #define METAL_MAX_CLINT_INTERRUPTS 0 +#define __METAL_CLINT_NUM_PARENTS 0 + #define __METAL_PLIC_SUBINTERRUPTS 0 #define METAL_MAX_PLIC_INTERRUPTS 0 +#define __METAL_PLIC_NUM_PARENTS 0 + #define __METAL_INTERRUPT_CONTROLLER_2000000_INTERRUPTS 3 #define __METAL_CLIC_SUBINTERRUPTS 153 @@ -45,6 +55,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,cpu.h> #include <metal/pmp.h> #include <metal/drivers/sifive,clic0.h> @@ -62,13 +73,21 @@ asm (".weak __metal_dt_clock_0"); struct __metal_driver_fixed_clock __metal_dt_clock_0; +asm (".weak __metal_dt_mem_sys_sram_0_80000000"); +struct metal_memory __metal_dt_mem_sys_sram_0_80000000; + +asm (".weak __metal_dt_mem_sys_sram_1_80008000"); +struct metal_memory __metal_dt_mem_sys_sram_1_80008000; + +asm (".weak __metal_dt_mem_spi_20004000"); +struct metal_memory __metal_dt_mem_spi_20004000; + /* From cpu@0 */ asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; asm (".weak __metal_dt_pmp_0"); struct metal_pmp __metal_dt_pmp_0; @@ -153,16 +172,49 @@ struct __metal_driver_fixed_clock __metal_dt_clock_0 = { .rate = 32500000UL, }; +struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = { + ._base_address = 2147483648UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = { + ._base_address = 2147516416UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_20004000 = { + ._base_address = 1073741824UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From cpu@0 */ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 32000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -182,7 +234,7 @@ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .control_size = 16777216UL, .init_done = 0, .num_interrupts = METAL_MAX_CLIC_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, .interrupt_lines[1] = 7, .interrupt_lines[2] = 11, @@ -534,6 +586,14 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { }; +#define __METAL_DT_MAX_MEMORIES 3 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_sys_sram_0_80000000, + &__metal_dt_mem_sys_sram_1_80008000, + &__metal_dt_mem_spi_20004000}; + /* From serial@20000000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) @@ -541,22 +601,12 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { #define __METAL_DT_STDOUT_UART_BAUD 115200 -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From pmp@0 */ #define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) diff --git a/bsp/coreip-e24-arty/metal.ramrodata.lds b/bsp/coreip-e24-arty/metal.ramrodata.lds index b653bbb..90b3388 100644 --- a/bsp/coreip-e24-arty/metal.ramrodata.lds +++ b/bsp/coreip-e24-arty/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -218,7 +219,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e24-arty/metal.scratchpad.lds b/bsp/coreip-e24-arty/metal.scratchpad.lds index 7541b7b..01ee127 100644 --- a/bsp/coreip-e24-arty/metal.scratchpad.lds +++ b/bsp/coreip-e24-arty/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e24-rtl/metal.default.lds b/bsp/coreip-e24-rtl/metal.default.lds index a17a5f1..a3c999a 100644 --- a/bsp/coreip-e24-rtl/metal.default.lds +++ b/bsp/coreip-e24-rtl/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e24-rtl/metal.h b/bsp/coreip-e24-rtl/metal.h index 8557b14..bada746 100644 --- a/bsp/coreip-e24-rtl/metal.h +++ b/bsp/coreip-e24-rtl/metal.h @@ -5,9 +5,15 @@ #ifdef __METAL_MACHINE_MACROS +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #define __METAL_CLIC_SUBINTERRUPTS 143 #ifndef __METAL_CLIC_SUBINTERRUPTS @@ -18,9 +24,13 @@ #define METAL_MAX_CLINT_INTERRUPTS 0 +#define __METAL_CLINT_NUM_PARENTS 0 + #define __METAL_PLIC_SUBINTERRUPTS 0 #define METAL_MAX_PLIC_INTERRUPTS 0 +#define __METAL_PLIC_NUM_PARENTS 0 + #define __METAL_INTERRUPT_CONTROLLER_2000000_INTERRUPTS 3 #define __METAL_CLIC_SUBINTERRUPTS 143 @@ -39,19 +49,28 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,cpu.h> #include <metal/pmp.h> #include <metal/drivers/sifive,clic0.h> #include <metal/drivers/sifive,local-external-interrupts0.h> #include <metal/drivers/sifive,test0.h> +asm (".weak __metal_dt_mem_sys_sram_0_80000000"); +struct metal_memory __metal_dt_mem_sys_sram_0_80000000; + +asm (".weak __metal_dt_mem_sys_sram_1_80008000"); +struct metal_memory __metal_dt_mem_sys_sram_1_80008000; + +asm (".weak __metal_dt_mem_testram_20000000"); +struct metal_memory __metal_dt_mem_testram_20000000; + /* From cpu@0 */ asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; asm (".weak __metal_dt_pmp_0"); struct metal_pmp __metal_dt_pmp_0; @@ -69,16 +88,49 @@ asm (".weak __metal_dt_teststatus_4000"); struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; +struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = { + ._base_address = 2147483648UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = { + ._base_address = 2147516416UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_testram_20000000 = { + ._base_address = 536870912UL, + ._size = 134217728UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From cpu@0 */ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -98,7 +150,7 @@ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .control_size = 16777216UL, .init_done = 0, .num_interrupts = METAL_MAX_CLIC_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, .interrupt_lines[1] = 7, .interrupt_lines[2] = 11, @@ -254,10 +306,13 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { }; -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) +#define __METAL_DT_MAX_MEMORIES 3 -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_sys_sram_0_80000000, + &__metal_dt_mem_sys_sram_1_80008000, + &__metal_dt_mem_testram_20000000}; #define __METAL_DT_MAX_HARTS 1 @@ -265,11 +320,6 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From pmp@0 */ #define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) diff --git a/bsp/coreip-e24-rtl/metal.ramrodata.lds b/bsp/coreip-e24-rtl/metal.ramrodata.lds index cb1ac45..b8f126d 100644 --- a/bsp/coreip-e24-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e24-rtl/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -218,7 +219,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e24-rtl/metal.scratchpad.lds b/bsp/coreip-e24-rtl/metal.scratchpad.lds index cb5d41c..44ced9a 100644 --- a/bsp/coreip-e24-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e24-rtl/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e31-arty/metal.default.lds b/bsp/coreip-e31-arty/metal.default.lds index 965607a..87bc213 100644 --- a/bsp/coreip-e31-arty/metal.default.lds +++ b/bsp/coreip-e31-arty/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e31-arty/metal.h b/bsp/coreip-e31-arty/metal.h index fead823..f029f9e 100644 --- a/bsp/coreip-e31-arty/metal.h +++ b/bsp/coreip-e31-arty/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 27 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 27 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -47,6 +61,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -65,6 +80,15 @@ asm (".weak __metal_dt_clock_0"); struct __metal_driver_fixed_clock __metal_dt_clock_0; +asm (".weak __metal_dt_mem_dtim_80000000"); +struct metal_memory __metal_dt_mem_dtim_80000000; + +asm (".weak __metal_dt_mem_itim_8000000"); +struct metal_memory __metal_dt_mem_itim_8000000; + +asm (".weak __metal_dt_mem_spi_20004000"); +struct metal_memory __metal_dt_mem_spi_20004000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -73,9 +97,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -160,6 +183,39 @@ struct __metal_driver_fixed_clock __metal_dt_clock_0 = { .rate = 32500000UL, }; +struct metal_memory __metal_dt_mem_dtim_80000000 = { + ._base_address = 2147483648UL, + ._size = 65536UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_8000000 = { + ._base_address = 134217728UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_20004000 = { + ._base_address = 1073741824UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -168,8 +224,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -178,11 +235,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 65000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -194,9 +251,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -214,8 +270,7 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, .interrupt_lines[0] = 16, .interrupt_lines[1] = 17, @@ -440,6 +495,14 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { }; +#define __METAL_DT_MAX_MEMORIES 3 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_dtim_80000000, + &__metal_dt_mem_itim_8000000, + &__metal_dt_mem_spi_20004000}; + /* From serial@20000000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) @@ -452,22 +515,12 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-e31-arty/metal.ramrodata.lds b/bsp/coreip-e31-arty/metal.ramrodata.lds index 8faa8d0..2056624 100644 --- a/bsp/coreip-e31-arty/metal.ramrodata.lds +++ b/bsp/coreip-e31-arty/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e31-arty/metal.scratchpad.lds b/bsp/coreip-e31-arty/metal.scratchpad.lds index 0edadd5..fe62b3a 100644 --- a/bsp/coreip-e31-arty/metal.scratchpad.lds +++ b/bsp/coreip-e31-arty/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e31-rtl/metal.default.lds b/bsp/coreip-e31-rtl/metal.default.lds index 3fd5c5f..4999528 100644 --- a/bsp/coreip-e31-rtl/metal.default.lds +++ b/bsp/coreip-e31-rtl/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e31-rtl/metal.h b/bsp/coreip-e31-rtl/metal.h index 39be849..b842fff 100644 --- a/bsp/coreip-e31-rtl/metal.h +++ b/bsp/coreip-e31-rtl/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 128 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 128 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -43,6 +57,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -51,6 +66,15 @@ #include <metal/drivers/sifive,global-external-interrupts0.h> #include <metal/drivers/sifive,test0.h> +asm (".weak __metal_dt_mem_testram_20000000"); +struct metal_memory __metal_dt_mem_testram_20000000; + +asm (".weak __metal_dt_mem_dtim_80000000"); +struct metal_memory __metal_dt_mem_dtim_80000000; + +asm (".weak __metal_dt_mem_itim_8000000"); +struct metal_memory __metal_dt_mem_itim_8000000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -59,9 +83,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -83,6 +106,39 @@ asm (".weak __metal_dt_teststatus_4000"); struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; +struct metal_memory __metal_dt_mem_testram_20000000 = { + ._base_address = 536870912UL, + ._size = 134217728UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_dtim_80000000 = { + ._base_address = 2147483648UL, + ._size = 65536UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_8000000 = { + ._base_address = 134217728UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -91,8 +147,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -101,11 +158,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -117,9 +174,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -137,8 +193,7 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, .interrupt_lines[0] = 16, .interrupt_lines[1] = 17, @@ -304,27 +359,25 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { }; +#define __METAL_DT_MAX_MEMORIES 3 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_testram_20000000, + &__metal_dt_mem_dtim_80000000, + &__metal_dt_mem_itim_8000000}; + /* From clint@2000000 */ #define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-e31-rtl/metal.ramrodata.lds b/bsp/coreip-e31-rtl/metal.ramrodata.lds index 1946306..c8b82a2 100644 --- a/bsp/coreip-e31-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e31-rtl/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e31-rtl/metal.scratchpad.lds b/bsp/coreip-e31-rtl/metal.scratchpad.lds index 3c1fe99..f7da1bc 100644 --- a/bsp/coreip-e31-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e31-rtl/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e34-arty/metal.default.lds b/bsp/coreip-e34-arty/metal.default.lds index 965607a..87bc213 100644 --- a/bsp/coreip-e34-arty/metal.default.lds +++ b/bsp/coreip-e34-arty/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e34-arty/metal.h b/bsp/coreip-e34-arty/metal.h index 172ea35..3c79ea5 100644 --- a/bsp/coreip-e34-arty/metal.h +++ b/bsp/coreip-e34-arty/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 27 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 27 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -47,6 +61,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -65,6 +80,15 @@ asm (".weak __metal_dt_clock_0"); struct __metal_driver_fixed_clock __metal_dt_clock_0; +asm (".weak __metal_dt_mem_dtim_80000000"); +struct metal_memory __metal_dt_mem_dtim_80000000; + +asm (".weak __metal_dt_mem_itim_8000000"); +struct metal_memory __metal_dt_mem_itim_8000000; + +asm (".weak __metal_dt_mem_spi_20004000"); +struct metal_memory __metal_dt_mem_spi_20004000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -73,9 +97,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -160,6 +183,39 @@ struct __metal_driver_fixed_clock __metal_dt_clock_0 = { .rate = 32500000UL, }; +struct metal_memory __metal_dt_mem_dtim_80000000 = { + ._base_address = 2147483648UL, + ._size = 65536UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_8000000 = { + ._base_address = 134217728UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_20004000 = { + ._base_address = 1073741824UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -168,8 +224,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -178,11 +235,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 65000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -194,9 +251,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -214,8 +270,7 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, .interrupt_lines[0] = 16, .interrupt_lines[1] = 17, @@ -440,6 +495,14 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { }; +#define __METAL_DT_MAX_MEMORIES 3 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_dtim_80000000, + &__metal_dt_mem_itim_8000000, + &__metal_dt_mem_spi_20004000}; + /* From serial@20000000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) @@ -452,22 +515,12 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-e34-arty/metal.ramrodata.lds b/bsp/coreip-e34-arty/metal.ramrodata.lds index 8faa8d0..2056624 100644 --- a/bsp/coreip-e34-arty/metal.ramrodata.lds +++ b/bsp/coreip-e34-arty/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e34-arty/metal.scratchpad.lds b/bsp/coreip-e34-arty/metal.scratchpad.lds index 0edadd5..fe62b3a 100644 --- a/bsp/coreip-e34-arty/metal.scratchpad.lds +++ b/bsp/coreip-e34-arty/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e34-rtl/metal.default.lds b/bsp/coreip-e34-rtl/metal.default.lds index 3fd5c5f..4999528 100644 --- a/bsp/coreip-e34-rtl/metal.default.lds +++ b/bsp/coreip-e34-rtl/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e34-rtl/metal.h b/bsp/coreip-e34-rtl/metal.h index 178d80a..89e7f85 100644 --- a/bsp/coreip-e34-rtl/metal.h +++ b/bsp/coreip-e34-rtl/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 128 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 128 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -43,6 +57,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -51,6 +66,15 @@ #include <metal/drivers/sifive,global-external-interrupts0.h> #include <metal/drivers/sifive,test0.h> +asm (".weak __metal_dt_mem_testram_20000000"); +struct metal_memory __metal_dt_mem_testram_20000000; + +asm (".weak __metal_dt_mem_dtim_80000000"); +struct metal_memory __metal_dt_mem_dtim_80000000; + +asm (".weak __metal_dt_mem_itim_8000000"); +struct metal_memory __metal_dt_mem_itim_8000000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -59,9 +83,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -83,6 +106,39 @@ asm (".weak __metal_dt_teststatus_4000"); struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; +struct metal_memory __metal_dt_mem_testram_20000000 = { + ._base_address = 536870912UL, + ._size = 134217728UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_dtim_80000000 = { + ._base_address = 2147483648UL, + ._size = 65536UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_8000000 = { + ._base_address = 134217728UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -91,8 +147,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -101,11 +158,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -117,9 +174,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -137,8 +193,7 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, .interrupt_lines[0] = 16, .interrupt_lines[1] = 17, @@ -304,27 +359,25 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { }; +#define __METAL_DT_MAX_MEMORIES 3 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_testram_20000000, + &__metal_dt_mem_dtim_80000000, + &__metal_dt_mem_itim_8000000}; + /* From clint@2000000 */ #define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-e34-rtl/metal.ramrodata.lds b/bsp/coreip-e34-rtl/metal.ramrodata.lds index 1946306..c8b82a2 100644 --- a/bsp/coreip-e34-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e34-rtl/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e34-rtl/metal.scratchpad.lds b/bsp/coreip-e34-rtl/metal.scratchpad.lds index 3c1fe99..f7da1bc 100644 --- a/bsp/coreip-e34-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e34-rtl/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e76-arty/metal.default.lds b/bsp/coreip-e76-arty/metal.default.lds index c4cae6b..ccd5fb0 100644 --- a/bsp/coreip-e76-arty/metal.default.lds +++ b/bsp/coreip-e76-arty/metal.default.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e76-arty/metal.h b/bsp/coreip-e76-arty/metal.h index 35ad054..b384007 100644 --- a/bsp/coreip-e76-arty/metal.h +++ b/bsp/coreip-e76-arty/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 31 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 31 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -47,6 +61,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -64,6 +79,12 @@ asm (".weak __metal_dt_tlclk"); struct __metal_driver_fixed_clock __metal_dt_tlclk; +asm (".weak __metal_dt_mem_memory_80000000"); +struct metal_memory __metal_dt_mem_memory_80000000; + +asm (".weak __metal_dt_mem_spi_20004000"); +struct metal_memory __metal_dt_mem_spi_20004000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -72,9 +93,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -159,6 +179,28 @@ struct __metal_driver_fixed_clock __metal_dt_tlclk = { .rate = 32500000UL, }; +struct metal_memory __metal_dt_mem_memory_80000000 = { + ._base_address = 2147483648UL, + ._size = 268435456UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_20004000 = { + ._base_address = 1073741824UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -167,8 +209,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -177,11 +220,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 65000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -193,9 +236,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -429,6 +471,13 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { }; +#define __METAL_DT_MAX_MEMORIES 2 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_memory_80000000, + &__metal_dt_mem_spi_20004000}; + /* From serial@20000000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) @@ -441,22 +490,12 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-e76-arty/metal.ramrodata.lds b/bsp/coreip-e76-arty/metal.ramrodata.lds index cb59d74..2c0d61e 100644 --- a/bsp/coreip-e76-arty/metal.ramrodata.lds +++ b/bsp/coreip-e76-arty/metal.ramrodata.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-e76-arty/metal.scratchpad.lds b/bsp/coreip-e76-arty/metal.scratchpad.lds index f75dc04..fe384ff 100644 --- a/bsp/coreip-e76-arty/metal.scratchpad.lds +++ b/bsp/coreip-e76-arty/metal.scratchpad.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e76-rtl/metal.default.lds b/bsp/coreip-e76-rtl/metal.default.lds index ea5918b..e21f7c0 100644 --- a/bsp/coreip-e76-rtl/metal.default.lds +++ b/bsp/coreip-e76-rtl/metal.default.lds @@ -19,6 +19,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e76-rtl/metal.h b/bsp/coreip-e76-rtl/metal.h index 393700c..abd7a4d 100644 --- a/bsp/coreip-e76-rtl/metal.h +++ b/bsp/coreip-e76-rtl/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 128 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 128 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -41,6 +55,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -48,6 +63,9 @@ #include <metal/drivers/sifive,global-external-interrupts0.h> #include <metal/drivers/sifive,test0.h> +asm (".weak __metal_dt_mem_memory_80000000"); +struct metal_memory __metal_dt_mem_memory_80000000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -56,9 +74,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -76,6 +93,17 @@ asm (".weak __metal_dt_teststatus_4000"); struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; +struct metal_memory __metal_dt_mem_memory_80000000 = { + ._base_address = 2147483648UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -84,8 +112,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -94,11 +123,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -110,9 +139,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -271,27 +299,23 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { }; +#define __METAL_DT_MAX_MEMORIES 1 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_memory_80000000}; + /* From clint@2000000 */ #define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-e76-rtl/metal.ramrodata.lds b/bsp/coreip-e76-rtl/metal.ramrodata.lds index 201621e..901ac13 100644 --- a/bsp/coreip-e76-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e76-rtl/metal.ramrodata.lds @@ -19,6 +19,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-e76-rtl/metal.scratchpad.lds b/bsp/coreip-e76-rtl/metal.scratchpad.lds index ea5918b..e21f7c0 100644 --- a/bsp/coreip-e76-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e76-rtl/metal.scratchpad.lds @@ -19,6 +19,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-s51-arty/metal.default.lds b/bsp/coreip-s51-arty/metal.default.lds index 965607a..87bc213 100644 --- a/bsp/coreip-s51-arty/metal.default.lds +++ b/bsp/coreip-s51-arty/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-s51-arty/metal.h b/bsp/coreip-s51-arty/metal.h index 0dd45af..947c49d 100644 --- a/bsp/coreip-s51-arty/metal.h +++ b/bsp/coreip-s51-arty/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 27 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 27 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -47,6 +61,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -65,6 +80,15 @@ asm (".weak __metal_dt_clock_0"); struct __metal_driver_fixed_clock __metal_dt_clock_0; +asm (".weak __metal_dt_mem_dtim_80000000"); +struct metal_memory __metal_dt_mem_dtim_80000000; + +asm (".weak __metal_dt_mem_itim_8000000"); +struct metal_memory __metal_dt_mem_itim_8000000; + +asm (".weak __metal_dt_mem_spi_20004000"); +struct metal_memory __metal_dt_mem_spi_20004000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -73,9 +97,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -160,6 +183,39 @@ struct __metal_driver_fixed_clock __metal_dt_clock_0 = { .rate = 32500000UL, }; +struct metal_memory __metal_dt_mem_dtim_80000000 = { + ._base_address = 2147483648UL, + ._size = 65536UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_8000000 = { + ._base_address = 134217728UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_20004000 = { + ._base_address = 1073741824UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -168,8 +224,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -178,11 +235,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 65000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -194,9 +251,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -214,8 +270,7 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, .interrupt_lines[0] = 16, .interrupt_lines[1] = 17, @@ -440,6 +495,14 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { }; +#define __METAL_DT_MAX_MEMORIES 3 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_dtim_80000000, + &__metal_dt_mem_itim_8000000, + &__metal_dt_mem_spi_20004000}; + /* From serial@20000000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) @@ -452,22 +515,12 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-s51-arty/metal.ramrodata.lds b/bsp/coreip-s51-arty/metal.ramrodata.lds index 8faa8d0..2056624 100644 --- a/bsp/coreip-s51-arty/metal.ramrodata.lds +++ b/bsp/coreip-s51-arty/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-s51-arty/metal.scratchpad.lds b/bsp/coreip-s51-arty/metal.scratchpad.lds index 0edadd5..fe62b3a 100644 --- a/bsp/coreip-s51-arty/metal.scratchpad.lds +++ b/bsp/coreip-s51-arty/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-s51-rtl/metal.default.lds b/bsp/coreip-s51-rtl/metal.default.lds index a997b8b..e616f3d 100644 --- a/bsp/coreip-s51-rtl/metal.default.lds +++ b/bsp/coreip-s51-rtl/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-s51-rtl/metal.h b/bsp/coreip-s51-rtl/metal.h index b815b67..849add9 100644 --- a/bsp/coreip-s51-rtl/metal.h +++ b/bsp/coreip-s51-rtl/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 128 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 128 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -43,6 +57,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -51,6 +66,15 @@ #include <metal/drivers/sifive,global-external-interrupts0.h> #include <metal/drivers/sifive,test0.h> +asm (".weak __metal_dt_mem_testram_20000000"); +struct metal_memory __metal_dt_mem_testram_20000000; + +asm (".weak __metal_dt_mem_dtim_80000000"); +struct metal_memory __metal_dt_mem_dtim_80000000; + +asm (".weak __metal_dt_mem_itim_8000000"); +struct metal_memory __metal_dt_mem_itim_8000000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -59,9 +83,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -83,6 +106,39 @@ asm (".weak __metal_dt_teststatus_4000"); struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; +struct metal_memory __metal_dt_mem_testram_20000000 = { + ._base_address = 536870912UL, + ._size = 67108864UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_dtim_80000000 = { + ._base_address = 2147483648UL, + ._size = 65536UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_8000000 = { + ._base_address = 134217728UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -91,8 +147,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -101,11 +158,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -117,9 +174,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -137,8 +193,7 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, .interrupt_lines[0] = 16, .interrupt_lines[1] = 17, @@ -304,27 +359,25 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { }; +#define __METAL_DT_MAX_MEMORIES 3 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_testram_20000000, + &__metal_dt_mem_dtim_80000000, + &__metal_dt_mem_itim_8000000}; + /* From clint@2000000 */ #define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-s51-rtl/metal.ramrodata.lds b/bsp/coreip-s51-rtl/metal.ramrodata.lds index 23aef82..9aa142b 100644 --- a/bsp/coreip-s51-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s51-rtl/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-s51-rtl/metal.scratchpad.lds b/bsp/coreip-s51-rtl/metal.scratchpad.lds index c789249..3d4d966 100644 --- a/bsp/coreip-s51-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s51-rtl/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-s54-arty/metal.default.lds b/bsp/coreip-s54-arty/metal.default.lds index 965607a..87bc213 100644 --- a/bsp/coreip-s54-arty/metal.default.lds +++ b/bsp/coreip-s54-arty/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-s54-arty/metal.h b/bsp/coreip-s54-arty/metal.h index d4ac5cb..546c3c6 100644 --- a/bsp/coreip-s54-arty/metal.h +++ b/bsp/coreip-s54-arty/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 27 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 27 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -47,6 +61,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -65,6 +80,15 @@ asm (".weak __metal_dt_clock_0"); struct __metal_driver_fixed_clock __metal_dt_clock_0; +asm (".weak __metal_dt_mem_dtim_80000000"); +struct metal_memory __metal_dt_mem_dtim_80000000; + +asm (".weak __metal_dt_mem_itim_8000000"); +struct metal_memory __metal_dt_mem_itim_8000000; + +asm (".weak __metal_dt_mem_spi_20004000"); +struct metal_memory __metal_dt_mem_spi_20004000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -73,9 +97,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -160,6 +183,39 @@ struct __metal_driver_fixed_clock __metal_dt_clock_0 = { .rate = 32500000UL, }; +struct metal_memory __metal_dt_mem_dtim_80000000 = { + ._base_address = 2147483648UL, + ._size = 65536UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_8000000 = { + ._base_address = 134217728UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_20004000 = { + ._base_address = 1073741824UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -168,8 +224,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -178,11 +235,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 65000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -194,9 +251,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -214,8 +270,7 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, .interrupt_lines[0] = 16, .interrupt_lines[1] = 17, @@ -440,6 +495,14 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { }; +#define __METAL_DT_MAX_MEMORIES 3 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_dtim_80000000, + &__metal_dt_mem_itim_8000000, + &__metal_dt_mem_spi_20004000}; + /* From serial@20000000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) @@ -452,22 +515,12 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-s54-arty/metal.ramrodata.lds b/bsp/coreip-s54-arty/metal.ramrodata.lds index 8faa8d0..2056624 100644 --- a/bsp/coreip-s54-arty/metal.ramrodata.lds +++ b/bsp/coreip-s54-arty/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-s54-arty/metal.scratchpad.lds b/bsp/coreip-s54-arty/metal.scratchpad.lds index 0edadd5..fe62b3a 100644 --- a/bsp/coreip-s54-arty/metal.scratchpad.lds +++ b/bsp/coreip-s54-arty/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-s54-rtl/metal.default.lds b/bsp/coreip-s54-rtl/metal.default.lds index a997b8b..e616f3d 100644 --- a/bsp/coreip-s54-rtl/metal.default.lds +++ b/bsp/coreip-s54-rtl/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-s54-rtl/metal.h b/bsp/coreip-s54-rtl/metal.h index 360c3d2..0003693 100644 --- a/bsp/coreip-s54-rtl/metal.h +++ b/bsp/coreip-s54-rtl/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 128 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 128 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -43,6 +57,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -51,6 +66,15 @@ #include <metal/drivers/sifive,global-external-interrupts0.h> #include <metal/drivers/sifive,test0.h> +asm (".weak __metal_dt_mem_testram_20000000"); +struct metal_memory __metal_dt_mem_testram_20000000; + +asm (".weak __metal_dt_mem_dtim_80000000"); +struct metal_memory __metal_dt_mem_dtim_80000000; + +asm (".weak __metal_dt_mem_itim_8000000"); +struct metal_memory __metal_dt_mem_itim_8000000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -59,9 +83,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -83,6 +106,39 @@ asm (".weak __metal_dt_teststatus_4000"); struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; +struct metal_memory __metal_dt_mem_testram_20000000 = { + ._base_address = 536870912UL, + ._size = 67108864UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_dtim_80000000 = { + ._base_address = 2147483648UL, + ._size = 65536UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_8000000 = { + ._base_address = 134217728UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -91,8 +147,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -101,11 +158,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -117,9 +174,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -137,8 +193,7 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, .interrupt_lines[0] = 16, .interrupt_lines[1] = 17, @@ -304,27 +359,25 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { }; +#define __METAL_DT_MAX_MEMORIES 3 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_testram_20000000, + &__metal_dt_mem_dtim_80000000, + &__metal_dt_mem_itim_8000000}; + /* From clint@2000000 */ #define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-s54-rtl/metal.ramrodata.lds b/bsp/coreip-s54-rtl/metal.ramrodata.lds index 23aef82..9aa142b 100644 --- a/bsp/coreip-s54-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s54-rtl/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-s54-rtl/metal.scratchpad.lds b/bsp/coreip-s54-rtl/metal.scratchpad.lds index c789249..3d4d966 100644 --- a/bsp/coreip-s54-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s54-rtl/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-s76-arty/metal.default.lds b/bsp/coreip-s76-arty/metal.default.lds index c4cae6b..ccd5fb0 100644 --- a/bsp/coreip-s76-arty/metal.default.lds +++ b/bsp/coreip-s76-arty/metal.default.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-s76-arty/metal.h b/bsp/coreip-s76-arty/metal.h index 04f7436..0a385de 100644 --- a/bsp/coreip-s76-arty/metal.h +++ b/bsp/coreip-s76-arty/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 31 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 31 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -47,6 +61,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -64,6 +79,12 @@ asm (".weak __metal_dt_tlclk"); struct __metal_driver_fixed_clock __metal_dt_tlclk; +asm (".weak __metal_dt_mem_memory_80000000"); +struct metal_memory __metal_dt_mem_memory_80000000; + +asm (".weak __metal_dt_mem_spi_20004000"); +struct metal_memory __metal_dt_mem_spi_20004000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -72,9 +93,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -159,6 +179,28 @@ struct __metal_driver_fixed_clock __metal_dt_tlclk = { .rate = 32500000UL, }; +struct metal_memory __metal_dt_mem_memory_80000000 = { + ._base_address = 2147483648UL, + ._size = 268435456UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_20004000 = { + ._base_address = 1073741824UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -167,8 +209,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -177,11 +220,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 65000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -193,9 +236,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -429,6 +471,13 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { }; +#define __METAL_DT_MAX_MEMORIES 2 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_memory_80000000, + &__metal_dt_mem_spi_20004000}; + /* From serial@20000000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) @@ -441,22 +490,12 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-s76-arty/metal.ramrodata.lds b/bsp/coreip-s76-arty/metal.ramrodata.lds index cb59d74..2c0d61e 100644 --- a/bsp/coreip-s76-arty/metal.ramrodata.lds +++ b/bsp/coreip-s76-arty/metal.ramrodata.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/coreip-s76-arty/metal.scratchpad.lds b/bsp/coreip-s76-arty/metal.scratchpad.lds index f75dc04..fe384ff 100644 --- a/bsp/coreip-s76-arty/metal.scratchpad.lds +++ b/bsp/coreip-s76-arty/metal.scratchpad.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-s76-rtl/metal.default.lds b/bsp/coreip-s76-rtl/metal.default.lds index ea5918b..e21f7c0 100644 --- a/bsp/coreip-s76-rtl/metal.default.lds +++ b/bsp/coreip-s76-rtl/metal.default.lds @@ -19,6 +19,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-s76-rtl/metal.h b/bsp/coreip-s76-rtl/metal.h index 8f096d0..c10f9d6 100644 --- a/bsp/coreip-s76-rtl/metal.h +++ b/bsp/coreip-s76-rtl/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 128 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 128 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -41,6 +55,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -48,6 +63,9 @@ #include <metal/drivers/sifive,global-external-interrupts0.h> #include <metal/drivers/sifive,test0.h> +asm (".weak __metal_dt_mem_memory_80000000"); +struct metal_memory __metal_dt_mem_memory_80000000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -56,9 +74,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -76,6 +93,17 @@ asm (".weak __metal_dt_teststatus_4000"); struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; +struct metal_memory __metal_dt_mem_memory_80000000 = { + ._base_address = 2147483648UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -84,8 +112,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -94,11 +123,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -110,9 +139,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -271,27 +299,23 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { }; +#define __METAL_DT_MAX_MEMORIES 1 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_memory_80000000}; + /* From clint@2000000 */ #define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/coreip-s76-rtl/metal.ramrodata.lds b/bsp/coreip-s76-rtl/metal.ramrodata.lds index 201621e..901ac13 100644 --- a/bsp/coreip-s76-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s76-rtl/metal.ramrodata.lds @@ -19,6 +19,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-s76-rtl/metal.scratchpad.lds b/bsp/coreip-s76-rtl/metal.scratchpad.lds index ea5918b..e21f7c0 100644 --- a/bsp/coreip-s76-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s76-rtl/metal.scratchpad.lds @@ -19,6 +19,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/coreip-u54-rtl/README.md b/bsp/coreip-u54-rtl/README.md new file mode 100644 index 0000000..cd34149 --- /dev/null +++ b/bsp/coreip-u54-rtl/README.md @@ -0,0 +1,17 @@ +The SiFive U54 Standard Core is a single-core instantiation of the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux. + +The U54 is ideal for low-cost Linux applications such as IoT nodes and gateways, point-of-sale, and networking. + +This target features: + +- 1 RV64GC U54 Application Core +- 16KB L1 I-cache with ECC +- 16KB L1 D-cache with ECC +- 8 Region Physical Memory Protection +- 48 Local Interrupts per core +- Sv39 Virtual Memory support with 38 Physical Address bits +- Integrated 128KB L2 Cache with ECC +- Real-time capabilities +- CLINT for multi-core timer and software interrupts +- PLIC with support for up to 128 interrupts with 7 priority levels +- Debug with instruction trace diff --git a/bsp/coreip-u54-rtl/design.dts b/bsp/coreip-u54-rtl/design.dts new file mode 100644 index 0000000..b773072 --- /dev/null +++ b/bsp/coreip-u54-rtl/design.dts @@ -0,0 +1,133 @@ +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev"; + model = "SiFive,FU540G"; + L19: cpus { + #address-cells = <1>; + #size-cells = <0>; + L8: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <16384>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <16384>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L16>; + reg = <0x0>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L6>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L5: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L11: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x20000000>; + }; + L18: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus"; + ranges; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; + L13: axi4-periph-port@20000000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,axi4-periph-port", "sifive,axi4-port", "sifive,periph-port", "simple-bus"; + ranges = <0x0 0x20000000 0x0 0x20000000 0x0 0x20000000 0x1 0x0 0x1 0x0 0xf 0x0>; + }; + L12: axi4-sys-port@40000000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-bus"; + ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x10 0x0 0x10 0x0 0x30 0x0>; + }; + L7: bus-error-unit@1700000 { + compatible = "sifive,buserror0"; + interrupt-parent = <&L2>; + interrupts = <132>; + reg = <0x0 0x1700000 0x0 0x1000>; + reg-names = "control"; + }; + L16: cache-controller@2010000 { + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + compatible = "sifive,ccache0", "cache"; + interrupt-parent = <&L2>; + interrupts = <128 129 130 131>; + next-level-cache = <&L0 &L11>; + reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x40000>; + reg-names = "control", "sideband"; + sifive,ecc-granularity = <8>; + sifive,mshr-count = <5>; + }; + L3: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L5 3 &L5 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + reg-names = "control"; + }; + L4: debug-controller@0 { + compatible = "sifive,debug-013", "riscv,debug-013"; + interrupts-extended = <&L5 65535>; + reg = <0x0 0x0 0x0 0x1000>; + reg-names = "control"; + }; + L1: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x0 0x3000 0x0 0x1000>; + }; + L10: global-external-interrupts { + compatible = "sifive,global-external-interrupts0"; + interrupt-parent = <&L2>; + interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>; + }; + L2: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L5 11 &L5 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <132>; + }; + L6: itim@1800000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1800000 0x0 0x4000>; + reg-names = "mem"; + }; + L0: rom@a000000 { + compatible = "ucbbar,cacheable-zero0"; + reg = <0x0 0xa000000 0x0 0x2000000>; + }; + L9: teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x0 0x4000 0x0 0x1000>; + reg-names = "control"; + }; + }; +}; diff --git a/bsp/coreip-u54-rtl/metal.default.lds b/bsp/coreip-u54-rtl/metal.default.lds new file mode 100644 index 0000000..ae24b07 --- /dev/null +++ b/bsp/coreip-u54-rtl/metal.default.lds @@ -0,0 +1,226 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_LOAD; + itim PT_LOAD; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >ram AT>ram :ram + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >ram AT>ram :ram + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >ram AT>ram :ram + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >ram AT>ram :ram + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>ram :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>ram :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >ram AT>ram :ram + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>ram :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-u54-rtl/metal.h b/bsp/coreip-u54-rtl/metal.h new file mode 100644 index 0000000..3955675 --- /dev/null +++ b/bsp/coreip-u54-rtl/metal.h @@ -0,0 +1,393 @@ +#ifndef ASSEMBLY + +#ifndef COREIP_U54_RTL__METAL_H +#define COREIP_U54_RTL__METAL_H + +#ifdef __METAL_MACHINE_MACROS + +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif +#define __METAL_PLIC_SUBINTERRUPTS 133 + +#define __METAL_PLIC_NUM_PARENTS 2 + +#ifndef __METAL_PLIC_SUBINTERRUPTS +#define __METAL_PLIC_SUBINTERRUPTS 0 +#endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif +#ifndef __METAL_CLIC_SUBINTERRUPTS +#define __METAL_CLIC_SUBINTERRUPTS 0 +#endif + +#else /* ! __METAL_MACHINE_MACROS */ + +#define __METAL_CLINT_2000000_INTERRUPTS 2 + +#define METAL_MAX_CLINT_INTERRUPTS 2 + +#define __METAL_CLINT_NUM_PARENTS 2 + +#define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 2 + +#define __METAL_PLIC_SUBINTERRUPTS 133 + +#define METAL_MAX_PLIC_INTERRUPTS 2 + +#define __METAL_PLIC_NUM_PARENTS 2 + +#define __METAL_CLIC_SUBINTERRUPTS 0 +#define METAL_MAX_CLIC_INTERRUPTS 0 + +#define METAL_MAX_LOCAL_EXT_INTERRUPTS 0 + +#define __METAL_GLOBAL_EXTERNAL_INTERRUPTS_INTERRUPTS 127 + +#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 127 + +#define METAL_MAX_GPIO_INTERRUPTS 0 + +#define METAL_MAX_UART_INTERRUPTS 0 + + +#include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> +#include <metal/drivers/riscv,clint0.h> +#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv,plic0.h> +#include <metal/pmp.h> +#include <metal/drivers/sifive,global-external-interrupts0.h> +#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive,fu540-c000,l2.h> + +asm (".weak __metal_dt_mem_itim_1800000"); +struct metal_memory __metal_dt_mem_itim_1800000; + +asm (".weak __metal_dt_mem_memory_80000000"); +struct metal_memory __metal_dt_mem_memory_80000000; + +/* From clint@2000000 */ +asm (".weak __metal_dt_clint_2000000"); +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; + +/* From cpu@0 */ +asm (".weak __metal_dt_cpu_0"); +struct __metal_driver_cpu __metal_dt_cpu_0; + +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; + +/* From interrupt_controller@c000000 */ +asm (".weak __metal_dt_interrupt_controller_c000000"); +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; + +asm (".weak __metal_dt_pmp_0"); +struct metal_pmp __metal_dt_pmp_0; + +/* From global_external_interrupts */ +asm (".weak __metal_dt_global_external_interrupts"); +struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; + +/* From teststatus@4000 */ +asm (".weak __metal_dt_teststatus_4000"); +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; + +/* From cache_controller@2010000 */ +asm (".weak __metal_dt_cache_controller_2010000"); +struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000; + + +struct metal_memory __metal_dt_mem_itim_1800000 = { + ._base_address = 25165824UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_memory_80000000 = { + ._base_address = 2147483648UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +/* From clint@2000000 */ +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { + .vtable = &__metal_driver_vtable_riscv_clint0, + .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable, + .control_base = 33554432UL, + .control_size = 65536UL, + .init_done = 0, + .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[1] = 7, +}; + +/* From cpu@0 */ +struct __metal_driver_cpu __metal_dt_cpu_0 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller@c000000 */ +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { + .vtable = &__metal_driver_vtable_riscv_plic0, + .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, + .init_done = 0, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[1] = 9, + .control_base = 201326592UL, + .control_size = 67108864UL, + .max_priority = 7UL, + .num_interrupts = 133UL, + .interrupt_controller = 1, +}; + +/* From pmp@0 */ +struct metal_pmp __metal_dt_pmp_0 = { + .num_regions = 8UL, +}; + +/* From global_external_interrupts */ +struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { + .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0, + .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, + .init_done = 0, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS, + .interrupt_lines[0] = 1, + .interrupt_lines[1] = 2, + .interrupt_lines[2] = 3, + .interrupt_lines[3] = 4, + .interrupt_lines[4] = 5, + .interrupt_lines[5] = 6, + .interrupt_lines[6] = 7, + .interrupt_lines[7] = 8, + .interrupt_lines[8] = 9, + .interrupt_lines[9] = 10, + .interrupt_lines[10] = 11, + .interrupt_lines[11] = 12, + .interrupt_lines[12] = 13, + .interrupt_lines[13] = 14, + .interrupt_lines[14] = 15, + .interrupt_lines[15] = 16, + .interrupt_lines[16] = 17, + .interrupt_lines[17] = 18, + .interrupt_lines[18] = 19, + .interrupt_lines[19] = 20, + .interrupt_lines[20] = 21, + .interrupt_lines[21] = 22, + .interrupt_lines[22] = 23, + .interrupt_lines[23] = 24, + .interrupt_lines[24] = 25, + .interrupt_lines[25] = 26, + .interrupt_lines[26] = 27, + .interrupt_lines[27] = 28, + .interrupt_lines[28] = 29, + .interrupt_lines[29] = 30, + .interrupt_lines[30] = 31, + .interrupt_lines[31] = 32, + .interrupt_lines[32] = 33, + .interrupt_lines[33] = 34, + .interrupt_lines[34] = 35, + .interrupt_lines[35] = 36, + .interrupt_lines[36] = 37, + .interrupt_lines[37] = 38, + .interrupt_lines[38] = 39, + .interrupt_lines[39] = 40, + .interrupt_lines[40] = 41, + .interrupt_lines[41] = 42, + .interrupt_lines[42] = 43, + .interrupt_lines[43] = 44, + .interrupt_lines[44] = 45, + .interrupt_lines[45] = 46, + .interrupt_lines[46] = 47, + .interrupt_lines[47] = 48, + .interrupt_lines[48] = 49, + .interrupt_lines[49] = 50, + .interrupt_lines[50] = 51, + .interrupt_lines[51] = 52, + .interrupt_lines[52] = 53, + .interrupt_lines[53] = 54, + .interrupt_lines[54] = 55, + .interrupt_lines[55] = 56, + .interrupt_lines[56] = 57, + .interrupt_lines[57] = 58, + .interrupt_lines[58] = 59, + .interrupt_lines[59] = 60, + .interrupt_lines[60] = 61, + .interrupt_lines[61] = 62, + .interrupt_lines[62] = 63, + .interrupt_lines[63] = 64, + .interrupt_lines[64] = 65, + .interrupt_lines[65] = 66, + .interrupt_lines[66] = 67, + .interrupt_lines[67] = 68, + .interrupt_lines[68] = 69, + .interrupt_lines[69] = 70, + .interrupt_lines[70] = 71, + .interrupt_lines[71] = 72, + .interrupt_lines[72] = 73, + .interrupt_lines[73] = 74, + .interrupt_lines[74] = 75, + .interrupt_lines[75] = 76, + .interrupt_lines[76] = 77, + .interrupt_lines[77] = 78, + .interrupt_lines[78] = 79, + .interrupt_lines[79] = 80, + .interrupt_lines[80] = 81, + .interrupt_lines[81] = 82, + .interrupt_lines[82] = 83, + .interrupt_lines[83] = 84, + .interrupt_lines[84] = 85, + .interrupt_lines[85] = 86, + .interrupt_lines[86] = 87, + .interrupt_lines[87] = 88, + .interrupt_lines[88] = 89, + .interrupt_lines[89] = 90, + .interrupt_lines[90] = 91, + .interrupt_lines[91] = 92, + .interrupt_lines[92] = 93, + .interrupt_lines[93] = 94, + .interrupt_lines[94] = 95, + .interrupt_lines[95] = 96, + .interrupt_lines[96] = 97, + .interrupt_lines[97] = 98, + .interrupt_lines[98] = 99, + .interrupt_lines[99] = 100, + .interrupt_lines[100] = 101, + .interrupt_lines[101] = 102, + .interrupt_lines[102] = 103, + .interrupt_lines[103] = 104, + .interrupt_lines[104] = 105, + .interrupt_lines[105] = 106, + .interrupt_lines[106] = 107, + .interrupt_lines[107] = 108, + .interrupt_lines[108] = 109, + .interrupt_lines[109] = 110, + .interrupt_lines[110] = 111, + .interrupt_lines[111] = 112, + .interrupt_lines[112] = 113, + .interrupt_lines[113] = 114, + .interrupt_lines[114] = 115, + .interrupt_lines[115] = 116, + .interrupt_lines[116] = 117, + .interrupt_lines[117] = 118, + .interrupt_lines[118] = 119, + .interrupt_lines[119] = 120, + .interrupt_lines[120] = 121, + .interrupt_lines[121] = 122, + .interrupt_lines[122] = 123, + .interrupt_lines[123] = 124, + .interrupt_lines[124] = 125, + .interrupt_lines[125] = 126, + .interrupt_lines[126] = 127, +}; + +/* From teststatus@4000 */ +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { + .vtable = &__metal_driver_vtable_sifive_test0, + .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown, + .base = 16384UL, + .size = 4096UL, +}; + +/* From cache_controller@2010000 */ +struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = { + .vtable = &__metal_driver_vtable_sifive_fu540_c000_l2, + .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache, +}; + + +#define __METAL_DT_MAX_MEMORIES 2 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_itim_1800000, + &__metal_dt_mem_memory_80000000}; + +/* From clint@2000000 */ +#define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) + +#define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) + +#define __METAL_DT_MAX_HARTS 1 + +asm (".weak __metal_cpu_table"); +struct __metal_driver_cpu *__metal_cpu_table[] = { + &__metal_dt_cpu_0}; + +/* From interrupt_controller@c000000 */ +#define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +/* From pmp@0 */ +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) + +/* From global_external_interrupts */ +#define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) + +#define __METAL_DT_GLOBAL_EXTERNAL_INTERRUPTS_HANDLE (&__metal_dt_global_external_interrupts.irc) + +#define __MEE_DT_MAX_GPIOS 0 + +asm (".weak __metal_gpio_table"); +struct __metal_driver_sifive_gpio0 *__metal_gpio_table[] = { + NULL }; +#define __METAL_DT_MAX_BUTTONS 0 + +asm (".weak __metal_button_table"); +struct __metal_driver_sifive_gpio_button *__metal_button_table[] = { + NULL }; +#define __METAL_DT_MAX_LEDS 0 + +asm (".weak __metal_led_table"); +struct __metal_driver_sifive_gpio_led *__metal_led_table[] = { + NULL }; +#define __METAL_DT_MAX_SWITCHES 0 + +asm (".weak __metal_switch_table"); +struct __metal_driver_sifive_gpio_switch *__metal_switch_table[] = { + NULL }; +#define __METAL_DT_MAX_SPIS 0 + +asm (".weak __metal_spi_table"); +struct __metal_driver_sifive_spi0 *__metal_spi_table[] = { + NULL }; +/* From teststatus@4000 */ +#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_teststatus_4000.shutdown) + +#define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown) + + +#endif /* ! __METAL_MACHINE_MACROS */ +#endif /* COREIP_U54_RTL__METAL_H*/ +#endif /* ! ASSEMBLY */ diff --git a/bsp/coreip-u54-rtl/metal.ramrodata.lds b/bsp/coreip-u54-rtl/metal.ramrodata.lds new file mode 100644 index 0000000..306ba19 --- /dev/null +++ b/bsp/coreip-u54-rtl/metal.ramrodata.lds @@ -0,0 +1,223 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_LOAD; + itim PT_LOAD; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >ram AT>ram :ram + + + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >ram AT>ram :ram + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >ram AT>ram :ram + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>ram :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>ram :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >ram AT>ram :ram + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>ram :ram_init + + + .data : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-u54-rtl/metal.scratchpad.lds b/bsp/coreip-u54-rtl/metal.scratchpad.lds new file mode 100644 index 0000000..ae24b07 --- /dev/null +++ b/bsp/coreip-u54-rtl/metal.scratchpad.lds @@ -0,0 +1,226 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_LOAD; + itim PT_LOAD; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >ram AT>ram :ram + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >ram AT>ram :ram + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >ram AT>ram :ram + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >ram AT>ram :ram + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>ram :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>ram :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >ram AT>ram :ram + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>ram :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-u54-rtl/settings.mk b/bsp/coreip-u54-rtl/settings.mk new file mode 100644 index 0000000..d6b3a83 --- /dev/null +++ b/bsp/coreip-u54-rtl/settings.mk @@ -0,0 +1,7 @@ +RISCV_ARCH=rv64imafdc +RISCV_ABI=lp64d +RISCV_CMODEL=medany + +COREIP_MEM_WIDTH=128 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-u54mc-rtl/README.md b/bsp/coreip-u54mc-rtl/README.md new file mode 100644 index 0000000..1d26288 --- /dev/null +++ b/bsp/coreip-u54mc-rtl/README.md @@ -0,0 +1,23 @@ +The SiFive U54-MC Standard Core is the world’s first RISC-V application processor, capable of supporting full-featured operating systems such as Linux. + +The U54-MC has 4x 64-bit U5 cores and 1x 64-bit S5 core—providing high performance with maximum efficiency. This core is an ideal choice for low-cost Linux applications such as IoT nodes and gateways, storage, and networking. + +This target features: + +- 4x RV64GC U54 Application Cores + - 32KB L1 I-cache with ECC + - 32KB L1 D-cache with ECC + - 8 Region Physical Memory Protection + - 48 Local Interrupts per core + - Sv39 Virtual Memory support with 38 Physical Address bits +- 1x RV64IMAC S51 Monitor Core + - 16KB L1 I-Cache with ECC + - 8KB DTIM with ECC + - 8 Region Physical Memory Protection + - 48 Local Interrupts +- Fully Coherent TileLink Bus +- Integrated 2MB L2 Cache with ECC +- Real-time capabilities +- CLINT for multi-core timer and software interrupts +- PLIC with support for up to 511 interrupts with 7 priority levels +- Debug with instruction trace diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts new file mode 100644 index 0000000..27a3c94 --- /dev/null +++ b/bsp/coreip-u54mc-rtl/design.dts @@ -0,0 +1,290 @@ +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev"; + model = "SiFive,FU540G"; + L36: cpus { + #address-cells = <1>; + #size-cells = <0>; + L9: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&L33>; + reg = <0x0>; + riscv,isa = "rv64imac"; + sifive,dtim = <&L7>; + sifive,itim = <&L6>; + status = "okay"; + timebase-frequency = <1000000>; + L5: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L13: cpu@1 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L33>; + reg = <0x1>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L11>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L10: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L17: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L33>; + reg = <0x2>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L15>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L14: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L21: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L33>; + reg = <0x3>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L19>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L18: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L25: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L33>; + reg = <0x4>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L23>; + status = "okay"; + timebase-frequency = <1000000>; + tlb-split; + L22: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L28: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x20000000>; + }; + L35: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus"; + ranges; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; + L30: axi4-periph-port@20000000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,axi4-periph-port", "sifive,axi4-port", "sifive,periph-port", "simple-bus"; + ranges = <0x0 0x20000000 0x0 0x20000000 0x0 0x20000000 0x1 0x0 0x1 0x0 0xf 0x0>; + }; + L29: axi4-sys-port@40000000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-bus"; + ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x10 0x0 0x10 0x0 0x30 0x0>; + }; + L8: bus-error-unit@1700000 { + compatible = "sifive,buserror0"; + interrupt-parent = <&L2>; + interrupts = <132>; + reg = <0x0 0x1700000 0x0 0x1000>; + reg-names = "control"; + }; + L12: bus-error-unit@1701000 { + compatible = "sifive,buserror0"; + interrupt-parent = <&L2>; + interrupts = <133>; + reg = <0x0 0x1701000 0x0 0x1000>; + reg-names = "control"; + }; + L16: bus-error-unit@1702000 { + compatible = "sifive,buserror0"; + interrupt-parent = <&L2>; + interrupts = <134>; + reg = <0x0 0x1702000 0x0 0x1000>; + reg-names = "control"; + }; + L20: bus-error-unit@1703000 { + compatible = "sifive,buserror0"; + interrupt-parent = <&L2>; + interrupts = <135>; + reg = <0x0 0x1703000 0x0 0x1000>; + reg-names = "control"; + }; + L24: bus-error-unit@1704000 { + compatible = "sifive,buserror0"; + interrupt-parent = <&L2>; + interrupts = <136>; + reg = <0x0 0x1704000 0x0 0x1000>; + reg-names = "control"; + }; + L33: cache-controller@2010000 { + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + compatible = "sifive,ccache0", "cache"; + interrupt-parent = <&L2>; + interrupts = <128 129 130 131>; + next-level-cache = <&L0 &L28>; + reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x200000>; + reg-names = "control", "sideband"; + sifive,ecc-granularity = <8>; + sifive,mshr-count = <6>; + }; + L3: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L5 3 &L5 7 &L10 3 &L10 7 &L14 3 &L14 7 &L18 3 &L18 7 &L22 3 &L22 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + reg-names = "control"; + }; + L4: debug-controller@0 { + compatible = "sifive,debug-013", "riscv,debug-013"; + interrupts-extended = <&L5 65535 &L10 65535 &L14 65535 &L18 65535 &L22 65535>; + reg = <0x0 0x0 0x0 0x1000>; + reg-names = "control"; + }; + L7: dtim@1000000 { + compatible = "sifive,dtim0"; + reg = <0x0 0x1000000 0x0 0x2000>; + reg-names = "mem"; + }; + L1: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x0 0x3000 0x0 0x1000>; + }; + L27: global-external-interrupts { + compatible = "sifive,global-external-interrupts0"; + interrupt-parent = <&L2>; + interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>; + }; + L2: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L5 11 &L10 11 &L10 9 &L14 11 &L14 9 &L18 11 &L18 9 &L22 11 &L22 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <136>; + }; + L6: itim@1800000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1800000 0x0 0x4000>; + reg-names = "mem"; + }; + L11: itim@1808000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1808000 0x0 0x8000>; + reg-names = "mem"; + }; + L15: itim@1810000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1810000 0x0 0x8000>; + reg-names = "mem"; + }; + L19: itim@1818000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1818000 0x0 0x8000>; + reg-names = "mem"; + }; + L23: itim@1820000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1820000 0x0 0x8000>; + reg-names = "mem"; + }; + L0: rom@a000000 { + compatible = "ucbbar,cacheable-zero0"; + reg = <0x0 0xa000000 0x0 0x2000000>; + }; + L26: teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x0 0x4000 0x0 0x1000>; + reg-names = "control"; + }; + }; +}; diff --git a/bsp/coreip-u54mc-rtl/metal.default.lds b/bsp/coreip-u54mc-rtl/metal.default.lds new file mode 100644 index 0000000..0d12f67 --- /dev/null +++ b/bsp/coreip-u54mc-rtl/metal.default.lds @@ -0,0 +1,230 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_LOAD; + itim PT_LOAD; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >ram AT>ram :ram + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >ram AT>ram :ram + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >ram AT>ram :ram + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >ram AT>ram :ram + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>ram :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>ram :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >ram AT>ram :ram + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>ram :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + . = __stack_size; + . = __stack_size; + . = __stack_size; + . = __stack_size; + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h new file mode 100644 index 0000000..380de59 --- /dev/null +++ b/bsp/coreip-u54mc-rtl/metal.h @@ -0,0 +1,594 @@ +#ifndef ASSEMBLY + +#ifndef COREIP_U54MC_RTL__METAL_H +#define COREIP_U54MC_RTL__METAL_H + +#ifdef __METAL_MACHINE_MACROS + +#define __METAL_CLINT_NUM_PARENTS 10 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif +#define __METAL_PLIC_SUBINTERRUPTS 137 + +#define __METAL_PLIC_NUM_PARENTS 9 + +#ifndef __METAL_PLIC_SUBINTERRUPTS +#define __METAL_PLIC_SUBINTERRUPTS 0 +#endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif +#ifndef __METAL_CLIC_SUBINTERRUPTS +#define __METAL_CLIC_SUBINTERRUPTS 0 +#endif + +#else /* ! __METAL_MACHINE_MACROS */ + +#define __METAL_CLINT_2000000_INTERRUPTS 10 + +#define METAL_MAX_CLINT_INTERRUPTS 10 + +#define __METAL_CLINT_NUM_PARENTS 10 + +#define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 9 + +#define __METAL_PLIC_SUBINTERRUPTS 137 + +#define METAL_MAX_PLIC_INTERRUPTS 9 + +#define __METAL_PLIC_NUM_PARENTS 9 + +#define __METAL_CLIC_SUBINTERRUPTS 0 +#define METAL_MAX_CLIC_INTERRUPTS 0 + +#define METAL_MAX_LOCAL_EXT_INTERRUPTS 0 + +#define __METAL_GLOBAL_EXTERNAL_INTERRUPTS_INTERRUPTS 127 + +#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 127 + +#define METAL_MAX_GPIO_INTERRUPTS 0 + +#define METAL_MAX_UART_INTERRUPTS 0 + + +#include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> +#include <metal/drivers/riscv,clint0.h> +#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv,plic0.h> +#include <metal/pmp.h> +#include <metal/drivers/sifive,global-external-interrupts0.h> +#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive,fu540-c000,l2.h> + +asm (".weak __metal_dt_mem_dtim_1000000"); +struct metal_memory __metal_dt_mem_dtim_1000000; + +asm (".weak __metal_dt_mem_itim_1800000"); +struct metal_memory __metal_dt_mem_itim_1800000; + +asm (".weak __metal_dt_mem_itim_1808000"); +struct metal_memory __metal_dt_mem_itim_1808000; + +asm (".weak __metal_dt_mem_itim_1810000"); +struct metal_memory __metal_dt_mem_itim_1810000; + +asm (".weak __metal_dt_mem_itim_1818000"); +struct metal_memory __metal_dt_mem_itim_1818000; + +asm (".weak __metal_dt_mem_itim_1820000"); +struct metal_memory __metal_dt_mem_itim_1820000; + +asm (".weak __metal_dt_mem_memory_80000000"); +struct metal_memory __metal_dt_mem_memory_80000000; + +/* From clint@2000000 */ +asm (".weak __metal_dt_clint_2000000"); +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; + +/* From cpu@0 */ +asm (".weak __metal_dt_cpu_0"); +struct __metal_driver_cpu __metal_dt_cpu_0; + +/* From cpu@1 */ +asm (".weak __metal_dt_cpu_1"); +struct __metal_driver_cpu __metal_dt_cpu_1; + +/* From cpu@2 */ +asm (".weak __metal_dt_cpu_2"); +struct __metal_driver_cpu __metal_dt_cpu_2; + +/* From cpu@3 */ +asm (".weak __metal_dt_cpu_3"); +struct __metal_driver_cpu __metal_dt_cpu_3; + +/* From cpu@4 */ +asm (".weak __metal_dt_cpu_4"); +struct __metal_driver_cpu __metal_dt_cpu_4; + +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; + +asm (".weak __metal_dt_cpu_1_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller; + +asm (".weak __metal_dt_cpu_2_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller; + +asm (".weak __metal_dt_cpu_3_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller; + +asm (".weak __metal_dt_cpu_4_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller; + +/* From interrupt_controller@c000000 */ +asm (".weak __metal_dt_interrupt_controller_c000000"); +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; + +asm (".weak __metal_dt_pmp_0"); +struct metal_pmp __metal_dt_pmp_0; + +/* From global_external_interrupts */ +asm (".weak __metal_dt_global_external_interrupts"); +struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; + +/* From teststatus@4000 */ +asm (".weak __metal_dt_teststatus_4000"); +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; + +/* From cache_controller@2010000 */ +asm (".weak __metal_dt_cache_controller_2010000"); +struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000; + + +struct metal_memory __metal_dt_mem_dtim_1000000 = { + ._base_address = 16777216UL, + ._size = 8192UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1800000 = { + ._base_address = 25165824UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1808000 = { + ._base_address = 25198592UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1810000 = { + ._base_address = 25231360UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1818000 = { + ._base_address = 25264128UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1820000 = { + ._base_address = 25296896UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_memory_80000000 = { + ._base_address = 2147483648UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +/* From clint@2000000 */ +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { + .vtable = &__metal_driver_vtable_riscv_clint0, + .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable, + .control_base = 33554432UL, + .control_size = 65536UL, + .init_done = 0, + .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[1] = 7, + .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[2] = 3, + .interrupt_parents[3] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[3] = 7, + .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[4] = 3, + .interrupt_parents[5] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[5] = 7, + .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[6] = 3, + .interrupt_parents[7] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[7] = 7, + .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[8] = 3, + .interrupt_parents[9] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[9] = 7, +}; + +/* From cpu@0 */ +struct __metal_driver_cpu __metal_dt_cpu_0 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, +}; + +/* From cpu@1 */ +struct __metal_driver_cpu __metal_dt_cpu_1 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_1_interrupt_controller.controller, +}; + +/* From cpu@2 */ +struct __metal_driver_cpu __metal_dt_cpu_2 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_2_interrupt_controller.controller, +}; + +/* From cpu@3 */ +struct __metal_driver_cpu __metal_dt_cpu_3 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_3_interrupt_controller.controller, +}; + +/* From cpu@4 */ +struct __metal_driver_cpu __metal_dt_cpu_4 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_4_interrupt_controller.controller, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller@c000000 */ +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { + .vtable = &__metal_driver_vtable_riscv_plic0, + .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, + .init_done = 0, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, + .interrupt_parents[1] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[1] = 11, + .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[2] = 9, + .interrupt_parents[3] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[3] = 11, + .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[4] = 9, + .interrupt_parents[5] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[5] = 11, + .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[6] = 9, + .interrupt_parents[7] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[7] = 11, + .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[8] = 9, + .control_base = 201326592UL, + .control_size = 67108864UL, + .max_priority = 7UL, + .num_interrupts = 137UL, + .interrupt_controller = 1, +}; + +/* From pmp@0 */ +struct metal_pmp __metal_dt_pmp_0 = { + .num_regions = 8UL, +}; + +/* From global_external_interrupts */ +struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { + .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0, + .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, + .init_done = 0, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS, + .interrupt_lines[0] = 1, + .interrupt_lines[1] = 2, + .interrupt_lines[2] = 3, + .interrupt_lines[3] = 4, + .interrupt_lines[4] = 5, + .interrupt_lines[5] = 6, + .interrupt_lines[6] = 7, + .interrupt_lines[7] = 8, + .interrupt_lines[8] = 9, + .interrupt_lines[9] = 10, + .interrupt_lines[10] = 11, + .interrupt_lines[11] = 12, + .interrupt_lines[12] = 13, + .interrupt_lines[13] = 14, + .interrupt_lines[14] = 15, + .interrupt_lines[15] = 16, + .interrupt_lines[16] = 17, + .interrupt_lines[17] = 18, + .interrupt_lines[18] = 19, + .interrupt_lines[19] = 20, + .interrupt_lines[20] = 21, + .interrupt_lines[21] = 22, + .interrupt_lines[22] = 23, + .interrupt_lines[23] = 24, + .interrupt_lines[24] = 25, + .interrupt_lines[25] = 26, + .interrupt_lines[26] = 27, + .interrupt_lines[27] = 28, + .interrupt_lines[28] = 29, + .interrupt_lines[29] = 30, + .interrupt_lines[30] = 31, + .interrupt_lines[31] = 32, + .interrupt_lines[32] = 33, + .interrupt_lines[33] = 34, + .interrupt_lines[34] = 35, + .interrupt_lines[35] = 36, + .interrupt_lines[36] = 37, + .interrupt_lines[37] = 38, + .interrupt_lines[38] = 39, + .interrupt_lines[39] = 40, + .interrupt_lines[40] = 41, + .interrupt_lines[41] = 42, + .interrupt_lines[42] = 43, + .interrupt_lines[43] = 44, + .interrupt_lines[44] = 45, + .interrupt_lines[45] = 46, + .interrupt_lines[46] = 47, + .interrupt_lines[47] = 48, + .interrupt_lines[48] = 49, + .interrupt_lines[49] = 50, + .interrupt_lines[50] = 51, + .interrupt_lines[51] = 52, + .interrupt_lines[52] = 53, + .interrupt_lines[53] = 54, + .interrupt_lines[54] = 55, + .interrupt_lines[55] = 56, + .interrupt_lines[56] = 57, + .interrupt_lines[57] = 58, + .interrupt_lines[58] = 59, + .interrupt_lines[59] = 60, + .interrupt_lines[60] = 61, + .interrupt_lines[61] = 62, + .interrupt_lines[62] = 63, + .interrupt_lines[63] = 64, + .interrupt_lines[64] = 65, + .interrupt_lines[65] = 66, + .interrupt_lines[66] = 67, + .interrupt_lines[67] = 68, + .interrupt_lines[68] = 69, + .interrupt_lines[69] = 70, + .interrupt_lines[70] = 71, + .interrupt_lines[71] = 72, + .interrupt_lines[72] = 73, + .interrupt_lines[73] = 74, + .interrupt_lines[74] = 75, + .interrupt_lines[75] = 76, + .interrupt_lines[76] = 77, + .interrupt_lines[77] = 78, + .interrupt_lines[78] = 79, + .interrupt_lines[79] = 80, + .interrupt_lines[80] = 81, + .interrupt_lines[81] = 82, + .interrupt_lines[82] = 83, + .interrupt_lines[83] = 84, + .interrupt_lines[84] = 85, + .interrupt_lines[85] = 86, + .interrupt_lines[86] = 87, + .interrupt_lines[87] = 88, + .interrupt_lines[88] = 89, + .interrupt_lines[89] = 90, + .interrupt_lines[90] = 91, + .interrupt_lines[91] = 92, + .interrupt_lines[92] = 93, + .interrupt_lines[93] = 94, + .interrupt_lines[94] = 95, + .interrupt_lines[95] = 96, + .interrupt_lines[96] = 97, + .interrupt_lines[97] = 98, + .interrupt_lines[98] = 99, + .interrupt_lines[99] = 100, + .interrupt_lines[100] = 101, + .interrupt_lines[101] = 102, + .interrupt_lines[102] = 103, + .interrupt_lines[103] = 104, + .interrupt_lines[104] = 105, + .interrupt_lines[105] = 106, + .interrupt_lines[106] = 107, + .interrupt_lines[107] = 108, + .interrupt_lines[108] = 109, + .interrupt_lines[109] = 110, + .interrupt_lines[110] = 111, + .interrupt_lines[111] = 112, + .interrupt_lines[112] = 113, + .interrupt_lines[113] = 114, + .interrupt_lines[114] = 115, + .interrupt_lines[115] = 116, + .interrupt_lines[116] = 117, + .interrupt_lines[117] = 118, + .interrupt_lines[118] = 119, + .interrupt_lines[119] = 120, + .interrupt_lines[120] = 121, + .interrupt_lines[121] = 122, + .interrupt_lines[122] = 123, + .interrupt_lines[123] = 124, + .interrupt_lines[124] = 125, + .interrupt_lines[125] = 126, + .interrupt_lines[126] = 127, +}; + +/* From teststatus@4000 */ +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { + .vtable = &__metal_driver_vtable_sifive_test0, + .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown, + .base = 16384UL, + .size = 4096UL, +}; + +/* From cache_controller@2010000 */ +struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = { + .vtable = &__metal_driver_vtable_sifive_fu540_c000_l2, + .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache, +}; + + +#define __METAL_DT_MAX_MEMORIES 7 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_dtim_1000000, + &__metal_dt_mem_itim_1800000, + &__metal_dt_mem_itim_1808000, + &__metal_dt_mem_itim_1810000, + &__metal_dt_mem_itim_1818000, + &__metal_dt_mem_itim_1820000, + &__metal_dt_mem_memory_80000000}; + +/* From clint@2000000 */ +#define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) + +#define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) + +#define __METAL_DT_MAX_HARTS 5 + +asm (".weak __metal_cpu_table"); +struct __metal_driver_cpu *__metal_cpu_table[] = { + &__metal_dt_cpu_0, + &__metal_dt_cpu_1, + &__metal_dt_cpu_2, + &__metal_dt_cpu_3, + &__metal_dt_cpu_4}; + +/* From interrupt_controller@c000000 */ +#define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +/* From pmp@0 */ +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) + +/* From global_external_interrupts */ +#define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) + +#define __METAL_DT_GLOBAL_EXTERNAL_INTERRUPTS_HANDLE (&__metal_dt_global_external_interrupts.irc) + +#define __MEE_DT_MAX_GPIOS 0 + +asm (".weak __metal_gpio_table"); +struct __metal_driver_sifive_gpio0 *__metal_gpio_table[] = { + NULL }; +#define __METAL_DT_MAX_BUTTONS 0 + +asm (".weak __metal_button_table"); +struct __metal_driver_sifive_gpio_button *__metal_button_table[] = { + NULL }; +#define __METAL_DT_MAX_LEDS 0 + +asm (".weak __metal_led_table"); +struct __metal_driver_sifive_gpio_led *__metal_led_table[] = { + NULL }; +#define __METAL_DT_MAX_SWITCHES 0 + +asm (".weak __metal_switch_table"); +struct __metal_driver_sifive_gpio_switch *__metal_switch_table[] = { + NULL }; +#define __METAL_DT_MAX_SPIS 0 + +asm (".weak __metal_spi_table"); +struct __metal_driver_sifive_spi0 *__metal_spi_table[] = { + NULL }; +/* From teststatus@4000 */ +#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_teststatus_4000.shutdown) + +#define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown) + + +#endif /* ! __METAL_MACHINE_MACROS */ +#endif /* COREIP_U54MC_RTL__METAL_H*/ +#endif /* ! ASSEMBLY */ diff --git a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds new file mode 100644 index 0000000..7b1cf8e --- /dev/null +++ b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds @@ -0,0 +1,227 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_LOAD; + itim PT_LOAD; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >ram AT>ram :ram + + + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >ram AT>ram :ram + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >ram AT>ram :ram + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>ram :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>ram :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >ram AT>ram :ram + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>ram :ram_init + + + .data : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + . = __stack_size; + . = __stack_size; + . = __stack_size; + . = __stack_size; + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds new file mode 100644 index 0000000..0d12f67 --- /dev/null +++ b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds @@ -0,0 +1,230 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x20000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_LOAD; + itim PT_LOAD; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >ram AT>ram :ram + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >ram AT>ram :ram + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >ram AT>ram :ram + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >ram AT>ram :ram + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>ram :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>ram :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >ram AT>ram :ram + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>ram :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + . = __stack_size; + . = __stack_size; + . = __stack_size; + . = __stack_size; + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk new file mode 100644 index 0000000..0fe5f84 --- /dev/null +++ b/bsp/coreip-u54mc-rtl/settings.mk @@ -0,0 +1,7 @@ +RISCV_ARCH=rv64imac +RISCV_ABI=lp64 +RISCV_CMODEL=medany + +COREIP_MEM_WIDTH=128 + +TARGET_TAGS=rtl diff --git a/bsp/freedom-e310-arty/metal.default.lds b/bsp/freedom-e310-arty/metal.default.lds index 815b31b..4b90f06 100644 --- a/bsp/freedom-e310-arty/metal.default.lds +++ b/bsp/freedom-e310-arty/metal.default.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/freedom-e310-arty/metal.h b/bsp/freedom-e310-arty/metal.h index 2eb644c..16f2d53 100644 --- a/bsp/freedom-e310-arty/metal.h +++ b/bsp/freedom-e310-arty/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 27 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 27 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -45,6 +59,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -58,6 +73,15 @@ asm (".weak __metal_dt_clock_0"); struct __metal_driver_fixed_clock __metal_dt_clock_0; +asm (".weak __metal_dt_mem_dtim_80000000"); +struct metal_memory __metal_dt_mem_dtim_80000000; + +asm (".weak __metal_dt_mem_itim_8000000"); +struct metal_memory __metal_dt_mem_itim_8000000; + +asm (".weak __metal_dt_mem_spi_10014000"); +struct metal_memory __metal_dt_mem_spi_10014000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -66,9 +90,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -98,6 +121,39 @@ struct __metal_driver_fixed_clock __metal_dt_clock_0 = { .rate = 65000000UL, }; +struct metal_memory __metal_dt_mem_dtim_80000000 = { + ._base_address = 2147483648UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_8000000 = { + ._base_address = 134217728UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_10014000 = { + ._base_address = 536870912UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -106,8 +162,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -116,11 +173,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -132,9 +189,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -147,8 +203,7 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, .interrupt_lines[0] = 16, .interrupt_lines[1] = 17, @@ -224,6 +279,14 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = { }; +#define __METAL_DT_MAX_MEMORIES 3 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_dtim_80000000, + &__metal_dt_mem_itim_8000000, + &__metal_dt_mem_spi_10014000}; + /* From serial@10013000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_10013000.uart) @@ -236,22 +299,12 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = { #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/freedom-e310-arty/metal.ramrodata.lds b/bsp/freedom-e310-arty/metal.ramrodata.lds index 9d535aa..b24d83f 100644 --- a/bsp/freedom-e310-arty/metal.ramrodata.lds +++ b/bsp/freedom-e310-arty/metal.ramrodata.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/freedom-e310-arty/metal.scratchpad.lds b/bsp/freedom-e310-arty/metal.scratchpad.lds index 89a39b9..711bc3c 100644 --- a/bsp/freedom-e310-arty/metal.scratchpad.lds +++ b/bsp/freedom-e310-arty/metal.scratchpad.lds @@ -21,6 +21,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/sifive-hifive-unleashed/README.md b/bsp/sifive-hifive-unleashed/README.md new file mode 100644 index 0000000..1349a86 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/README.md @@ -0,0 +1,19 @@ +# SiFive HiFive Unleashed + +The SiFive HiFive Unleashed features an FU540-C000 SoC with the U54-MC Core IP. + +## Configuring MSEL + +The mode select switches should be set as follows: +``` + USB LED Mode Select Ethernet + +===|___|==****==+-+-+-+-+-+-+=================|******|===+ + | | | | |X|X|X| | | | + | | | | | | | | | | | + | HFXSEL->|X|X|X| | | | |______| | + | +-+-+-+-+-+-+ | + | RTCSEL-----/ 0 1 2 3 <--MSEL | + | | +``` + +This will cause the board to boot from the SPI flash at 0x2000\_0000. diff --git a/bsp/sifive-hifive-unleashed/design.dts b/bsp/sifive-hifive-unleashed/design.dts new file mode 100644 index 0000000..ee6897f --- /dev/null +++ b/bsp/sifive-hifive-unleashed/design.dts @@ -0,0 +1,627 @@ +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540g", "sifive,fu500"; + model = "sifive,hifive-unleashed-a00"; + + aliases { + serial0 = &L28; + serial1 = &L29; + }; + + chosen { + stdout-path = "/soc/serial@10010000:115200"; + }; + + firmware { + sifive,fsbl = "YYYY-MM-DD"; + }; + + L3: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L9: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&L24 &L0>; + reg = <0>; + riscv,isa = "rv64imac"; + sifive,dtim = <&L8>; + sifive,itim = <&L7>; + status = "okay"; + L10: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L12: cpu@1 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <1>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L11>; + status = "okay"; + tlb-split; + L13: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L15: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <2>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L14>; + status = "okay"; + tlb-split; + L16: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L18: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <3>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L17>; + status = "okay"; + tlb-split; + L19: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L21: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <4>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L20>; + status = "okay"; + tlb-split; + L22: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L36: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1f 0x80000000>; + }; + L2: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus"; + ranges; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <1>; + }; + refclk: refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "xtal"; + }; + prci: prci@10000000 { + compatible = "sifive,ux00prci0"; + reg = <0x0 0x10000000 0x0 0x1000>; + reg-names = "control"; + clocks = <&refclk>; + #clock-cells = <1>; + }; + tlclk: tlclk { + compatible = "fixed-factor-clock"; + clocks = <&refclk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + L51: cadence-gemgxl-mgmt@100a0000 { + compatible = "sifive,cadencegemgxlmgmt0"; + reg = <0x0 0x100a0000 0x0 0x1000>; + reg-names = "control"; + #clock-cells = <0>; + }; + L35: bus-blocker@100b8000 { + compatible = "sifive,bus-blocker0"; + reg = <0x0 0x100b8000 0x0 0x1000>; + reg-names = "control"; + }; + L0: cache-controller@2010000 { + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + compatible = "sifive,ccache0", "cache"; + interrupt-parent = <&L4>; + interrupts = <1 2 3>; + next-level-cache = <&L25 &L40 &L36>; + reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; + reg-names = "control", "sideband"; + }; + L33: cadence-ddr-mgmt@100c0000 { + compatible = "sifive,cadenceddrmgmt0"; + reg = <0x0 0x100c0000 0x0 0x1000>; + reg-names = "control"; + }; + L40: chiplink@40000000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,chiplink", "simple-bus"; + ranges = <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000 0x30 0x0 0x30 0x0 0x10 0x0 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x20 0x0 0x20 0x0 0x10 0x0>; + }; + L5: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L10 3 &L10 7 &L13 3 &L13 7 &L16 3 &L16 7 &L19 3 &L19 7 &L22 3 &L22 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + reg-names = "control"; + }; + L6: debug-controller@0 { + compatible = "sifive,debug-013", "riscv,debug-013"; + interrupts-extended = <&L10 65535 &L13 65535 &L16 65535 &L19 65535 &L22 65535>; + reg = <0x0 0x0 0x0 0x1000>; + reg-names = "control"; + }; + L32: dma@3000000 { + #dma-cells = <1>; + compatible = "riscv,dma0"; + dma-channels = <4>; + dma-requests = <0>; + interrupt-parent = <&L4>; + interrupts = <23 24 25 26 27 28 29 30>; + reg = <0x0 0x3000000 0x0 0x100000>; + reg-names = "control"; + riscv,dma-pools = <1>; + }; + L8: dtim@1000000 { + compatible = "sifive,dtim0"; + reg = <0x0 0x1000000 0x0 0x2000>; + reg-names = "mem"; + }; + L44: ememoryotp@10070000 { + compatible = "sifive,ememoryotp0"; + reg = <0x0 0x10070000 0x0 0x1000>; + reg-names = "control"; + }; + L24: error-device@18000000 { + compatible = "sifive,error0"; + reg = <0x0 0x18000000 0x0 0x8000000>; + reg-names = "mem"; + }; + L52: ethernet@10090000 { + compatible = "cdns,macb"; + interrupt-parent = <&L4>; + interrupts = <53>; + reg = <0x0 0x10090000 0x0 0x2000>; + reg-names = "control"; + + local-mac-address = [00 00 00 00 00 00]; + phy-mode = "gmii"; + clock-names = "pclk", "hclk", "tx_clk"; + clocks = <&prci 1>, <&prci 1>, <&L51>; + + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@0 { + reg = <0>; + reset-gpios = <&L31 12 1>; + }; + }; + L31: gpio@10060000 { + compatible = "sifive,gpio0"; + interrupt-parent = <&L4>; + interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; + reg = <0x0 0x10060000 0x0 0x1000>; + reg-names = "control"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpio-restart { + compatible = "gpio-restart"; + gpios = <&L31 10 1>; + }; + L47: i2c@10030000 { + compatible = "sifive,i2c0", "opencores,i2c-ocores"; + reg = <0x0 0x10030000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + + reg-shift = <2>; + reg-io-width = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + /* On pre-production boards only */ +/* + ina233-vdd_soc_core@40 { + compatible = "ti,pmbus"; + reg = <0x40>; + }; + ina233-vdd_ddr_soc@44 { + compatible = "ti,pmbus"; + reg = <0x44>; + }; + ina233-vdd_ddr_mem@45 { + compatible = "ti,pmbus"; + reg = <0x45>; + }; + ina233-vdd_corepll@47 { + compatible = "ti,pmbus"; + reg = <0x47>; + }; + ina233-vdd_otp@4a { + compatible = "ti,pmbus"; + reg = <0x4a>; + }; + ina233-vdd_io@4b { + compatible = "ti,pmbus"; + reg = <0x4b>; + }; + ina233-vdd_ddrpll@48 { + compatible = "ti,pmbus"; + reg = <0x48>; + }; + ina233-avdd_ddrpll@49 { + compatible = "ti,pmbus"; + reg = <0x49>; + }; + ina233-vdd_givdd@4c { + compatible = "ti,pmbus"; + reg = <0x4c>; + }; + ina233vdd_gemgxlpll@4d { + compatible = "ti,pmbus"; + reg = <0x4d>; + }; +*/ + /* On the tester board */ +/* + m24c02 { + compatible = "st,24c02"; + reg = <0x51>; + }; +*/ + }; + L4: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L10 11 &L13 11 &L13 9 &L16 11 &L16 9 &L19 11 &L19 9 &L22 11 &L22 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <53>; + }; + L7: itim@1800000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1800000 0x0 0x4000>; + reg-names = "mem"; + }; + L11: itim@1808000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1808000 0x0 0x8000>; + reg-names = "mem"; + }; + L14: itim@1810000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1810000 0x0 0x8000>; + reg-names = "mem"; + }; + L17: itim@1818000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1818000 0x0 0x8000>; + reg-names = "mem"; + }; + L20: itim@1820000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1820000 0x0 0x8000>; + reg-names = "mem"; + }; + L37: memory-controller@100b0000 { + compatible = "sifive,ux00ddr0"; + interrupt-parent = <&L4>; + interrupts = <31>; + reg = <0x0 0x100b0000 0x0 0x4000>; + reg-names = "control"; + }; + pci@2000000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + interrupt-map = <0 0 0 1 &xil_pcie_intc 1 0 0 0 2 &xil_pcie_intc 2 0 0 0 3 &xil_pcie_intc 3 0 0 0 4 &xil_pcie_intc 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&L4>; + interrupts = <32>; + ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; + reg = <0x020 0x0 0x0 0x4000000>; + reg-names = "control"; + xil_pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + pci@2030000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "ms-pf,axi-pcie-host"; + device_type = "pci"; + bus-range = <0x01 0x7f>; + interrupt-map = <0 0 0 1 &ms_pcie_intc 1 0 0 0 2 &ms_pcie_intc 2 0 0 0 3 &ms_pcie_intc 3 0 0 0 4 &ms_pcie_intc 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&L4>; + interrupts = <32>; + ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; + reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>; + reg-names = "control", "apb"; + ms_pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + L53: pinctrl@10080000 { + compatible = "sifive,pinctrl0"; + reg = <0x0 0x10080000 0x0 0x1000>; + reg-names = "control"; + }; + L45: pwm@10020000 { + compatible = "sifive,pwm0"; + interrupt-parent = <&L4>; + interrupts = <42 43 44 45>; + reg = <0x0 0x10020000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + sifive,approx-period = <1000000>; + #pwm-cells = <2>; + }; + L46: pwm@10021000 { + compatible = "sifive,pwm0"; + interrupt-parent = <&L4>; + interrupts = <46 47 48 49>; + reg = <0x0 0x10021000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + sifive,approx-period = <1000000>; + #pwm-cells = <2>; + }; + pwmleds { + compatible = "pwm-leds"; + heartbeat { + pwms = <&L45 0 0>; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + mtd { + pwms = <&L45 1 0>; + max-brightness = <255>; + linux,default-trigger = "mtd"; + }; + netdev { + pwms = <&L45 2 0>; + max-brightness = <255>; + linux,default-trigger = "netdev"; + }; + panic { + pwms = <&L45 3 0>; + max-brightness = <255>; + linux,default-trigger = "panic"; + }; + /* These LEDs are on the tester board */ +/* + testled { + pwms = <&L46 0 0>; + max-brightness = <255>; + }; + green { + pwms = <&L46 1 0>; + max-brightness = <255>; + }; + red { + pwms = <&L46 2 0>; + max-brightness = <255>; + }; + blue { + pwms = <&L46 3 0>; + max-brightness = <255>; + }; +*/ + }; + L27: rom@1000 { + compatible = "sifive,modeselect0"; + reg = <0x0 0x1000 0x0 0x1000>; + reg-names = "mem"; + }; + L26: rom@10000 { + compatible = "sifive,maskrom0"; + reg = <0x0 0x10000 0x0 0x8000>; + reg-names = "mem"; + }; + L25: rom@a000000 { + compatible = "ucbbar,cacheable-zero0"; + reg = <0x0 0xa000000 0x0 0x2000000>; + reg-names = "mem"; + }; + L28: serial@10010000 { + compatible = "sifive,uart0"; + interrupt-parent = <&L4>; + interrupts = <4>; + reg = <0x0 0x10010000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + }; + L29: serial@10011000 { + compatible = "sifive,uart0"; + interrupt-parent = <&L4>; + interrupts = <5>; + reg = <0x0 0x10011000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + }; + L49: spi@10040000 { + compatible = "sifive,spi0"; + interrupt-parent = <&L4>; + interrupts = <51>; + reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>; + reg-names = "control", "mem"; + clocks = <&tlclk>; + + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "issi,is25wp256d", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + L50: spi@10041000 { + compatible = "sifive,spi0"; + interrupt-parent = <&L4>; + interrupts = <52>; + reg = <0x0 0x10041000 0x0 0x1000 0x0 0x30000000 0x0 0x10000000>; + reg-names = "control", "mem"; + clocks = <&tlclk>; + + #address-cells = <1>; + #size-cells = <0>; + + /* These flash chips are on the tester board */ +/* + flash@0 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + flash@1 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + flash@2 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + flash@3 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <3>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +*/ + }; + L30: spi@10050000 { + compatible = "sifive,spi0"; + interrupt-parent = <&L4>; + interrupts = <6>; + reg = <0x0 0x10050000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + + #address-cells = <1>; + #size-cells = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + gpios = <&L31 11 1>; + }; + }; + L23: teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x0 0x4000 0x0 0x1000>; + reg-names = "control"; + }; + }; +}; diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds new file mode 100644 index 0000000..61b2203 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/metal.default.lds @@ -0,0 +1,231 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x80000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 + flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 0x10000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_NULL; + itim PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >flash AT>flash :flash + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >flash AT>flash :flash + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>flash :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>flash :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >flash AT>flash :flash + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>flash :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + . = __stack_size; + . = __stack_size; + . = __stack_size; + . = __stack_size; + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/sifive-hifive-unleashed/metal.h b/bsp/sifive-hifive-unleashed/metal.h new file mode 100644 index 0000000..b7a329b --- /dev/null +++ b/bsp/sifive-hifive-unleashed/metal.h @@ -0,0 +1,647 @@ +#ifndef ASSEMBLY + +#ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_H +#define SIFIVE_HIFIVE_UNLEASHED__METAL_H + +#ifdef __METAL_MACHINE_MACROS + +#define __METAL_CLINT_NUM_PARENTS 10 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif +#define __METAL_PLIC_SUBINTERRUPTS 54 + +#define __METAL_PLIC_NUM_PARENTS 9 + +#ifndef __METAL_PLIC_SUBINTERRUPTS +#define __METAL_PLIC_SUBINTERRUPTS 0 +#endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif +#ifndef __METAL_CLIC_SUBINTERRUPTS +#define __METAL_CLIC_SUBINTERRUPTS 0 +#endif + +#else /* ! __METAL_MACHINE_MACROS */ + +#define __METAL_CLINT_2000000_INTERRUPTS 10 + +#define METAL_MAX_CLINT_INTERRUPTS 10 + +#define __METAL_CLINT_NUM_PARENTS 10 + +#define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 9 + +#define __METAL_PLIC_SUBINTERRUPTS 54 + +#define METAL_MAX_PLIC_INTERRUPTS 9 + +#define __METAL_PLIC_NUM_PARENTS 9 + +#define __METAL_CLIC_SUBINTERRUPTS 0 +#define METAL_MAX_CLIC_INTERRUPTS 0 + +#define METAL_MAX_LOCAL_EXT_INTERRUPTS 0 + +#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 0 + +#define __METAL_GPIO_10060000_INTERRUPTS 16 + +#define METAL_MAX_GPIO_INTERRUPTS 16 + +#define __METAL_SERIAL_10010000_INTERRUPTS 1 + +#define __METAL_SERIAL_10011000_INTERRUPTS 1 + +#define METAL_MAX_UART_INTERRUPTS 1 + + +#include <metal/drivers/fixed-clock.h> +#include <metal/drivers/fixed-factor-clock.h> +#include <metal/memory.h> +#include <metal/drivers/riscv,clint0.h> +#include <metal/drivers/riscv,cpu.h> +#include <metal/drivers/riscv,plic0.h> +#include <metal/pmp.h> +#include <metal/drivers/sifive,gpio0.h> +#include <metal/drivers/sifive,spi0.h> +#include <metal/drivers/sifive,test0.h> +#include <metal/drivers/sifive,uart0.h> +#include <metal/drivers/sifive,fu540-c000,l2.h> + +/* From refclk */ +asm (".weak __metal_dt_refclk"); +struct __metal_driver_fixed_clock __metal_dt_refclk; + +/* From tlclk */ +asm (".weak __metal_dt_tlclk"); +struct __metal_driver_fixed_factor_clock __metal_dt_tlclk; + +asm (".weak __metal_dt_mem_dtim_1000000"); +struct metal_memory __metal_dt_mem_dtim_1000000; + +asm (".weak __metal_dt_mem_itim_1800000"); +struct metal_memory __metal_dt_mem_itim_1800000; + +asm (".weak __metal_dt_mem_itim_1808000"); +struct metal_memory __metal_dt_mem_itim_1808000; + +asm (".weak __metal_dt_mem_itim_1810000"); +struct metal_memory __metal_dt_mem_itim_1810000; + +asm (".weak __metal_dt_mem_itim_1818000"); +struct metal_memory __metal_dt_mem_itim_1818000; + +asm (".weak __metal_dt_mem_itim_1820000"); +struct metal_memory __metal_dt_mem_itim_1820000; + +asm (".weak __metal_dt_mem_memory_80000000"); +struct metal_memory __metal_dt_mem_memory_80000000; + +asm (".weak __metal_dt_mem_spi_10040000"); +struct metal_memory __metal_dt_mem_spi_10040000; + +asm (".weak __metal_dt_mem_spi_10041000"); +struct metal_memory __metal_dt_mem_spi_10041000; + +asm (".weak __metal_dt_mem_spi_10050000"); +struct metal_memory __metal_dt_mem_spi_10050000; + +/* From clint@2000000 */ +asm (".weak __metal_dt_clint_2000000"); +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; + +/* From cpu@0 */ +asm (".weak __metal_dt_cpu_0"); +struct __metal_driver_cpu __metal_dt_cpu_0; + +/* From cpu@1 */ +asm (".weak __metal_dt_cpu_1"); +struct __metal_driver_cpu __metal_dt_cpu_1; + +/* From cpu@2 */ +asm (".weak __metal_dt_cpu_2"); +struct __metal_driver_cpu __metal_dt_cpu_2; + +/* From cpu@3 */ +asm (".weak __metal_dt_cpu_3"); +struct __metal_driver_cpu __metal_dt_cpu_3; + +/* From cpu@4 */ +asm (".weak __metal_dt_cpu_4"); +struct __metal_driver_cpu __metal_dt_cpu_4; + +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; + +asm (".weak __metal_dt_cpu_1_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller; + +asm (".weak __metal_dt_cpu_2_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller; + +asm (".weak __metal_dt_cpu_3_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller; + +asm (".weak __metal_dt_cpu_4_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller; + +/* From interrupt_controller@c000000 */ +asm (".weak __metal_dt_interrupt_controller_c000000"); +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; + +asm (".weak __metal_dt_pmp_0"); +struct metal_pmp __metal_dt_pmp_0; + +/* From gpio@10060000 */ +asm (".weak __metal_dt_gpio_10060000"); +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000; + +/* From spi@10040000 */ +asm (".weak __metal_dt_spi_10040000"); +struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000; + +/* From spi@10041000 */ +asm (".weak __metal_dt_spi_10041000"); +struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000; + +/* From spi@10050000 */ +asm (".weak __metal_dt_spi_10050000"); +struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000; + +/* From teststatus@4000 */ +asm (".weak __metal_dt_teststatus_4000"); +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; + +/* From serial@10010000 */ +asm (".weak __metal_dt_serial_10010000"); +struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000; + +/* From serial@10011000 */ +asm (".weak __metal_dt_serial_10011000"); +struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000; + +/* From cache_controller@2010000 */ +asm (".weak __metal_dt_cache_controller_2010000"); +struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000; + + +/* From refclk */ +struct __metal_driver_fixed_clock __metal_dt_refclk = { + .vtable = &__metal_driver_vtable_fixed_clock, + .clock.vtable = &__metal_driver_vtable_fixed_clock.clock, + .rate = 33333333UL, +}; + +/* From tlclk */ +struct __metal_driver_fixed_factor_clock __metal_dt_tlclk = { + .vtable = &__metal_driver_vtable_fixed_factor_clock, + .clock.vtable = &__metal_driver_vtable_fixed_factor_clock.clock, +/* From refclk */ + .parent = &__metal_dt_refclk.clock, + .mult = 1, + .div = 2, +}; + +struct metal_memory __metal_dt_mem_dtim_1000000 = { + ._base_address = 16777216UL, + ._size = 8192UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1800000 = { + ._base_address = 25165824UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1808000 = { + ._base_address = 25198592UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1810000 = { + ._base_address = 25231360UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1818000 = { + ._base_address = 25264128UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1820000 = { + ._base_address = 25296896UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_memory_80000000 = { + ._base_address = 2147483648UL, + ._size = 135291469824UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_10040000 = { + ._base_address = 536870912UL, + ._size = 268435456UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_10041000 = { + ._base_address = 805306368UL, + ._size = 268435456UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_10050000 = { + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +/* From clint@2000000 */ +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { + .vtable = &__metal_driver_vtable_riscv_clint0, + .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable, + .control_base = 33554432UL, + .control_size = 65536UL, + .init_done = 0, + .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[1] = 7, + .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[2] = 3, + .interrupt_parents[3] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[3] = 7, + .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[4] = 3, + .interrupt_parents[5] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[5] = 7, + .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[6] = 3, + .interrupt_parents[7] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[7] = 7, + .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[8] = 3, + .interrupt_parents[9] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[9] = 7, +}; + +/* From cpu@0 */ +struct __metal_driver_cpu __metal_dt_cpu_0 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, +}; + +/* From cpu@1 */ +struct __metal_driver_cpu __metal_dt_cpu_1 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_1_interrupt_controller.controller, +}; + +/* From cpu@2 */ +struct __metal_driver_cpu __metal_dt_cpu_2 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_2_interrupt_controller.controller, +}; + +/* From cpu@3 */ +struct __metal_driver_cpu __metal_dt_cpu_3 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_3_interrupt_controller.controller, +}; + +/* From cpu@4 */ +struct __metal_driver_cpu __metal_dt_cpu_4 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_4_interrupt_controller.controller, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller@c000000 */ +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { + .vtable = &__metal_driver_vtable_riscv_plic0, + .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, + .init_done = 0, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, + .interrupt_parents[1] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[1] = 11, + .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[2] = 9, + .interrupt_parents[3] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[3] = 11, + .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[4] = 9, + .interrupt_parents[5] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[5] = 11, + .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[6] = 9, + .interrupt_parents[7] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[7] = 11, + .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[8] = 9, + .control_base = 201326592UL, + .control_size = 67108864UL, + .max_priority = 7UL, + .num_interrupts = 54UL, + .interrupt_controller = 1, +}; + +/* From pmp@0 */ +struct metal_pmp __metal_dt_pmp_0 = { + .num_regions = 1UL, +}; + +/* From gpio@10060000 */ +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = { + .vtable = &__metal_driver_vtable_sifive_gpio0, + .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio, + .base = 268828672UL, + .size = 4096UL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_GPIO_INTERRUPTS, + .interrupt_lines[0] = 7, + .interrupt_lines[1] = 8, + .interrupt_lines[2] = 9, + .interrupt_lines[3] = 10, + .interrupt_lines[4] = 11, + .interrupt_lines[5] = 12, + .interrupt_lines[6] = 13, + .interrupt_lines[7] = 14, + .interrupt_lines[8] = 15, + .interrupt_lines[9] = 16, + .interrupt_lines[10] = 17, + .interrupt_lines[11] = 18, + .interrupt_lines[12] = 19, + .interrupt_lines[13] = 20, + .interrupt_lines[14] = 21, + .interrupt_lines[15] = 22, +}; + +/* From spi@10040000 */ +struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = { + .vtable = &__metal_driver_vtable_sifive_spi0, + .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, + .control_base = 268697600UL, + .control_size = 4096UL, +/* From tlclk */ + .clock = &__metal_dt_tlclk.clock, + .pinmux = NULL, +}; + +/* From spi@10041000 */ +struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = { + .vtable = &__metal_driver_vtable_sifive_spi0, + .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, + .control_base = 268701696UL, + .control_size = 4096UL, +/* From tlclk */ + .clock = &__metal_dt_tlclk.clock, + .pinmux = NULL, +}; + +/* From spi@10050000 */ +struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000 = { + .vtable = &__metal_driver_vtable_sifive_spi0, + .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, + .control_base = 268763136UL, + .control_size = 4096UL, +/* From tlclk */ + .clock = &__metal_dt_tlclk.clock, + .pinmux = NULL, +}; + +/* From teststatus@4000 */ +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { + .vtable = &__metal_driver_vtable_sifive_test0, + .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown, + .base = 16384UL, + .size = 4096UL, +}; + +/* From serial@10010000 */ +struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = { + .vtable = &__metal_driver_vtable_sifive_uart0, + .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, + .control_base = 268500992UL, + .control_size = 4096UL, +/* From tlclk */ + .clock = &__metal_dt_tlclk.clock, + .pinmux = NULL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_UART_INTERRUPTS, + .interrupt_line = 4UL, +}; + +/* From serial@10011000 */ +struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000 = { + .vtable = &__metal_driver_vtable_sifive_uart0, + .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, + .control_base = 268505088UL, + .control_size = 4096UL, +/* From tlclk */ + .clock = &__metal_dt_tlclk.clock, + .pinmux = NULL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_UART_INTERRUPTS, + .interrupt_line = 5UL, +}; + +/* From cache_controller@2010000 */ +struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = { + .vtable = &__metal_driver_vtable_sifive_fu540_c000_l2, + .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache, +}; + + +#define __METAL_DT_MAX_MEMORIES 9 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_dtim_1000000, + &__metal_dt_mem_itim_1800000, + &__metal_dt_mem_itim_1808000, + &__metal_dt_mem_itim_1810000, + &__metal_dt_mem_itim_1818000, + &__metal_dt_mem_itim_1820000, + &__metal_dt_mem_memory_80000000, + &__metal_dt_mem_spi_10040000, + &__metal_dt_mem_spi_10041000}; + +/* From serial@10010000 */ +#define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_10010000.uart) + +#define __METAL_DT_SERIAL_10010000_HANDLE (&__metal_dt_serial_10010000.uart) + +#define __METAL_DT_STDOUT_UART_BAUD 115200 + +/* From clint@2000000 */ +#define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) + +#define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) + +#define __METAL_DT_MAX_HARTS 5 + +asm (".weak __metal_cpu_table"); +struct __metal_driver_cpu *__metal_cpu_table[] = { + &__metal_dt_cpu_0, + &__metal_dt_cpu_1, + &__metal_dt_cpu_2, + &__metal_dt_cpu_3, + &__metal_dt_cpu_4}; + +/* From interrupt_controller@c000000 */ +#define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +/* From pmp@0 */ +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) + +#define __MEE_DT_MAX_GPIOS 1 + +asm (".weak __metal_gpio_table"); +struct __metal_driver_sifive_gpio0 *__metal_gpio_table[] = { + &__metal_dt_gpio_10060000}; + +#define __METAL_DT_MAX_BUTTONS 0 + +asm (".weak __metal_button_table"); +struct __metal_driver_sifive_gpio_button *__metal_button_table[] = { + NULL }; +#define __METAL_DT_MAX_LEDS 0 + +asm (".weak __metal_led_table"); +struct __metal_driver_sifive_gpio_led *__metal_led_table[] = { + NULL }; +#define __METAL_DT_MAX_SWITCHES 0 + +asm (".weak __metal_switch_table"); +struct __metal_driver_sifive_gpio_switch *__metal_switch_table[] = { + NULL }; +#define __METAL_DT_MAX_SPIS 3 + +asm (".weak __metal_spi_table"); +struct __metal_driver_sifive_spi0 *__metal_spi_table[] = { + &__metal_dt_spi_10040000, + &__metal_dt_spi_10041000, + &__metal_dt_spi_10050000}; + +/* From teststatus@4000 */ +#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_teststatus_4000.shutdown) + +#define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown) + + +#endif /* ! __METAL_MACHINE_MACROS */ +#endif /* SIFIVE_HIFIVE_UNLEASHED__METAL_H*/ +#endif /* ! ASSEMBLY */ diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds new file mode 100644 index 0000000..b57aaf7 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds @@ -0,0 +1,228 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x80000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 + flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 0x10000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_NULL; + itim PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >flash AT>flash :flash + + + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >flash AT>flash :flash + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>flash :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>flash :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >flash AT>flash :flash + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>flash :ram_init + + + .data : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + . = __stack_size; + . = __stack_size; + . = __stack_size; + . = __stack_size; + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds new file mode 100644 index 0000000..f145bc7 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds @@ -0,0 +1,231 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x80000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 + flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 0x10000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_LOAD; + itim PT_LOAD; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >ram AT>ram :ram + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >ram AT>ram :ram + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >ram AT>ram :ram + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >ram AT>ram :ram + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>ram :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>ram :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >ram AT>ram :ram + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>ram :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + . = __stack_size; + . = __stack_size; + . = __stack_size; + . = __stack_size; + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/sifive-hifive-unleashed/openocd.cfg b/bsp/sifive-hifive-unleashed/openocd.cfg new file mode 100644 index 0000000..7589897 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/openocd.cfg @@ -0,0 +1,24 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME 0x10040000 +init +halt + +# Uncomment this if you want to be able to clobber your SPI Flash, which +# probably you don't since you can do it through Linux + +# flash protect 0 0 last off diff --git a/bsp/sifive-hifive-unleashed/settings.mk b/bsp/sifive-hifive-unleashed/settings.mk new file mode 100644 index 0000000..38a72d6 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/settings.mk @@ -0,0 +1,5 @@ +RISCV_ARCH=rv64imac +RISCV_ABI=lp64 +RISCV_CMODEL=medany + +TARGET_TAGS=board openocd diff --git a/bsp/sifive-hifive1-revb/metal.default.lds b/bsp/sifive-hifive1-revb/metal.default.lds index 878e09e..7a08d34 100644 --- a/bsp/sifive-hifive1-revb/metal.default.lds +++ b/bsp/sifive-hifive1-revb/metal.default.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/sifive-hifive1-revb/metal.h b/bsp/sifive-hifive1-revb/metal.h index 83ac0e1..a5d90e5 100644 --- a/bsp/sifive-hifive1-revb/metal.h +++ b/bsp/sifive-hifive1-revb/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 27 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 27 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -45,6 +59,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -70,6 +85,12 @@ struct __metal_driver_fixed_clock __metal_dt_clock_2; asm (".weak __metal_dt_clock_5"); struct __metal_driver_fixed_clock __metal_dt_clock_5; +asm (".weak __metal_dt_mem_dtim_80000000"); +struct metal_memory __metal_dt_mem_dtim_80000000; + +asm (".weak __metal_dt_mem_spi_10014000"); +struct metal_memory __metal_dt_mem_spi_10014000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -78,9 +99,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -143,6 +163,28 @@ struct __metal_driver_fixed_clock __metal_dt_clock_5 = { .rate = 32000000UL, }; +struct metal_memory __metal_dt_mem_dtim_80000000 = { + ._base_address = 2147483648UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_10014000 = { + ._base_address = 536870912UL, + ._size = 500000UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -151,8 +193,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -161,11 +204,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -177,9 +220,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -197,8 +239,7 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, .interrupt_lines[0] = 16, .interrupt_lines[1] = 17, @@ -324,6 +365,13 @@ struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = { }; +#define __METAL_DT_MAX_MEMORIES 2 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_dtim_80000000, + &__metal_dt_mem_spi_10014000}; + /* From serial@10013000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_10013000.uart) @@ -336,22 +384,12 @@ struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = { #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/sifive-hifive1-revb/metal.ramrodata.lds b/bsp/sifive-hifive1-revb/metal.ramrodata.lds index 5f7b6d3..cf49d3b 100644 --- a/bsp/sifive-hifive1-revb/metal.ramrodata.lds +++ b/bsp/sifive-hifive1-revb/metal.ramrodata.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/sifive-hifive1-revb/metal.scratchpad.lds b/bsp/sifive-hifive1-revb/metal.scratchpad.lds index 416f203..8ab46ed 100644 --- a/bsp/sifive-hifive1-revb/metal.scratchpad.lds +++ b/bsp/sifive-hifive1-revb/metal.scratchpad.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/sifive-hifive1/metal.default.lds b/bsp/sifive-hifive1/metal.default.lds index a656a41..3c68d7d 100644 --- a/bsp/sifive-hifive1/metal.default.lds +++ b/bsp/sifive-hifive1/metal.default.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -217,7 +218,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/sifive-hifive1/metal.h b/bsp/sifive-hifive1/metal.h index 0b5941f..422bdf1 100644 --- a/bsp/sifive-hifive1/metal.h +++ b/bsp/sifive-hifive1/metal.h @@ -5,11 +5,21 @@ #ifdef __METAL_MACHINE_MACROS +#define __METAL_CLINT_NUM_PARENTS 2 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif #define __METAL_PLIC_SUBINTERRUPTS 27 +#define __METAL_PLIC_NUM_PARENTS 1 + #ifndef __METAL_PLIC_SUBINTERRUPTS #define __METAL_PLIC_SUBINTERRUPTS 0 #endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif #ifndef __METAL_CLIC_SUBINTERRUPTS #define __METAL_CLIC_SUBINTERRUPTS 0 #endif @@ -20,12 +30,16 @@ #define METAL_MAX_CLINT_INTERRUPTS 2 +#define __METAL_CLINT_NUM_PARENTS 2 + #define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 1 #define __METAL_PLIC_SUBINTERRUPTS 27 #define METAL_MAX_PLIC_INTERRUPTS 1 +#define __METAL_PLIC_NUM_PARENTS 1 + #define __METAL_CLIC_SUBINTERRUPTS 0 #define METAL_MAX_CLIC_INTERRUPTS 0 @@ -45,6 +59,7 @@ #include <metal/drivers/fixed-clock.h> +#include <metal/memory.h> #include <metal/drivers/riscv,clint0.h> #include <metal/drivers/riscv,cpu.h> #include <metal/drivers/riscv,plic0.h> @@ -70,6 +85,12 @@ struct __metal_driver_fixed_clock __metal_dt_clock_2; asm (".weak __metal_dt_clock_5"); struct __metal_driver_fixed_clock __metal_dt_clock_5; +asm (".weak __metal_dt_mem_dtim_80000000"); +struct metal_memory __metal_dt_mem_dtim_80000000; + +asm (".weak __metal_dt_mem_spi_10014000"); +struct metal_memory __metal_dt_mem_spi_10014000; + /* From clint@2000000 */ asm (".weak __metal_dt_clint_2000000"); struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; @@ -78,9 +99,8 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; asm (".weak __metal_dt_cpu_0"); struct __metal_driver_cpu __metal_dt_cpu_0; -/* From interrupt_controller */ -asm (".weak __metal_dt_interrupt_controller"); -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ asm (".weak __metal_dt_interrupt_controller_c000000"); @@ -140,6 +160,28 @@ struct __metal_driver_fixed_clock __metal_dt_clock_5 = { .rate = 32000000UL, }; +struct metal_memory __metal_dt_mem_dtim_80000000 = { + ._base_address = 2147483648UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_10014000 = { + ._base_address = 536870912UL, + ._size = 536870912UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + /* From clint@2000000 */ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, @@ -148,8 +190,9 @@ struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .control_size = 65536UL, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, .interrupt_lines[1] = 7, }; @@ -158,11 +201,11 @@ struct __metal_driver_cpu __metal_dt_cpu_0 = { .vtable = &__metal_driver_vtable_cpu, .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, .timebase = 1000000UL, - .interrupt_controller = &__metal_dt_interrupt_controller.controller, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, }; /* From interrupt_controller */ -struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .vtable = &__metal_driver_vtable_riscv_cpu_intc, .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, .init_done = 0, @@ -174,9 +217,8 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .vtable = &__metal_driver_vtable_riscv_plic0, .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, - .interrupt_line = 11UL, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, .control_base = 201326592UL, .control_size = 67108864UL, .max_priority = 7UL, @@ -189,8 +231,7 @@ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_externa .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, .init_done = 0, -/* From interrupt_controller */ - .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller, .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, .interrupt_lines[0] = 16, .interrupt_lines[1] = 17, @@ -316,6 +357,13 @@ struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = { }; +#define __METAL_DT_MAX_MEMORIES 2 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_dtim_80000000, + &__metal_dt_mem_spi_10014000}; + /* From serial@10013000 */ #define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_10013000.uart) @@ -328,22 +376,12 @@ struct __metal_driver_sifive_fe310_g000_prci __metal_dt_prci_10008000 = { #define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) -/* From cpu@0 */ -#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) - -#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) - #define __METAL_DT_MAX_HARTS 1 asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From interrupt_controller */ -#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) - -#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) - /* From interrupt_controller@c000000 */ #define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) diff --git a/bsp/sifive-hifive1/metal.ramrodata.lds b/bsp/sifive-hifive1/metal.ramrodata.lds index 58987fc..2f58f9b 100644 --- a/bsp/sifive-hifive1/metal.ramrodata.lds +++ b/bsp/sifive-hifive1/metal.ramrodata.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; @@ -214,7 +215,6 @@ SECTIONS { PROVIDE( metal_segment_heap_target_start = . ); . = __heap_size; - . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); PROVIDE( metal_segment_heap_target_end = . ); PROVIDE( _heap_end = . ); } >ram AT>ram :ram diff --git a/bsp/sifive-hifive1/metal.scratchpad.lds b/bsp/sifive-hifive1/metal.scratchpad.lds index d10076f..80a39b5 100644 --- a/bsp/sifive-hifive1/metal.scratchpad.lds +++ b/bsp/sifive-hifive1/metal.scratchpad.lds @@ -20,6 +20,7 @@ PHDRS SECTIONS { __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; diff --git a/bsp/update-targets.sh b/bsp/update-targets.sh index b79b5f5..0ae3ff4 100755 --- a/bsp/update-targets.sh +++ b/bsp/update-targets.sh @@ -34,7 +34,7 @@ done if [ "$CUSTOM_PATH" == "" -a "$CUSTOM_NAME" == "" -a "$DTSFILE" == "" ] then TARGET_LIST="$(ls -d coreip*) " - TARGET_LIST+="sifive-hifive1 sifive-hifive1-revb freedom-e310-arty " + TARGET_LIST+="sifive-hifive1 sifive-hifive1-revb freedom-e310-arty sifive-hifive-unleashed " else if [ ! -f "$DTSFILE" -a "$DTSFILE" != "*.dts" ] then diff --git a/doc/sphinx/contents.rst b/doc/sphinx/contents.rst index ab751d9..d0d7cc5 100644 --- a/doc/sphinx/contents.rst +++ b/doc/sphinx/contents.rst @@ -15,6 +15,10 @@ Freedom E SDK comes packaged with the following board support packages under the - sifive-hifive1-revb +- `SiFive HiFive Unleashed <https://www.sifive.com/boards/hifive-unleashed>`_ + + - sifive-hifive-unleashed + - `SiFive Freedom E310 Arty <https://github.com/sifive/freedom>`_ - freedom-e310-arty @@ -29,6 +33,8 @@ Freedom E SDK comes packaged with the following board support packages under the - coreip-s54-rtl - coreip-e76-rtl - coreip-s76-rtl + - coreip-u54-rtl + - coreip-u54mc-rtl - SiFive CoreIP Arty FPGA Evaluation targets diff --git a/freedom-metal b/freedom-metal -Subproject 1e1609b3ac4f5a4b5b1a06e46ac27a520818bd2 +Subproject 6d69e6d48babe4472a6f4671b832cb7df941f27 diff --git a/scripts/fixup-dts b/scripts/fixup-dts index adea17d..ddbbd0c 100755 --- a/scripts/fixup-dts +++ b/scripts/fixup-dts @@ -71,8 +71,8 @@ fi if [ `grep -c 'sifive,testram0' ${dts}` -eq 0 ]; then - # bullet cores have a memory defined already - if [ `grep -c 'sifive,bullet0' ${dts}` -eq 0 ]; then + # bullet and U cores have a memory defined already + if [ `grep -c 'sifive,bullet0' ${dts}` -eq 0 -a `grep -c 'SiFive,FU' ${dts}` -eq 0 ]; then echo "$0: Test memory node not found in ${dts}." diff --git a/software/multicore-hello b/software/multicore-hello new file mode 160000 +Subproject 211878a46834be031de521e70904ec3a6d80bc8 |