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authormwachs5 <megan@sifive.com>2017-11-16 09:30:52 -0800
committermwachs5 <megan@sifive.com>2017-11-16 09:30:52 -0800
commit0d9d9cc3d84949894080e1281fc8b68e9b1913c4 (patch)
tree2fcd18b5e5692a98d13d72379a0f025fa1e275ac
parentb53187a0434fe5e8dce288f55cfca36b292552e4 (diff)
E300 Arty: Don't need to specify the expected ID, just tell it where the SPIFlash controller is. This allows it to work for newer versions of the E300 Arty Dev Kit as well.
-rw-r--r--bsp/env/freedom-e300-arty/openocd.cfg4
1 files changed, 2 insertions, 2 deletions
diff --git a/bsp/env/freedom-e300-arty/openocd.cfg b/bsp/env/freedom-e300-arty/openocd.cfg
index f4b28ed..ba13207 100644
--- a/bsp/env/freedom-e300-arty/openocd.cfg
+++ b/bsp/env/freedom-e300-arty/openocd.cfg
@@ -13,13 +13,13 @@ ftdi_layout_signal LED -data 0x0800
#
set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+jtag newtap $_CHIPNAME cpu -irlen 5
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
-flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME 0x10014000
init
#reset
if {[ info exists pulse_srst]} {