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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-05 23:09:10 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-05 23:09:10 +0000 |
| commit | 39ea32d9f14d786d8457ef2e30b0bceb2e5729ce (patch) | |
| tree | 1ff732bf03f9eb4d3d0b650b40faccd27bd9714a | |
| parent | 27ce8f39998000aec5c1a309d3147c925117eb93 (diff) | |
| parent | 19921e76d3388e2768ba2f9ce090209e02e3a59a (diff) | |
Merge pull request #189 from sifive/more-codemodels
Add codemodel settings for new targets
| -rw-r--r-- | bsp/coreip-e20/settings.mk | 1 | ||||
| -rw-r--r-- | bsp/coreip-e21/settings.mk | 1 | ||||
| -rw-r--r-- | bsp/coreip-e24/settings.mk | 1 | ||||
| -rw-r--r-- | bsp/coreip-e34/settings.mk | 1 | ||||
| -rw-r--r-- | bsp/coreip-e76/settings.mk | 1 | ||||
| -rw-r--r-- | bsp/coreip-s54/settings.mk | 1 | ||||
| -rw-r--r-- | bsp/coreip-s76/settings.mk | 1 |
7 files changed, 7 insertions, 0 deletions
diff --git a/bsp/coreip-e20/settings.mk b/bsp/coreip-e20/settings.mk index 50c6504..1ac4d9f 100644 --- a/bsp/coreip-e20/settings.mk +++ b/bsp/coreip-e20/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imc RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 diff --git a/bsp/coreip-e21/settings.mk b/bsp/coreip-e21/settings.mk index 0c818ec..32bb84d 100644 --- a/bsp/coreip-e21/settings.mk +++ b/bsp/coreip-e21/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 diff --git a/bsp/coreip-e24/settings.mk b/bsp/coreip-e24/settings.mk index 0c818ec..32bb84d 100644 --- a/bsp/coreip-e24/settings.mk +++ b/bsp/coreip-e24/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 diff --git a/bsp/coreip-e34/settings.mk b/bsp/coreip-e34/settings.mk index 0c818ec..32bb84d 100644 --- a/bsp/coreip-e34/settings.mk +++ b/bsp/coreip-e34/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 diff --git a/bsp/coreip-e76/settings.mk b/bsp/coreip-e76/settings.mk index 3dcc8c7..fd049f4 100644 --- a/bsp/coreip-e76/settings.mk +++ b/bsp/coreip-e76/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=64 diff --git a/bsp/coreip-s54/settings.mk b/bsp/coreip-s54/settings.mk index 553417e..fabb838 100644 --- a/bsp/coreip-s54/settings.mk +++ b/bsp/coreip-s54/settings.mk @@ -1,3 +1,4 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 +RISCV_CMODE=medany COREIP_MEM_WIDTH=64 diff --git a/bsp/coreip-s76/settings.mk b/bsp/coreip-s76/settings.mk index 553417e..a7d8dfa 100644 --- a/bsp/coreip-s76/settings.mk +++ b/bsp/coreip-s76/settings.mk @@ -1,3 +1,4 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 +RISCV_CMODEL=medany COREIP_MEM_WIDTH=64 |