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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-05 12:53:25 -0800 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-05 12:53:25 -0800 |
| commit | 4b4ba5f34f09bf1aea8f331a68789bbf9cfb2e5c (patch) | |
| tree | c54e265a5edd547eca72efc441e8018fa5227db6 | |
| parent | 27ce8f39998000aec5c1a309d3147c925117eb93 (diff) | |
Remove PMP reference from hifive1
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
| -rw-r--r-- | bsp/sifive-hifive1/README.md | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md index 6311207..d0d0c7a 100644 --- a/bsp/sifive-hifive1/README.md +++ b/bsp/sifive-hifive1/README.md @@ -4,7 +4,6 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines |