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| author | Hsiang-Chia.Huang <hsiangchiah@sifive.com> | 2019-05-29 05:58:13 -0700 |
|---|---|---|
| committer | Hsiang-Chia.Huang <hsiangchiah@sifive.com> | 2019-06-02 19:40:32 -0700 |
| commit | 9ed1c05e3b202ef2ef17cae4bfc0ca6425541d13 (patch) | |
| tree | 529b31e1159e56592621439d1bca1db64da03817 | |
| parent | 85a442db0dd3f2440019fe8586d28c2dec148cd3 (diff) | |
Add compile options for coremark and update freedom-metal repo.
Regenerate files in bsps.
| -rw-r--r-- | bsp/coreip-e20-arty/metal.ramrodata.lds | 14 | ||||
| m--------- | freedom-metal | 0 | ||||
| -rw-r--r-- | scripts/standalone.mk | 17 |
3 files changed, 26 insertions, 5 deletions
diff --git a/bsp/coreip-e20-arty/metal.ramrodata.lds b/bsp/coreip-e20-arty/metal.ramrodata.lds index 513e567..0c6fffa 100644 --- a/bsp/coreip-e20-arty/metal.ramrodata.lds +++ b/bsp/coreip-e20-arty/metal.ramrodata.lds @@ -9,8 +9,9 @@ ENTRY(_enter) MEMORY { - ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x10000 + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x8000 flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x1fc00000 + itim (wx!rai) : ORIGIN = 0x80008000, LENGTH = 0x8000 } PHDRS @@ -127,13 +128,17 @@ SECTIONS { . = ALIGN(4); PROVIDE( metal_segment_itim_target_start = . ); - } >ram AT>flash :ram_init + } >itim AT>flash :itim_init .itim : { *(.itim .itim.*) - } >flash AT>flash :flash + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >itim AT>flash :itim_init . = ALIGN(8); @@ -144,8 +149,7 @@ SECTIONS *(.text.startup .text.startup.*) *(.text .text.*) *(.gnu.linkonce.t.*) - *(.itim .itim.*) - } >flash AT>flash :flash + } >itim AT>flash :flash .lalign : diff --git a/freedom-metal b/freedom-metal -Subproject 7eb6be9e76019ab6c20c78c529b747bf6bc2b16 +Subproject 2c101d05a09afaf8f00469e5b0565069055d6a2 diff --git a/scripts/standalone.mk b/scripts/standalone.mk index 0526bd1..d0740cd 100644 --- a/scripts/standalone.mk +++ b/scripts/standalone.mk @@ -49,6 +49,14 @@ ifeq ($(LINK_TARGET),) endif endif +ifeq ($(PROGRAM),coremark) +ifeq ($(CONFIGURATION),release) +ifeq ($(LINK_TARGET),) +LINK_TARGET = ramrodata +endif +endif +endif + ifeq ($(LINK_TARGET),) LINK_TARGET = default endif @@ -127,6 +135,15 @@ endif RISCV_XCFLAGS += -DDHRY_ITERS=$(TARGET_DHRY_ITERS) endif +ifeq ($(PROGRAM),coremark) +ifeq ($(RISCV_SERIES),sifive-7-series) +RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions -funroll-all-loops --param max-inline-insns-auto=20 -falign-functions=8 -falign-jumps=8 -falign-loops=8 --param inline-min-speedup=10 -mtune=sifive-7-series -ffast-math +else +RISCV_XCFLAGS += -O2 -fno-common -funroll-loops -finline-functions --param max-inline-insns-auto=20 -falign-functions=4 -falign-jumps=4 -falign-loops=4 --param inline-min-speedup=10 +endif +RISCV_XCFLAGS += -DITERATIONS=$(TARGET_CORE_ITERS) +endif + # Turn on garbage collection for unused sections RISCV_LDFLAGS += -Wl,--gc-sections # Turn on linker map file generation |