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authorMegan Wachs <megan@sifive.com>2016-08-01 10:07:07 -0700
committerMegan Wachs <megan@sifive.com>2016-08-01 11:35:34 -0700
commitb80083544c12351a969a1ce7be83c88707db73e4 (patch)
treeb30c60f84368c8319a7f4beeb6834c84b776285f
parent51bca217eabfcc90d21924241250eca63b860a91 (diff)
Bump Tool versions
- Remove duplicate GDB - Update target name to freedom-e300
-rw-r--r--.gitmodules3
-rw-r--r--Makefile52
m---------riscv-binutils-gdb0
m---------riscv-gnu-toolchain0
m---------riscv-tests0
-rw-r--r--software/shared/Makefile.shared3
l---------software/shared/link.lds1
-rw-r--r--software/shared/syscall.c6
8 files changed, 32 insertions, 33 deletions
diff --git a/.gitmodules b/.gitmodules
index c870132..9cadd28 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,9 +4,6 @@
[submodule "riscv-gnu-toolchain"]
path = riscv-gnu-toolchain
url = http://github.com/riscv/riscv-gnu-toolchain.git
-[submodule "riscv-binutils-gdb"]
- path = riscv-binutils-gdb
- url = http://github.com/sifive/riscv-binutils-gdb.git
[submodule "riscv-tests"]
path = riscv-tests
url = http://github.com/riscv/riscv-tests.git
diff --git a/Makefile b/Makefile
index ac1f9b6..a9f9122 100644
--- a/Makefile
+++ b/Makefile
@@ -17,20 +17,26 @@ help :
@echo " tools:"
@echo " Install compilation & debugging tools"
@echo ""
- @echo " fpga [BOOTROM=demo]:"
- @echo " Rebuild the image (including Boot SW) to"
- @echo " reprogram the FPGA. "
- @echo ""
- @echo " software [PROGRAM=demo_gpio]:"
+ @echo " software [PROGRAM=demo_gpio PLATFORM=freedom-e300]:"
@echo " Build a software program to load with the"
@echo " debugger."
@echo ""
- @echo " run_debug [PROGRAM=demo_gpio]:"
- @echo " Launch the debugging tools to load or"
- @echo " debug running programs."
+ @echo " run_debug [PROGRAM=demo_gpio PLATFORM=freedom-e300]:"
+ @echo " Launch OpenOCD & GDB to load or debug "
+ @echo " running programs."
+ @echo ""
+ @echo " run_openocd [PLATFORM=freedom-e300]:"
+ @echo " run_gdb [PROGRAM=demo_gpio PLATFORM=freedom-e300]:"
+ @echo " Launch OpenOCD & GDB seperately"
@echo ""
+ @echo " fpga [BOOTROM=demo]:"
+ @echo " Rebuild the image (including Boot SW) to"
+ @echo " reprogram the FPGA image for Arty Board. "
+ @echo ""
+
@echo " For more information, visit dev.sifive.com"
+
#############################################################
# This section is for tool installation
#############################################################
@@ -40,10 +46,6 @@ toolchain32_wrkdir := $(wrkdir)/riscv32-gnu-toolchain
toolchain64_wrkdir := $(wrkdir)/riscv64-gnu-toolchain
toolchain_dest := $(CURDIR)/toolchain
-gdb_srcdir := $(srcdir)/riscv-binutils-gdb
-gdb_wrkdir := $(wrkdir)/riscv-binutils-gdb
-gdb_dest := $(CURDIR)/toolchain
-
openocd_srcdir := $(srcdir)/openocd
openocd_wrkdir := $(wrkdir)/openocd
openocd_dest := $(CURDIR)/toolchain
@@ -56,13 +58,12 @@ target32 := riscv32-unknown-linux-gnu
all: tools
@echo All done.
-tools: tools64 tools32 openocd gdb
+tools: tools64 tools32 openocd
@echo All Tools Installed
tools64: $(toolchain_dest)/bin/$(target64)-gcc
tools32: $(toolchain_dest)/bin/$(target32)-gcc
openocd: $(openocd_dest)/bin/openocd
-gdb: $(gdb_dest)/bin/$(target64)-gdb
$(toolchain_dest)/bin/$(target64)-gcc: $(toolchain_srcdir)
mkdir -p $(toolchain64_wrkdir)
@@ -83,13 +84,6 @@ $(openocd_dest)/bin/openocd: $(openocd_srcdir)
$(MAKE) -C $(openocd_wrkdir)
$(MAKE) -C $(openocd_wrkdir) install
-$(gdb_dest)/bin/$(target64)-gdb : $(gdb_srcdir)
- mkdir -p $(gdb_wrkdir)
- cd $(gdb_wrkdir); $(gdb_srcdir)/configure --prefix=$(gdb_dest) --target=riscv64-unknown-elf
- $(MAKE) -C $(gdb_wrkdir)
- $(MAKE) -C $(gdb_wrkdir) install
-
-
.PHONY: uninstall
uninstall:
rm -rf -- $(toolchain_dest)
@@ -129,15 +123,23 @@ software_clean:
#############################################################
# This Section is for launching the debugger
#############################################################
-OPENOCD = $(toolchain_dest)/bin/openocd
-OPENOCDARGS += -f $(srcdir)/riscv-tests/debug/targets/m2gl_m2s/openocd.cfg
+OPENOCD = $(toolchain_dest)/bin/openocd
+PLATFORM ?= freedom-e300
+OPENOCDARGS += -f $(srcdir)/riscv-tests/debug/targets/$(PLATFORM)/openocd.cfg
GDB = $(toolchain_dest)/bin/riscv64-unknown-elf-gdb
-GDBARGS += -ex "target extended-remote localhost:3333"
+GDBCMDS += -ex "target extended-remote localhost:3333"
+GDBARGS =
+
+run_openocd:
+ $(OPENOCD) $(OPENOCDARGS)
+
+run_gdb:
+ $(GDB) $(PROGRAM_DIR)/$(PROGRAM) $(GDBARGS)
run_debug:
$(OPENOCD) $(OPENOCDARGS) &
- $(GDB) $(PROGRAM_DIR)/$(PROGRAM) $(GDBARGS)
+ $(GDB) $(PROGRAM_DIR)/$(PROGRAM) $(GDBARGS) $(GDBCMDS)
.PHONY: clean
clean:
diff --git a/riscv-binutils-gdb b/riscv-binutils-gdb
deleted file mode 160000
-Subproject 23e74aee45e4b9330310c4d18fe68e7f87ba1cb
diff --git a/riscv-gnu-toolchain b/riscv-gnu-toolchain
-Subproject 83665a769ab27547192c86045bd17b14f4f6446
+Subproject 7494440b5e6182e1237ebdbdda8f72169a4afff
diff --git a/riscv-tests b/riscv-tests
-Subproject 97cffefa6ebeb5fdc174fc51c7d642f714daa55
+Subproject 4117bf6b12b2de928ca19e9638376f75f7be6d7
diff --git a/software/shared/Makefile.shared b/software/shared/Makefile.shared
index 5817826..70550a0 100644
--- a/software/shared/Makefile.shared
+++ b/software/shared/Makefile.shared
@@ -8,7 +8,8 @@ C_SRCS += $(SHARED_DIR)/init.c
C_SRCS += $(SHARED_DIR)/syscall.c
C_SRCS += $(SHARED_DIR)/drivers_sifive/plic.c
-LINKER_SCRIPT := $(SHARED_DIR)/link.lds
+PLATFORM ?= freedom-e300
+LINKER_SCRIPT := $(SWDIR)/../riscv-tests/debug/targets/$(PLATFORM)/link.lds
HEADERS += $(SHARED_DIR)/*.h
C_SRCS += $(TARGET).c
diff --git a/software/shared/link.lds b/software/shared/link.lds
deleted file mode 120000
index 013b6cb..0000000
--- a/software/shared/link.lds
+++ /dev/null
@@ -1 +0,0 @@
-../../riscv-tests/debug/targets/m2gl_m2s/link.lds \ No newline at end of file
diff --git a/software/shared/syscall.c b/software/shared/syscall.c
index 2e4199f..1acb88f 100644
--- a/software/shared/syscall.c
+++ b/software/shared/syscall.c
@@ -46,7 +46,7 @@ void _exit(int code)
write(STDERR_FILENO, message, strlen(message));
write_hex(STDERR_FILENO, code);
- while (1);
+ while (1){};
}
@@ -192,11 +192,11 @@ ssize_t write(int fd, const void* ptr, size_t len)
for (jj = 0; jj < len; jj++){
- while ((*uart_tx_count) < 1);
+ while ((*uart_tx_count) < 1){};
*uart_tx = current[jj];
if (current[jj] == '\n'){
- while ((*uart_tx_count) < 1);
+ while ((*uart_tx_count) < 1){};
*uart_tx = '\r';
}
}