diff options
| author | hsiang-chia.huang <hsiangchia.huang@sifive.com> | 2019-05-24 10:22:08 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-24 10:22:08 +0800 |
| commit | faf58a49c3b6421107ada0e8af43170a5ffafcea (patch) | |
| tree | 3996d52a748ae2420b5c9c6c9efe4158d5dece53 | |
| parent | 7817c5e85cb6f9f6d5b98f6702fa4b7d1fb99e02 (diff) | |
| parent | 2c0269905929128bd0bd13a55ae3d8afd60a1af6 (diff) | |
Merge branch 'development-19.05' into dhrystone_19.05
197 files changed, 900 insertions, 515 deletions
diff --git a/.gitmodules b/.gitmodules index aba5d34..40b88d9 100644 --- a/.gitmodules +++ b/.gitmodules @@ -46,3 +46,9 @@ [submodule "software/multicore-hello"] path = software/multicore-hello url = https://github.com/sifive/example-multicore-hello.git +[submodule "software/example-user-mode"] + path = software/example-user-mode + url = https://github.com/sifive/example-user-mode.git +[submodule "software/example-user-syscall"] + path = software/example-user-syscall + url = https://github.com/sifive/example-user-syscall.git @@ -139,7 +139,7 @@ list-target-tags: # Metal programs are any submodules in the software folder .PHONY: list-programs list-programs: - @echo program-list: $(shell grep -o '= software/.*$$' .gitmodules | sed 's/.*\///') + @echo program-list: $(shell ls $(PROGRAM_ROOT)/software) .PHONY: list-options list-options: list-programs list-targets diff --git a/bsp/coreip-e20-arty/metal-inline.h b/bsp/coreip-e20-arty/metal-inline.h index 8170f13..3b9c4e5 100644 --- a/bsp/coreip-e20-arty/metal-inline.h +++ b/bsp/coreip-e20-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -23,8 +23,10 @@ extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock * /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/coreip-e20-arty/metal-platform.h b/bsp/coreip-e20-arty/metal-platform.h index 0e58533..d049910 100644 --- a/bsp/coreip-e20-arty/metal-platform.h +++ b/bsp/coreip-e20-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E20_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-e20-arty/metal.default.lds b/bsp/coreip-e20-arty/metal.default.lds index 2516d37..badb729 100644 --- a/bsp/coreip-e20-arty/metal.default.lds +++ b/bsp/coreip-e20-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e20-arty/metal.h b/bsp/coreip-e20-arty/metal.h index 5e182ab..34014a1 100644 --- a/bsp/coreip-e20-arty/metal.h +++ b/bsp/coreip-e20-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -170,6 +170,16 @@ static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock * /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -190,6 +200,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/coreip-e20-arty/metal.ramrodata.lds b/bsp/coreip-e20-arty/metal.ramrodata.lds index 0290158..5742665 100644 --- a/bsp/coreip-e20-arty/metal.ramrodata.lds +++ b/bsp/coreip-e20-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e20-arty/metal.scratchpad.lds b/bsp/coreip-e20-arty/metal.scratchpad.lds index 5d4cd7b..3702a05 100644 --- a/bsp/coreip-e20-arty/metal.scratchpad.lds +++ b/bsp/coreip-e20-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e20-arty/settings.mk b/bsp/coreip-e20-arty/settings.mk index bc4125f..9a4c6d6 100644 --- a/bsp/coreip-e20-arty/settings.mk +++ b/bsp/coreip-e20-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imc diff --git a/bsp/coreip-e20-rtl/metal-inline.h b/bsp/coreip-e20-rtl/metal-inline.h index 1f2399d..a896131 100644 --- a/bsp/coreip-e20-rtl/metal-inline.h +++ b/bsp/coreip-e20-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -22,8 +22,10 @@ /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/coreip-e20-rtl/metal-platform.h b/bsp/coreip-e20-rtl/metal-platform.h index b4f13ec..4aa40ea 100644 --- a/bsp/coreip-e20-rtl/metal-platform.h +++ b/bsp/coreip-e20-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E20_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-e20-rtl/metal.default.lds b/bsp/coreip-e20-rtl/metal.default.lds index c95e179..7937b08 100644 --- a/bsp/coreip-e20-rtl/metal.default.lds +++ b/bsp/coreip-e20-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -27,6 +27,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e20-rtl/metal.h b/bsp/coreip-e20-rtl/metal.h index 68d33ad..6749faa 100644 --- a/bsp/coreip-e20-rtl/metal.h +++ b/bsp/coreip-e20-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -97,6 +97,16 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -117,6 +127,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/coreip-e20-rtl/metal.ramrodata.lds b/bsp/coreip-e20-rtl/metal.ramrodata.lds index 02f50c8..2343ee7 100644 --- a/bsp/coreip-e20-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e20-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -27,6 +27,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e20-rtl/metal.scratchpad.lds b/bsp/coreip-e20-rtl/metal.scratchpad.lds index c95e179..7937b08 100644 --- a/bsp/coreip-e20-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e20-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -27,6 +27,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e20-rtl/settings.mk b/bsp/coreip-e20-rtl/settings.mk index 26ee991..a935127 100644 --- a/bsp/coreip-e20-rtl/settings.mk +++ b/bsp/coreip-e20-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imc diff --git a/bsp/coreip-e21-arty/design.dts b/bsp/coreip-e21-arty/design.dts index 7303568..40f61d0 100644 --- a/bsp/coreip-e21-arty/design.dts +++ b/bsp/coreip-e21-arty/design.dts @@ -21,6 +21,7 @@ device_type = "cpu"; reg = <0x0>; riscv,isa = "rv32imac"; + riscv,pmpregions = <4>; status = "okay"; timebase-frequency = <32000000>; hardware-exec-breakpoint-count = <4>; @@ -36,10 +37,6 @@ #size-cells = <1>; compatible = "SiFive,FE210G-soc", "fe210-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <4>; - }; hfclk: clock@0 { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/bsp/coreip-e21-arty/metal-inline.h b/bsp/coreip-e21-arty/metal-inline.h index 0f167d5..21116c7 100644 --- a/bsp/coreip-e21-arty/metal-inline.h +++ b/bsp/coreip-e21-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -23,8 +23,10 @@ extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock * /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -173,11 +175,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable, diff --git a/bsp/coreip-e21-arty/metal-platform.h b/bsp/coreip-e21-arty/metal-platform.h index 75dc2dd..3e275a2 100644 --- a/bsp/coreip-e21-arty/metal-platform.h +++ b/bsp/coreip-e21-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E21_ARTY__METAL_PLATFORM_H @@ -12,11 +12,6 @@ #define METAL_FIXED_CLOCK -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 4UL - -#define METAL_RISCV_PMP - /* From interrupt_controller@2000000 */ #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL #define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL diff --git a/bsp/coreip-e21-arty/metal.default.lds b/bsp/coreip-e21-arty/metal.default.lds index 0b7a37a..5bea1f5 100644 --- a/bsp/coreip-e21-arty/metal.default.lds +++ b/bsp/coreip-e21-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e21-arty/metal.h b/bsp/coreip-e21-arty/metal.h index 89b2931..f5e9533 100644 --- a/bsp/coreip-e21-arty/metal.h +++ b/bsp/coreip-e21-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_cpu __metal_dt_cpu_0; struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; @@ -174,6 +174,16 @@ static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock * /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -194,6 +204,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 4; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -1226,8 +1246,7 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e21-arty/metal.ramrodata.lds b/bsp/coreip-e21-arty/metal.ramrodata.lds index e1e793f..1e37ef6 100644 --- a/bsp/coreip-e21-arty/metal.ramrodata.lds +++ b/bsp/coreip-e21-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e21-arty/metal.scratchpad.lds b/bsp/coreip-e21-arty/metal.scratchpad.lds index e986066..21e626f 100644 --- a/bsp/coreip-e21-arty/metal.scratchpad.lds +++ b/bsp/coreip-e21-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk index 3e8ebf8..ab96737 100644 --- a/bsp/coreip-e21-arty/settings.mk +++ b/bsp/coreip-e21-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/coreip-e21-rtl/design.dts b/bsp/coreip-e21-rtl/design.dts index 9e846c0..ed9fa86 100644 --- a/bsp/coreip-e21-rtl/design.dts +++ b/bsp/coreip-e21-rtl/design.dts @@ -14,6 +14,7 @@ device_type = "cpu"; reg = <0x0>; riscv,isa = "rv32imac"; + riscv,pmpregions = <4>; status = "okay"; timebase-frequency = <1000000>; hardware-exec-breakpoint-count = <4>; @@ -29,10 +30,6 @@ #size-cells = <1>; compatible = "SiFive,FE210G-soc", "fe210-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L11: ahb-periph-port@20000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/bsp/coreip-e21-rtl/metal-inline.h b/bsp/coreip-e21-rtl/metal-inline.h index a117144..fc8a319 100644 --- a/bsp/coreip-e21-rtl/metal-inline.h +++ b/bsp/coreip-e21-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -22,8 +22,10 @@ /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -131,11 +133,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable, diff --git a/bsp/coreip-e21-rtl/metal-platform.h b/bsp/coreip-e21-rtl/metal-platform.h index baf85fc..51a7b22 100644 --- a/bsp/coreip-e21-rtl/metal-platform.h +++ b/bsp/coreip-e21-rtl/metal-platform.h @@ -1,17 +1,12 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E21_RTL__METAL_PLATFORM_H #define COREIP_E21_RTL__METAL_PLATFORM_H -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From interrupt_controller@2000000 */ #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL #define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL diff --git a/bsp/coreip-e21-rtl/metal.default.lds b/bsp/coreip-e21-rtl/metal.default.lds index d021e81..0f4bf1e 100644 --- a/bsp/coreip-e21-rtl/metal.default.lds +++ b/bsp/coreip-e21-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e21-rtl/metal.h b/bsp/coreip-e21-rtl/metal.h index 38b19a4..eb1da58 100644 --- a/bsp/coreip-e21-rtl/metal.h +++ b/bsp/coreip-e21-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -80,7 +80,7 @@ struct __metal_driver_cpu __metal_dt_cpu_0; struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; @@ -103,6 +103,16 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -123,6 +133,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 4; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -694,8 +714,7 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e21-rtl/metal.ramrodata.lds b/bsp/coreip-e21-rtl/metal.ramrodata.lds index 199cc1f..b3b1581 100644 --- a/bsp/coreip-e21-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e21-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e21-rtl/metal.scratchpad.lds b/bsp/coreip-e21-rtl/metal.scratchpad.lds index 8bea50d..4b1b222 100644 --- a/bsp/coreip-e21-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e21-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e21-rtl/settings.mk b/bsp/coreip-e21-rtl/settings.mk index fd09a82..afc60e3 100644 --- a/bsp/coreip-e21-rtl/settings.mk +++ b/bsp/coreip-e21-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/coreip-e24-arty/design.dts b/bsp/coreip-e24-arty/design.dts index f288b54..ba6b037 100644 --- a/bsp/coreip-e24-arty/design.dts +++ b/bsp/coreip-e24-arty/design.dts @@ -21,6 +21,7 @@ device_type = "cpu"; reg = <0x0>; riscv,isa = "rv32imafc"; + riscv,pmpregions = <4>; status = "okay"; timebase-frequency = <32000000>; hardware-exec-breakpoint-count = <4>; @@ -36,10 +37,6 @@ #size-cells = <1>; compatible = "SiFive,FE240G-soc", "fe240-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <4>; - }; hfclk: clock@0 { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/bsp/coreip-e24-arty/metal-inline.h b/bsp/coreip-e24-arty/metal-inline.h index bbe456e..ddb5acd 100644 --- a/bsp/coreip-e24-arty/metal-inline.h +++ b/bsp/coreip-e24-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -23,8 +23,10 @@ extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock * /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -173,11 +175,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable, diff --git a/bsp/coreip-e24-arty/metal-platform.h b/bsp/coreip-e24-arty/metal-platform.h index 1a3bd88..160303c 100644 --- a/bsp/coreip-e24-arty/metal-platform.h +++ b/bsp/coreip-e24-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E24_ARTY__METAL_PLATFORM_H @@ -12,11 +12,6 @@ #define METAL_FIXED_CLOCK -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 4UL - -#define METAL_RISCV_PMP - /* From interrupt_controller@2000000 */ #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL #define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL diff --git a/bsp/coreip-e24-arty/metal.default.lds b/bsp/coreip-e24-arty/metal.default.lds index 0b7a37a..5bea1f5 100644 --- a/bsp/coreip-e24-arty/metal.default.lds +++ b/bsp/coreip-e24-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e24-arty/metal.h b/bsp/coreip-e24-arty/metal.h index 772ac57..cb76f8f 100644 --- a/bsp/coreip-e24-arty/metal.h +++ b/bsp/coreip-e24-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_cpu __metal_dt_cpu_0; struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; @@ -174,6 +174,16 @@ static inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock * /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -194,6 +204,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 4; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -1226,8 +1246,7 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e24-arty/metal.ramrodata.lds b/bsp/coreip-e24-arty/metal.ramrodata.lds index e1e793f..1e37ef6 100644 --- a/bsp/coreip-e24-arty/metal.ramrodata.lds +++ b/bsp/coreip-e24-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e24-arty/metal.scratchpad.lds b/bsp/coreip-e24-arty/metal.scratchpad.lds index e986066..21e626f 100644 --- a/bsp/coreip-e24-arty/metal.scratchpad.lds +++ b/bsp/coreip-e24-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e24-arty/settings.mk b/bsp/coreip-e24-arty/settings.mk index 8f23cea..1e501a6 100644 --- a/bsp/coreip-e24-arty/settings.mk +++ b/bsp/coreip-e24-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-e24-rtl/design.dts b/bsp/coreip-e24-rtl/design.dts index da1b792..a254a10 100644 --- a/bsp/coreip-e24-rtl/design.dts +++ b/bsp/coreip-e24-rtl/design.dts @@ -14,6 +14,7 @@ device_type = "cpu"; reg = <0x0>; riscv,isa = "rv32imafc"; + riscv,pmpregions = <4>; status = "okay"; timebase-frequency = <1000000>; hardware-exec-breakpoint-count = <4>; @@ -29,10 +30,6 @@ #size-cells = <1>; compatible = "SiFive,FE240G-soc", "fe240-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L11: ahb-periph-port@20000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/bsp/coreip-e24-rtl/metal-inline.h b/bsp/coreip-e24-rtl/metal-inline.h index dd34d93..acc2c7e 100644 --- a/bsp/coreip-e24-rtl/metal-inline.h +++ b/bsp/coreip-e24-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -22,8 +22,10 @@ /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -131,11 +133,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable, diff --git a/bsp/coreip-e24-rtl/metal-platform.h b/bsp/coreip-e24-rtl/metal-platform.h index dabc75f..db73ab4 100644 --- a/bsp/coreip-e24-rtl/metal-platform.h +++ b/bsp/coreip-e24-rtl/metal-platform.h @@ -1,17 +1,12 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E24_RTL__METAL_PLATFORM_H #define COREIP_E24_RTL__METAL_PLATFORM_H -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From interrupt_controller@2000000 */ #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL #define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL diff --git a/bsp/coreip-e24-rtl/metal.default.lds b/bsp/coreip-e24-rtl/metal.default.lds index d021e81..0f4bf1e 100644 --- a/bsp/coreip-e24-rtl/metal.default.lds +++ b/bsp/coreip-e24-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e24-rtl/metal.h b/bsp/coreip-e24-rtl/metal.h index 6d97dbd..222afa0 100644 --- a/bsp/coreip-e24-rtl/metal.h +++ b/bsp/coreip-e24-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -80,7 +80,7 @@ struct __metal_driver_cpu __metal_dt_cpu_0; struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; @@ -103,6 +103,16 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -123,6 +133,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 4; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -694,8 +714,7 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e24-rtl/metal.ramrodata.lds b/bsp/coreip-e24-rtl/metal.ramrodata.lds index 199cc1f..b3b1581 100644 --- a/bsp/coreip-e24-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e24-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e24-rtl/metal.scratchpad.lds b/bsp/coreip-e24-rtl/metal.scratchpad.lds index 8bea50d..4b1b222 100644 --- a/bsp/coreip-e24-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e24-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e24-rtl/settings.mk b/bsp/coreip-e24-rtl/settings.mk index 715b312..dc10ea1 100644 --- a/bsp/coreip-e24-rtl/settings.mk +++ b/bsp/coreip-e24-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-e31-arty/design.dts b/bsp/coreip-e31-arty/design.dts index e9dda78..cf5dcab 100644 --- a/bsp/coreip-e31-arty/design.dts +++ b/bsp/coreip-e31-arty/design.dts @@ -25,6 +25,7 @@ next-level-cache = <&L10>; reg = <0x0>; riscv,isa = "rv32imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; @@ -47,10 +48,6 @@ compatible = "fixed-clock"; clock-frequency = <32500000>; }; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L2: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L4 3 &L4 7>; diff --git a/bsp/coreip-e31-arty/metal-inline.h b/bsp/coreip-e31-arty/metal-inline.h index fe89e39..463ecca 100644 --- a/bsp/coreip-e31-arty/metal-inline.h +++ b/bsp/coreip-e31-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -28,8 +28,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -188,11 +190,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-e31-arty/metal-platform.h b/bsp/coreip-e31-arty/metal-platform.h index c4c1b37..3993a61 100644 --- a/bsp/coreip-e31-arty/metal-platform.h +++ b/bsp/coreip-e31-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E31_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e31-arty/metal.default.lds b/bsp/coreip-e31-arty/metal.default.lds index 82a199e..4a9e1be 100644 --- a/bsp/coreip-e31-arty/metal.default.lds +++ b/bsp/coreip-e31-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e31-arty/metal.h b/bsp/coreip-e31-arty/metal.h index f3a6fb3..43e71a3 100644 --- a/bsp/coreip-e31-arty/metal.h +++ b/bsp/coreip-e31-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -109,7 +109,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -240,6 +240,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -260,6 +270,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -946,8 +966,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-e31-arty/metal.ramrodata.lds b/bsp/coreip-e31-arty/metal.ramrodata.lds index 22eeb0a..a280082 100644 --- a/bsp/coreip-e31-arty/metal.ramrodata.lds +++ b/bsp/coreip-e31-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e31-arty/metal.scratchpad.lds b/bsp/coreip-e31-arty/metal.scratchpad.lds index 808429b..16211dc 100644 --- a/bsp/coreip-e31-arty/metal.scratchpad.lds +++ b/bsp/coreip-e31-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk index 3e8ebf8..ab96737 100644 --- a/bsp/coreip-e31-arty/settings.mk +++ b/bsp/coreip-e31-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/coreip-e31-rtl/design.dts b/bsp/coreip-e31-rtl/design.dts index 7c527ec..6bfbf1a 100644 --- a/bsp/coreip-e31-rtl/design.dts +++ b/bsp/coreip-e31-rtl/design.dts @@ -17,6 +17,7 @@ i-cache-size = <16384>; reg = <0x0>; riscv,isa = "rv32imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; @@ -34,10 +35,6 @@ #size-cells = <1>; compatible = "SiFive,FE310G-soc", "fe310-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L12: ahb-periph-port@20000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/bsp/coreip-e31-rtl/metal-inline.h b/bsp/coreip-e31-rtl/metal-inline.h index 173385b..a5035c7 100644 --- a/bsp/coreip-e31-rtl/metal-inline.h +++ b/bsp/coreip-e31-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -27,8 +27,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -150,11 +152,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-e31-rtl/metal-platform.h b/bsp/coreip-e31-rtl/metal-platform.h index 43c8148..9e03fae 100644 --- a/bsp/coreip-e31-rtl/metal-platform.h +++ b/bsp/coreip-e31-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E31_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e31-rtl/metal.default.lds b/bsp/coreip-e31-rtl/metal.default.lds index d4a124f..f687862 100644 --- a/bsp/coreip-e31-rtl/metal.default.lds +++ b/bsp/coreip-e31-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e31-rtl/metal.h b/bsp/coreip-e31-rtl/metal.h index 22fc0eb..9e977af 100644 --- a/bsp/coreip-e31-rtl/metal.h +++ b/bsp/coreip-e31-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -175,6 +175,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -195,6 +205,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -833,8 +853,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-e31-rtl/metal.ramrodata.lds b/bsp/coreip-e31-rtl/metal.ramrodata.lds index 6f9d52e..e75a025 100644 --- a/bsp/coreip-e31-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e31-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e31-rtl/metal.scratchpad.lds b/bsp/coreip-e31-rtl/metal.scratchpad.lds index d711300..d05f5c2 100644 --- a/bsp/coreip-e31-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e31-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk index fd09a82..afc60e3 100644 --- a/bsp/coreip-e31-rtl/settings.mk +++ b/bsp/coreip-e31-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/coreip-e34-arty/design.dts b/bsp/coreip-e34-arty/design.dts index d0e640b..4cb0962 100644 --- a/bsp/coreip-e34-arty/design.dts +++ b/bsp/coreip-e34-arty/design.dts @@ -25,6 +25,7 @@ next-level-cache = <&L10>; reg = <0x0>; riscv,isa = "rv32imafc"; + riscv,pmpregions = <8>; sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; @@ -47,10 +48,6 @@ compatible = "fixed-clock"; clock-frequency = <32500000>; }; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L2: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L4 3 &L4 7>; diff --git a/bsp/coreip-e34-arty/metal-inline.h b/bsp/coreip-e34-arty/metal-inline.h index 1ba2da5..c322ecb 100644 --- a/bsp/coreip-e34-arty/metal-inline.h +++ b/bsp/coreip-e34-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -28,8 +28,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -188,11 +190,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-e34-arty/metal-platform.h b/bsp/coreip-e34-arty/metal-platform.h index c2cacc4..e3781a9 100644 --- a/bsp/coreip-e34-arty/metal-platform.h +++ b/bsp/coreip-e34-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E34_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e34-arty/metal.default.lds b/bsp/coreip-e34-arty/metal.default.lds index 82a199e..4a9e1be 100644 --- a/bsp/coreip-e34-arty/metal.default.lds +++ b/bsp/coreip-e34-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e34-arty/metal.h b/bsp/coreip-e34-arty/metal.h index 949a75c..384bd19 100644 --- a/bsp/coreip-e34-arty/metal.h +++ b/bsp/coreip-e34-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -109,7 +109,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -240,6 +240,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -260,6 +270,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -946,8 +966,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-e34-arty/metal.ramrodata.lds b/bsp/coreip-e34-arty/metal.ramrodata.lds index 22eeb0a..a280082 100644 --- a/bsp/coreip-e34-arty/metal.ramrodata.lds +++ b/bsp/coreip-e34-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e34-arty/metal.scratchpad.lds b/bsp/coreip-e34-arty/metal.scratchpad.lds index 808429b..16211dc 100644 --- a/bsp/coreip-e34-arty/metal.scratchpad.lds +++ b/bsp/coreip-e34-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e34-arty/settings.mk b/bsp/coreip-e34-arty/settings.mk index 8f23cea..1e501a6 100644 --- a/bsp/coreip-e34-arty/settings.mk +++ b/bsp/coreip-e34-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-e34-rtl/design.dts b/bsp/coreip-e34-rtl/design.dts index 142e9d4..745f2b4 100644 --- a/bsp/coreip-e34-rtl/design.dts +++ b/bsp/coreip-e34-rtl/design.dts @@ -17,6 +17,7 @@ i-cache-size = <16384>; reg = <0x0>; riscv,isa = "rv32imafc"; + riscv,pmpregions = <8>; sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; @@ -34,10 +35,6 @@ #size-cells = <1>; compatible = "SiFive,FE340G-soc", "fe340-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L12: ahb-periph-port@20000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/bsp/coreip-e34-rtl/metal-inline.h b/bsp/coreip-e34-rtl/metal-inline.h index 6ebb5a0..8a7c179 100644 --- a/bsp/coreip-e34-rtl/metal-inline.h +++ b/bsp/coreip-e34-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -27,8 +27,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -150,11 +152,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-e34-rtl/metal-platform.h b/bsp/coreip-e34-rtl/metal-platform.h index 8ac399d..4b128f9 100644 --- a/bsp/coreip-e34-rtl/metal-platform.h +++ b/bsp/coreip-e34-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E34_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e34-rtl/metal.default.lds b/bsp/coreip-e34-rtl/metal.default.lds index d4a124f..f687862 100644 --- a/bsp/coreip-e34-rtl/metal.default.lds +++ b/bsp/coreip-e34-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e34-rtl/metal.h b/bsp/coreip-e34-rtl/metal.h index de80e1b..a77fc08 100644 --- a/bsp/coreip-e34-rtl/metal.h +++ b/bsp/coreip-e34-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -175,6 +175,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -195,6 +205,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -833,8 +853,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-e34-rtl/metal.ramrodata.lds b/bsp/coreip-e34-rtl/metal.ramrodata.lds index 6f9d52e..e75a025 100644 --- a/bsp/coreip-e34-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e34-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e34-rtl/metal.scratchpad.lds b/bsp/coreip-e34-rtl/metal.scratchpad.lds index d711300..d05f5c2 100644 --- a/bsp/coreip-e34-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e34-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e34-rtl/settings.mk b/bsp/coreip-e34-rtl/settings.mk index 715b312..dc10ea1 100644 --- a/bsp/coreip-e34-rtl/settings.mk +++ b/bsp/coreip-e34-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-e76-arty/design.dts b/bsp/coreip-e76-arty/design.dts index 1ea526f..c1ef3b2 100644 --- a/bsp/coreip-e76-arty/design.dts +++ b/bsp/coreip-e76-arty/design.dts @@ -28,6 +28,7 @@ next-level-cache = <&L14 &L15>; reg = <0x0>; riscv,isa = "rv32imafc"; + riscv,pmpregions = <8>; status = "okay"; timebase-frequency = <65000000>; hardware-exec-breakpoint-count = <4>; @@ -47,10 +48,6 @@ #size-cells = <1>; compatible = "SiFive,FE710G-soc", "fe710-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L2: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L4 3 &L4 7>; diff --git a/bsp/coreip-e76-arty/metal-inline.h b/bsp/coreip-e76-arty/metal-inline.h index bd8e58b..d1af334 100644 --- a/bsp/coreip-e76-arty/metal-inline.h +++ b/bsp/coreip-e76-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -28,8 +28,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -174,11 +176,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-e76-arty/metal-platform.h b/bsp/coreip-e76-arty/metal-platform.h index d99248d..a08971f 100644 --- a/bsp/coreip-e76-arty/metal-platform.h +++ b/bsp/coreip-e76-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E76_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e76-arty/metal.default.lds b/bsp/coreip-e76-arty/metal.default.lds index 5f18721..fc983a7 100644 --- a/bsp/coreip-e76-arty/metal.default.lds +++ b/bsp/coreip-e76-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e76-arty/metal.h b/bsp/coreip-e76-arty/metal.h index 21a9416..0c4f0eb 100644 --- a/bsp/coreip-e76-arty/metal.h +++ b/bsp/coreip-e76-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -106,7 +106,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -237,6 +237,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -257,6 +267,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -891,8 +911,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-e76-arty/metal.ramrodata.lds b/bsp/coreip-e76-arty/metal.ramrodata.lds index 2399c34..f53fd33 100644 --- a/bsp/coreip-e76-arty/metal.ramrodata.lds +++ b/bsp/coreip-e76-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e76-arty/metal.scratchpad.lds b/bsp/coreip-e76-arty/metal.scratchpad.lds index f218377..eadc43f 100644 --- a/bsp/coreip-e76-arty/metal.scratchpad.lds +++ b/bsp/coreip-e76-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk index 8f23cea..1e501a6 100644 --- a/bsp/coreip-e76-arty/settings.mk +++ b/bsp/coreip-e76-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-e76-rtl/design.dts b/bsp/coreip-e76-rtl/design.dts index 40c0004..25bd59c 100644 --- a/bsp/coreip-e76-rtl/design.dts +++ b/bsp/coreip-e76-rtl/design.dts @@ -21,6 +21,7 @@ next-level-cache = <&L9>; reg = <0x0>; riscv,isa = "rv32imafc"; + riscv,pmpregions = <8>; status = "okay"; timebase-frequency = <1000000>; hardware-exec-breakpoint-count = <4>; @@ -40,10 +41,6 @@ #size-cells = <1>; compatible = "SiFive,FE710G-soc", "fe710-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L11: axi4-periph-port@20000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/bsp/coreip-e76-rtl/metal-inline.h b/bsp/coreip-e76-rtl/metal-inline.h index fe18ce9..aef66bd 100644 --- a/bsp/coreip-e76-rtl/metal-inline.h +++ b/bsp/coreip-e76-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -27,8 +27,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -125,11 +127,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-e76-rtl/metal-platform.h b/bsp/coreip-e76-rtl/metal-platform.h index fc2e618..5513ead 100644 --- a/bsp/coreip-e76-rtl/metal-platform.h +++ b/bsp/coreip-e76-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E76_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e76-rtl/metal.default.lds b/bsp/coreip-e76-rtl/metal.default.lds index 84b0c14..f1317d6 100644 --- a/bsp/coreip-e76-rtl/metal.default.lds +++ b/bsp/coreip-e76-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -27,6 +27,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e76-rtl/metal.h b/bsp/coreip-e76-rtl/metal.h index 84e5823..903e53d 100644 --- a/bsp/coreip-e76-rtl/metal.h +++ b/bsp/coreip-e76-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -89,7 +89,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -165,6 +165,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -185,6 +195,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -746,8 +766,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-e76-rtl/metal.ramrodata.lds b/bsp/coreip-e76-rtl/metal.ramrodata.lds index 60429dd..11169de 100644 --- a/bsp/coreip-e76-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e76-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -27,6 +27,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e76-rtl/metal.scratchpad.lds b/bsp/coreip-e76-rtl/metal.scratchpad.lds index 84b0c14..f1317d6 100644 --- a/bsp/coreip-e76-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e76-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -27,6 +27,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e76-rtl/settings.mk b/bsp/coreip-e76-rtl/settings.mk index 0ef35b7..8f9bb0b 100644 --- a/bsp/coreip-e76-rtl/settings.mk +++ b/bsp/coreip-e76-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-s51-arty/design.dts b/bsp/coreip-s51-arty/design.dts index 7d8e0d2..3bcab05 100644 --- a/bsp/coreip-s51-arty/design.dts +++ b/bsp/coreip-s51-arty/design.dts @@ -25,6 +25,7 @@ next-level-cache = <&L10>; reg = <0x0>; riscv,isa = "rv64imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; @@ -47,10 +48,6 @@ compatible = "fixed-clock"; clock-frequency = <32500000>; }; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L2: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L4 3 &L4 7>; diff --git a/bsp/coreip-s51-arty/metal-inline.h b/bsp/coreip-s51-arty/metal-inline.h index 7fe8125..3d1cc63 100644 --- a/bsp/coreip-s51-arty/metal-inline.h +++ b/bsp/coreip-s51-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -28,8 +28,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -188,11 +190,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-s51-arty/metal-platform.h b/bsp/coreip-s51-arty/metal-platform.h index 2d97f6c..7edd9aa 100644 --- a/bsp/coreip-s51-arty/metal-platform.h +++ b/bsp/coreip-s51-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_S51_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s51-arty/metal.default.lds b/bsp/coreip-s51-arty/metal.default.lds index 82a199e..4a9e1be 100644 --- a/bsp/coreip-s51-arty/metal.default.lds +++ b/bsp/coreip-s51-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s51-arty/metal.h b/bsp/coreip-s51-arty/metal.h index 9d1a901..f5087cc 100644 --- a/bsp/coreip-s51-arty/metal.h +++ b/bsp/coreip-s51-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -109,7 +109,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -240,6 +240,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -260,6 +270,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -946,8 +966,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-s51-arty/metal.ramrodata.lds b/bsp/coreip-s51-arty/metal.ramrodata.lds index 22eeb0a..a280082 100644 --- a/bsp/coreip-s51-arty/metal.ramrodata.lds +++ b/bsp/coreip-s51-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s51-arty/metal.scratchpad.lds b/bsp/coreip-s51-arty/metal.scratchpad.lds index 808429b..16211dc 100644 --- a/bsp/coreip-s51-arty/metal.scratchpad.lds +++ b/bsp/coreip-s51-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk index a18cf05..4c84306 100644 --- a/bsp/coreip-s51-arty/settings.mk +++ b/bsp/coreip-s51-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv64imac diff --git a/bsp/coreip-s51-rtl/design.dts b/bsp/coreip-s51-rtl/design.dts index bbbab4d..3a7bf54 100644 --- a/bsp/coreip-s51-rtl/design.dts +++ b/bsp/coreip-s51-rtl/design.dts @@ -17,6 +17,7 @@ i-cache-size = <16384>; reg = <0x0>; riscv,isa = "rv64imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; @@ -34,10 +35,6 @@ #size-cells = <2>; compatible = "SiFive,FS510G-soc", "fs510-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L12: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; diff --git a/bsp/coreip-s51-rtl/metal-inline.h b/bsp/coreip-s51-rtl/metal-inline.h index 06b7384..43b1d7b 100644 --- a/bsp/coreip-s51-rtl/metal-inline.h +++ b/bsp/coreip-s51-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -27,8 +27,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -150,11 +152,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-s51-rtl/metal-platform.h b/bsp/coreip-s51-rtl/metal-platform.h index 009cad9..9d7ee51 100644 --- a/bsp/coreip-s51-rtl/metal-platform.h +++ b/bsp/coreip-s51-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_S51_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s51-rtl/metal.default.lds b/bsp/coreip-s51-rtl/metal.default.lds index e68e937..e5be410 100644 --- a/bsp/coreip-s51-rtl/metal.default.lds +++ b/bsp/coreip-s51-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s51-rtl/metal.h b/bsp/coreip-s51-rtl/metal.h index 6cf2856..3a90f6c 100644 --- a/bsp/coreip-s51-rtl/metal.h +++ b/bsp/coreip-s51-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -175,6 +175,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -195,6 +205,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -833,8 +853,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-s51-rtl/metal.ramrodata.lds b/bsp/coreip-s51-rtl/metal.ramrodata.lds index 448d7ed..e9f838a 100644 --- a/bsp/coreip-s51-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s51-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s51-rtl/metal.scratchpad.lds b/bsp/coreip-s51-rtl/metal.scratchpad.lds index 4d43737..e46abb7 100644 --- a/bsp/coreip-s51-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s51-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s51-rtl/settings.mk b/bsp/coreip-s51-rtl/settings.mk index b69debb..12a8c2e 100644 --- a/bsp/coreip-s51-rtl/settings.mk +++ b/bsp/coreip-s51-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv64imac diff --git a/bsp/coreip-s54-arty/design.dts b/bsp/coreip-s54-arty/design.dts index ae42f18..1ae14e2 100644 --- a/bsp/coreip-s54-arty/design.dts +++ b/bsp/coreip-s54-arty/design.dts @@ -25,6 +25,7 @@ next-level-cache = <&L10>; reg = <0x0>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; @@ -47,10 +48,6 @@ compatible = "fixed-clock"; clock-frequency = <32500000>; }; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L2: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L4 3 &L4 7>; diff --git a/bsp/coreip-s54-arty/metal-inline.h b/bsp/coreip-s54-arty/metal-inline.h index fee9bcd..b321a86 100644 --- a/bsp/coreip-s54-arty/metal-inline.h +++ b/bsp/coreip-s54-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -28,8 +28,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -188,11 +190,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-s54-arty/metal-platform.h b/bsp/coreip-s54-arty/metal-platform.h index 7f1e2d0..d044a65 100644 --- a/bsp/coreip-s54-arty/metal-platform.h +++ b/bsp/coreip-s54-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_S54_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s54-arty/metal.default.lds b/bsp/coreip-s54-arty/metal.default.lds index 82a199e..4a9e1be 100644 --- a/bsp/coreip-s54-arty/metal.default.lds +++ b/bsp/coreip-s54-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s54-arty/metal.h b/bsp/coreip-s54-arty/metal.h index fd36163..6973c1b 100644 --- a/bsp/coreip-s54-arty/metal.h +++ b/bsp/coreip-s54-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -109,7 +109,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -240,6 +240,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -260,6 +270,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -946,8 +966,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-s54-arty/metal.ramrodata.lds b/bsp/coreip-s54-arty/metal.ramrodata.lds index 22eeb0a..a280082 100644 --- a/bsp/coreip-s54-arty/metal.ramrodata.lds +++ b/bsp/coreip-s54-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s54-arty/metal.scratchpad.lds b/bsp/coreip-s54-arty/metal.scratchpad.lds index 808429b..16211dc 100644 --- a/bsp/coreip-s54-arty/metal.scratchpad.lds +++ b/bsp/coreip-s54-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s54-arty/settings.mk b/bsp/coreip-s54-arty/settings.mk index 1679ade..ded9d2f 100644 --- a/bsp/coreip-s54-arty/settings.mk +++ b/bsp/coreip-s54-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-02 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv64imafdc diff --git a/bsp/coreip-s54-rtl/design.dts b/bsp/coreip-s54-rtl/design.dts index f5a21b4..118fe04 100644 --- a/bsp/coreip-s54-rtl/design.dts +++ b/bsp/coreip-s54-rtl/design.dts @@ -17,6 +17,7 @@ i-cache-size = <16384>; reg = <0x0>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; @@ -34,10 +35,6 @@ #size-cells = <2>; compatible = "SiFive,FS540G-soc", "fs540-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L12: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; diff --git a/bsp/coreip-s54-rtl/metal-inline.h b/bsp/coreip-s54-rtl/metal-inline.h index 402ee7e..a04cbc1 100644 --- a/bsp/coreip-s54-rtl/metal-inline.h +++ b/bsp/coreip-s54-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -27,8 +27,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -150,11 +152,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-s54-rtl/metal-platform.h b/bsp/coreip-s54-rtl/metal-platform.h index 3906b83..2175c30 100644 --- a/bsp/coreip-s54-rtl/metal-platform.h +++ b/bsp/coreip-s54-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_S54_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s54-rtl/metal.default.lds b/bsp/coreip-s54-rtl/metal.default.lds index e68e937..e5be410 100644 --- a/bsp/coreip-s54-rtl/metal.default.lds +++ b/bsp/coreip-s54-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s54-rtl/metal.h b/bsp/coreip-s54-rtl/metal.h index 6d8e8e1..3880110 100644 --- a/bsp/coreip-s54-rtl/metal.h +++ b/bsp/coreip-s54-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -175,6 +175,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -195,6 +205,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -833,8 +853,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-s54-rtl/metal.ramrodata.lds b/bsp/coreip-s54-rtl/metal.ramrodata.lds index 448d7ed..e9f838a 100644 --- a/bsp/coreip-s54-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s54-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s54-rtl/metal.scratchpad.lds b/bsp/coreip-s54-rtl/metal.scratchpad.lds index 4d43737..e46abb7 100644 --- a/bsp/coreip-s54-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s54-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s54-rtl/settings.mk b/bsp/coreip-s54-rtl/settings.mk index 7602565..a25dc18 100644 --- a/bsp/coreip-s54-rtl/settings.mk +++ b/bsp/coreip-s54-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-03 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv64imafdc diff --git a/bsp/coreip-s76-arty/design.dts b/bsp/coreip-s76-arty/design.dts index b5af1f3..00ed9ee 100644 --- a/bsp/coreip-s76-arty/design.dts +++ b/bsp/coreip-s76-arty/design.dts @@ -28,6 +28,7 @@ next-level-cache = <&L14 &L15>; reg = <0x0>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; status = "okay"; timebase-frequency = <65000000>; hardware-exec-breakpoint-count = <4>; @@ -47,10 +48,6 @@ #size-cells = <1>; compatible = "SiFive,FS760G-soc", "fs710-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <1>; - }; L2: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L4 3 &L4 7>; diff --git a/bsp/coreip-s76-arty/metal-inline.h b/bsp/coreip-s76-arty/metal-inline.h index 6d4d486..56168da 100644 --- a/bsp/coreip-s76-arty/metal-inline.h +++ b/bsp/coreip-s76-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -28,8 +28,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -174,11 +176,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-s76-arty/metal-platform.h b/bsp/coreip-s76-arty/metal-platform.h index eda81f7..c849584 100644 --- a/bsp/coreip-s76-arty/metal-platform.h +++ b/bsp/coreip-s76-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_S76_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s76-arty/metal.default.lds b/bsp/coreip-s76-arty/metal.default.lds index 5f18721..fc983a7 100644 --- a/bsp/coreip-s76-arty/metal.default.lds +++ b/bsp/coreip-s76-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s76-arty/metal.h b/bsp/coreip-s76-arty/metal.h index 7c64fc7..87f6ae5 100644 --- a/bsp/coreip-s76-arty/metal.h +++ b/bsp/coreip-s76-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -106,7 +106,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -237,6 +237,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -257,6 +267,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -891,8 +911,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-s76-arty/metal.ramrodata.lds b/bsp/coreip-s76-arty/metal.ramrodata.lds index 2399c34..f53fd33 100644 --- a/bsp/coreip-s76-arty/metal.ramrodata.lds +++ b/bsp/coreip-s76-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s76-arty/metal.scratchpad.lds b/bsp/coreip-s76-arty/metal.scratchpad.lds index f218377..eadc43f 100644 --- a/bsp/coreip-s76-arty/metal.scratchpad.lds +++ b/bsp/coreip-s76-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s76-arty/settings.mk b/bsp/coreip-s76-arty/settings.mk index a3f9bc1..ded9d2f 100644 --- a/bsp/coreip-s76-arty/settings.mk +++ b/bsp/coreip-s76-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-03 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv64imafdc diff --git a/bsp/coreip-s76-rtl/design.dts b/bsp/coreip-s76-rtl/design.dts index a4fd9c8..690b6a4 100644 --- a/bsp/coreip-s76-rtl/design.dts +++ b/bsp/coreip-s76-rtl/design.dts @@ -21,6 +21,7 @@ next-level-cache = <&L9>; reg = <0x0>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; status = "okay"; timebase-frequency = <1000000>; hardware-exec-breakpoint-count = <4>; @@ -40,10 +41,6 @@ #size-cells = <2>; compatible = "SiFive,FS760G-soc", "fs710-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L11: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; diff --git a/bsp/coreip-s76-rtl/metal-inline.h b/bsp/coreip-s76-rtl/metal-inline.h index 1d139e1..57d7a4d 100644 --- a/bsp/coreip-s76-rtl/metal-inline.h +++ b/bsp/coreip-s76-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -27,8 +27,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -125,11 +127,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-s76-rtl/metal-platform.h b/bsp/coreip-s76-rtl/metal-platform.h index 2d911a5..ca0320d 100644 --- a/bsp/coreip-s76-rtl/metal-platform.h +++ b/bsp/coreip-s76-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_S76_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s76-rtl/metal.default.lds b/bsp/coreip-s76-rtl/metal.default.lds index 84b0c14..f1317d6 100644 --- a/bsp/coreip-s76-rtl/metal.default.lds +++ b/bsp/coreip-s76-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -27,6 +27,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s76-rtl/metal.h b/bsp/coreip-s76-rtl/metal.h index 3221ed3..7b092fc 100644 --- a/bsp/coreip-s76-rtl/metal.h +++ b/bsp/coreip-s76-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -89,7 +89,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -165,6 +165,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -185,6 +195,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -746,8 +766,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-s76-rtl/metal.ramrodata.lds b/bsp/coreip-s76-rtl/metal.ramrodata.lds index 60429dd..11169de 100644 --- a/bsp/coreip-s76-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s76-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -27,6 +27,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s76-rtl/metal.scratchpad.lds b/bsp/coreip-s76-rtl/metal.scratchpad.lds index 84b0c14..f1317d6 100644 --- a/bsp/coreip-s76-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s76-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -27,6 +27,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-s76-rtl/settings.mk b/bsp/coreip-s76-rtl/settings.mk index 7602565..a25dc18 100644 --- a/bsp/coreip-s76-rtl/settings.mk +++ b/bsp/coreip-s76-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-03 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv64imafdc diff --git a/bsp/coreip-u54-rtl/design.dts b/bsp/coreip-u54-rtl/design.dts index b773072..154dc42 100644 --- a/bsp/coreip-u54-rtl/design.dts +++ b/bsp/coreip-u54-rtl/design.dts @@ -26,6 +26,7 @@ next-level-cache = <&L16>; reg = <0x0>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L6>; status = "okay"; timebase-frequency = <1000000>; @@ -46,10 +47,6 @@ #size-cells = <2>; compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L13: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; diff --git a/bsp/coreip-u54-rtl/metal-inline.h b/bsp/coreip-u54-rtl/metal-inline.h index 03d29e6..3d08799 100644 --- a/bsp/coreip-u54-rtl/metal-inline.h +++ b/bsp/coreip-u54-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -27,8 +27,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -136,11 +138,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-u54-rtl/metal-platform.h b/bsp/coreip-u54-rtl/metal-platform.h index 562f263..fb3d3b4 100644 --- a/bsp/coreip-u54-rtl/metal-platform.h +++ b/bsp/coreip-u54-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef COREIP_U54_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From cache_controller@2010000 */ #define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL #define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL diff --git a/bsp/coreip-u54-rtl/metal.default.lds b/bsp/coreip-u54-rtl/metal.default.lds index 3a5705a..93fc5a8 100644 --- a/bsp/coreip-u54-rtl/metal.default.lds +++ b/bsp/coreip-u54-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-u54-rtl/metal.h b/bsp/coreip-u54-rtl/metal.h index 0621896..7e793bc 100644 --- a/bsp/coreip-u54-rtl/metal.h +++ b/bsp/coreip-u54-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -92,7 +92,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -171,6 +171,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -191,6 +201,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -759,8 +779,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-u54-rtl/metal.ramrodata.lds b/bsp/coreip-u54-rtl/metal.ramrodata.lds index 2873493..57b767a 100644 --- a/bsp/coreip-u54-rtl/metal.ramrodata.lds +++ b/bsp/coreip-u54-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-u54-rtl/metal.scratchpad.lds b/bsp/coreip-u54-rtl/metal.scratchpad.lds index 3a5705a..93fc5a8 100644 --- a/bsp/coreip-u54-rtl/metal.scratchpad.lds +++ b/bsp/coreip-u54-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-u54-rtl/settings.mk b/bsp/coreip-u54-rtl/settings.mk index 9ae1de9..4cf87cb 100644 --- a/bsp/coreip-u54-rtl/settings.mk +++ b/bsp/coreip-u54-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-03 # +# [XXXXX] 23-05-2019 13-29-50 # # ----------------------------------- # RISCV_ARCH=rv64imafdc diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts index 27a3c94..2982dd5 100644 --- a/bsp/coreip-u54mc-rtl/design.dts +++ b/bsp/coreip-u54mc-rtl/design.dts @@ -5,6 +5,9 @@ #size-cells = <2>; compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev"; model = "SiFive,FU540G"; + chosen { + metal,boothart = <&L13>; + }; L36: cpus { #address-cells = <1>; #size-cells = <0>; @@ -18,6 +21,7 @@ next-level-cache = <&L33>; reg = <0x0>; riscv,isa = "rv64imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L7>; sifive,itim = <&L6>; status = "okay"; @@ -46,6 +50,7 @@ next-level-cache = <&L33>; reg = <0x1>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L11>; status = "okay"; timebase-frequency = <1000000>; @@ -74,6 +79,7 @@ next-level-cache = <&L33>; reg = <0x2>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L15>; status = "okay"; timebase-frequency = <1000000>; @@ -102,6 +108,7 @@ next-level-cache = <&L33>; reg = <0x3>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L19>; status = "okay"; timebase-frequency = <1000000>; @@ -130,6 +137,7 @@ next-level-cache = <&L33>; reg = <0x4>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L23>; status = "okay"; timebase-frequency = <1000000>; @@ -150,10 +158,6 @@ #size-cells = <2>; compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L30: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; diff --git a/bsp/coreip-u54mc-rtl/metal-inline.h b/bsp/coreip-u54mc-rtl/metal-inline.h index 58f8acc..34e4d33 100644 --- a/bsp/coreip-u54mc-rtl/metal-inline.h +++ b/bsp/coreip-u54mc-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -27,8 +27,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -235,11 +237,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-u54mc-rtl/metal-platform.h b/bsp/coreip-u54mc-rtl/metal-platform.h index 6df003f..7045d23 100644 --- a/bsp/coreip-u54mc-rtl/metal-platform.h +++ b/bsp/coreip-u54mc-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_U54MC_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From cache_controller@2010000 */ #define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL #define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL diff --git a/bsp/coreip-u54mc-rtl/metal.default.lds b/bsp/coreip-u54mc-rtl/metal.default.lds index ea7c853..a95cc07 100644 --- a/bsp/coreip-u54mc-rtl/metal.default.lds +++ b/bsp/coreip-u54mc-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 1); .init : diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h index dab7ff4..417332f 100644 --- a/bsp/coreip-u54mc-rtl/metal.h +++ b/bsp/coreip-u54mc-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -122,7 +122,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -249,6 +249,28 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) { + return 1; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) { + return 2; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) { + return 3; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -293,6 +315,28 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -912,8 +956,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds index 2dca5ed..b5f35f7 100644 --- a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds +++ b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 1); .init : diff --git a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds index ea7c853..a95cc07 100644 --- a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds +++ b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 1); .init : diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk index 7da27c4..ae9e038 100644 --- a/bsp/coreip-u54mc-rtl/settings.mk +++ b/bsp/coreip-u54mc-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-03 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv64imac diff --git a/bsp/freedom-e310-arty/metal-inline.h b/bsp/freedom-e310-arty/metal-inline.h index b2f329f..fafb3ec 100644 --- a/bsp/freedom-e310-arty/metal-inline.h +++ b/bsp/freedom-e310-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -28,8 +28,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/freedom-e310-arty/metal-platform.h b/bsp/freedom-e310-arty/metal-platform.h index 6ef2099..35d7e0a 100644 --- a/bsp/freedom-e310-arty/metal-platform.h +++ b/bsp/freedom-e310-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef FREEDOM_E310_ARTY__METAL_PLATFORM_H diff --git a/bsp/freedom-e310-arty/metal.default.lds b/bsp/freedom-e310-arty/metal.default.lds index d331a7b..f9dcdbd 100644 --- a/bsp/freedom-e310-arty/metal.default.lds +++ b/bsp/freedom-e310-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/freedom-e310-arty/metal.h b/bsp/freedom-e310-arty/metal.h index 50c05a4..c1c3dca 100644 --- a/bsp/freedom-e310-arty/metal.h +++ b/bsp/freedom-e310-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -192,6 +192,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -212,6 +222,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/freedom-e310-arty/metal.ramrodata.lds b/bsp/freedom-e310-arty/metal.ramrodata.lds index ee6ae00..d5d7b5b 100644 --- a/bsp/freedom-e310-arty/metal.ramrodata.lds +++ b/bsp/freedom-e310-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/freedom-e310-arty/metal.scratchpad.lds b/bsp/freedom-e310-arty/metal.scratchpad.lds index 5a6d82d..dfdf485 100644 --- a/bsp/freedom-e310-arty/metal.scratchpad.lds +++ b/bsp/freedom-e310-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/freedom-e310-arty/settings.mk b/bsp/freedom-e310-arty/settings.mk index da84dbc..d3d0bfc 100644 --- a/bsp/freedom-e310-arty/settings.mk +++ b/bsp/freedom-e310-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-03 # +# [XXXXX] 23-05-2019 13-29-50 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/sifive-hifive-unleashed/design.dts b/bsp/sifive-hifive-unleashed/design.dts index ee6897f..8702be3 100644 --- a/bsp/sifive-hifive-unleashed/design.dts +++ b/bsp/sifive-hifive-unleashed/design.dts @@ -33,6 +33,7 @@ next-level-cache = <&L24 &L0>; reg = <0>; riscv,isa = "rv64imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L8>; sifive,itim = <&L7>; status = "okay"; @@ -60,6 +61,7 @@ next-level-cache = <&L24 &L0>; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L11>; status = "okay"; tlb-split; @@ -87,6 +89,7 @@ next-level-cache = <&L24 &L0>; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L14>; status = "okay"; tlb-split; @@ -114,6 +117,7 @@ next-level-cache = <&L24 &L0>; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L17>; status = "okay"; tlb-split; @@ -141,6 +145,7 @@ next-level-cache = <&L24 &L0>; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L20>; status = "okay"; tlb-split; @@ -160,10 +165,6 @@ #size-cells = <2>; compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <1>; - }; refclk: refclk { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/bsp/sifive-hifive-unleashed/metal-inline.h b/bsp/sifive-hifive-unleashed/metal-inline.h index 6968bab..dcc51cb 100644 --- a/bsp/sifive-hifive-unleashed/metal-inline.h +++ b/bsp/sifive-hifive-unleashed/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -31,8 +31,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -295,11 +297,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From gpio@10060000 */ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = { .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio, diff --git a/bsp/sifive-hifive-unleashed/metal-platform.h b/bsp/sifive-hifive-unleashed/metal-platform.h index 0a1d909..4bfe75b 100644 --- a/bsp/sifive-hifive-unleashed/metal-platform.h +++ b/bsp/sifive-hifive-unleashed/metal-platform.h @@ -1,17 +1,20 @@ +/* Copyright 2019 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +/* ----------------------------------- */ +/* [XXXXX] 23-05-2019 13-29-50 */ +/* ----------------------------------- */ + #ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H #define SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H /* From refclk */ #define METAL_FIXED_CLOCK__CLOCK_FREQUENCY 33333333UL -#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 33333333UL #define METAL_FIXED_CLOCK /* From tlclk */ #define METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV 2UL -#define METAL_FIXED_FACTOR_CLOCK_0_CLOCK_DIV 2UL #define METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT 1UL -#define METAL_FIXED_FACTOR_CLOCK_0_CLOCK_MULT 1UL #define METAL_FIXED_FACTOR_CLOCK @@ -43,12 +46,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL -#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL - -#define METAL_RISCV_PMP - /* From cache_controller@2010000 */ #define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL #define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds index b4c68be..23351d2 100644 --- a/bsp/sifive-hifive-unleashed/metal.default.lds +++ b/bsp/sifive-hifive-unleashed/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/sifive-hifive-unleashed/metal.h b/bsp/sifive-hifive-unleashed/metal.h index e72a3db..4154037 100644 --- a/bsp/sifive-hifive-unleashed/metal.h +++ b/bsp/sifive-hifive-unleashed/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -141,7 +141,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From gpio@10060000 */ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000; @@ -318,6 +318,28 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) { + return 1; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) { + return 2; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) { + return 3; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -362,6 +384,28 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -777,8 +821,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) #define __MEE_DT_MAX_GPIOS 1 diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds index 3301bb0..4b31408 100644 --- a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds +++ b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds index cf43226..48d397f 100644 --- a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds +++ b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/sifive-hifive-unleashed/settings.mk b/bsp/sifive-hifive-unleashed/settings.mk index 07f05fd..2745538 100644 --- a/bsp/sifive-hifive-unleashed/settings.mk +++ b/bsp/sifive-hifive-unleashed/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-03 # +# [XXXXX] 23-05-2019 13-29-50 # # ----------------------------------- # RISCV_ARCH=rv64imac diff --git a/bsp/sifive-hifive1-revb/design.dts b/bsp/sifive-hifive1-revb/design.dts index 0e48622..970d3be 100644 --- a/bsp/sifive-hifive1-revb/design.dts +++ b/bsp/sifive-hifive1-revb/design.dts @@ -25,6 +25,7 @@ next-level-cache = <&spi0>; reg = <0>; riscv,isa = "rv32imac"; + riscv,pmpregions = <8>; sifive,dtim = <&dtim>; status = "okay"; timebase-frequency = <1000000>; @@ -43,12 +44,6 @@ #clock-cells = <1>; compatible = "sifive,hifive1"; ranges; - - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; - hfxoscin: clock@0 { #clock-cells = <0>; compatible = "fixed-clock"; diff --git a/bsp/sifive-hifive1-revb/metal-inline.h b/bsp/sifive-hifive1-revb/metal-inline.h index f159c90..5f341a0 100644 --- a/bsp/sifive-hifive1-revb/metal-inline.h +++ b/bsp/sifive-hifive1-revb/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -28,8 +28,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -188,11 +190,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/sifive-hifive1-revb/metal-platform.h b/bsp/sifive-hifive1-revb/metal-platform.h index 1353847..3e0f3b9 100644 --- a/bsp/sifive-hifive1-revb/metal-platform.h +++ b/bsp/sifive-hifive1-revb/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef SIFIVE_HIFIVE1_REVB__METAL_PLATFORM_H @@ -46,11 +46,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From aon@10000000 */ #define METAL_SIFIVE_AON0_10000000_BASE_ADDRESS 268435456UL #define METAL_SIFIVE_AON0_0_BASE_ADDRESS 268435456UL diff --git a/bsp/sifive-hifive1-revb/metal.default.lds b/bsp/sifive-hifive1-revb/metal.default.lds index 972ba9c..dcbff03 100644 --- a/bsp/sifive-hifive1-revb/metal.default.lds +++ b/bsp/sifive-hifive1-revb/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/sifive-hifive1-revb/metal.h b/bsp/sifive-hifive1-revb/metal.h index baf508e..7a111a2 100644 --- a/bsp/sifive-hifive1-revb/metal.h +++ b/bsp/sifive-hifive1-revb/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -111,7 +111,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -230,6 +230,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -250,6 +260,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -804,8 +824,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/sifive-hifive1-revb/metal.ramrodata.lds b/bsp/sifive-hifive1-revb/metal.ramrodata.lds index 558b219..014fe70 100644 --- a/bsp/sifive-hifive1-revb/metal.ramrodata.lds +++ b/bsp/sifive-hifive1-revb/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/sifive-hifive1-revb/metal.scratchpad.lds b/bsp/sifive-hifive1-revb/metal.scratchpad.lds index 05948a2..13a357e 100644 --- a/bsp/sifive-hifive1-revb/metal.scratchpad.lds +++ b/bsp/sifive-hifive1-revb/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk index fbfcb79..d793c1d 100644 --- a/bsp/sifive-hifive1-revb/settings.mk +++ b/bsp/sifive-hifive1-revb/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-03 # +# [XXXXX] 23-05-2019 13-29-50 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/sifive-hifive1/metal-inline.h b/bsp/sifive-hifive1/metal-inline.h index 117bff9..10470c7 100644 --- a/bsp/sifive-hifive1/metal-inline.h +++ b/bsp/sifive-hifive1/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -28,8 +28,10 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/sifive-hifive1/metal-platform.h b/bsp/sifive-hifive1/metal-platform.h index f63b445..0bda7f1 100644 --- a/bsp/sifive-hifive1/metal-platform.h +++ b/bsp/sifive-hifive1/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef SIFIVE_HIFIVE1__METAL_PLATFORM_H diff --git a/bsp/sifive-hifive1/metal.default.lds b/bsp/sifive-hifive1/metal.default.lds index 7346fd0..3b27dd0 100644 --- a/bsp/sifive-hifive1/metal.default.lds +++ b/bsp/sifive-hifive1/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/sifive-hifive1/metal.h b/bsp/sifive-hifive1/metal.h index 39d733d..29f6127 100644 --- a/bsp/sifive-hifive1/metal.h +++ b/bsp/sifive-hifive1/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -228,6 +228,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { @@ -248,6 +258,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/sifive-hifive1/metal.ramrodata.lds b/bsp/sifive-hifive1/metal.ramrodata.lds index 00bc224..2f49231 100644 --- a/bsp/sifive-hifive1/metal.ramrodata.lds +++ b/bsp/sifive-hifive1/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/sifive-hifive1/metal.scratchpad.lds b/bsp/sifive-hifive1/metal.scratchpad.lds index 7a716d7..cb27d7e 100644 --- a/bsp/sifive-hifive1/metal.scratchpad.lds +++ b/bsp/sifive-hifive1/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 23-05-2019 13-29-50 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk index b4b69dc..6b305de 100644 --- a/bsp/sifive-hifive1/settings.mk +++ b/bsp/sifive-hifive1/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 22-05-2019 00-09-03 # +# [XXXXX] 23-05-2019 13-29-50 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/freedom-metal b/freedom-metal -Subproject 1c091eac4c18c4988a0551d63bfcf4b835fb421 +Subproject 66dc596a9a8ae9aef3380e068c17e5a5a6362ca diff --git a/scripts/fixup-dts b/scripts/fixup-dts index 005c5de..278b835 100755 --- a/scripts/fixup-dts +++ b/scripts/fixup-dts @@ -43,7 +43,7 @@ if [ `grep -c 'riscv,pmp' ${dts}` -eq 0 ]; then $TARGET != "coreip-e20-rtl" -a \ $TARGET != "coreip-e20-arty" ]; then - ${SED} -i 's/ranges;/ranges;\n\t\tpmp: pmp@0 {\n\t\t\tcompatible = "riscv,pmp";\n\t\t\tregions = <1>;\n\t\t};/' ${dts} + ${SED} -i '/riscv,isa/a riscv,pmpregions = <1>;' ${dts} echo -e "$0: \tAdded pmp@0" fi diff --git a/software/example-pmp b/software/example-pmp -Subproject 7f49ff4dc12f3cc81814507d24eb36017dccabd +Subproject 496a081ab983c6558e17053682bd14f611c2846 diff --git a/software/example-user-mode b/software/example-user-mode new file mode 160000 +Subproject 262b4ec4f928a80a1d6f941cc257616ed235188 diff --git a/software/example-user-syscall b/software/example-user-syscall new file mode 160000 +Subproject e4110601669ef7db1b789b08e92d5b81f27d91a diff --git a/software/software-interrupt b/software/software-interrupt -Subproject 02fcd09838d28fbffbac437357e4dde2973f07f +Subproject f78801f451a73bd76081a5c28349cdc28756e70 diff --git a/software/timer-interrupt b/software/timer-interrupt -Subproject 6ddaeff553a71c6218f42b72e93f7f05347dca2 +Subproject adef8e7476a93e79a5c6ec9a05ae19d42d53bb9 |