diff options
| author | Megan Wachs <megan@sifive.com> | 2017-05-04 05:46:05 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2017-05-04 05:46:05 -0700 |
| commit | 4d5cbec9118cbedf2d4ae5b54acaa22862245a4c (patch) | |
| tree | bb197ca9ef8f9265a79485f3a13e4e921a0ff93b | |
| parent | 3a01ac1b7c0e72c04679f0cd6552c4ff0b308863 (diff) | |
Update SDK For E31/E51 Coreplex IP Evaluation
60 files changed, 3589 insertions, 186 deletions
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<nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> + <linkedResources> + <link> + <name>bsp</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>demo_gpio.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/software/demo_gpio/demo_gpio.c</locationURI> + </link> + <link> + <name>bsp/.DS_Store</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/.DS_Store</locationURI> + </link> + <link> + <name>bsp/drivers</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>bsp/env</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>bsp/include</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>bsp/drivers/fe300prci</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>bsp/drivers/plic</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>bsp/env/.DS_Store</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/.DS_Store</locationURI> + </link> + <link> + <name>bsp/env/encoding.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/encoding.h</locationURI> + </link> + <link> + <name>bsp/env/entry.S</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/entry.S</locationURI> + </link> + <link> + <name>bsp/env/freedom-e300-hifive1</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>bsp/env/hifive1.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/hifive1.h</locationURI> + </link> + <link> + <name>bsp/env/start.S</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI> + </link> + <link> + <name>bsp/include/.DS_Store</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/.DS_Store</locationURI> + </link> + <link> + <name>bsp/include/sifive</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>bsp/drivers/fe300prci/fe300prci_driver.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c</locationURI> + </link> + <link> + <name>bsp/drivers/fe300prci/fe300prci_driver.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.h</locationURI> + </link> + <link> + <name>bsp/drivers/plic/plic_driver.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.c</locationURI> + </link> + <link> + <name>bsp/drivers/plic/plic_driver.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.h</locationURI> + </link> + <link> + <name>bsp/env/freedom-e300-hifive1/init.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/init.c</locationURI> + </link> + <link> + <name>bsp/env/freedom-e300-hifive1/link.lds</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/link.lds</locationURI> + </link> + <link> + <name>bsp/env/freedom-e300-hifive1/openocd.cfg</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/openocd.cfg</locationURI> + </link> + <link> + <name>bsp/env/freedom-e300-hifive1/platform.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/platform.h</locationURI> + </link> + <link> + <name>bsp/env/freedom-e300-hifive1/settings.mk</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/freedom-e300-hifive1/settings.mk</locationURI> + </link> + <link> + <name>bsp/include/sifive/.DS_Store</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/.DS_Store</locationURI> + </link> + <link> + <name>bsp/include/sifive/bits.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/const.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>bsp/include/sifive/sections.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/smp.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/aon.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/clint.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/gpio.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/otp.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/plic.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/prci.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/pwm.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/spi.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/uart.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI> + </link> + </linkedResources> +</projectDescription> diff --git a/FreedomStudio/HiFive1/demo_gpio/link.lds b/FreedomStudio/HiFive1/demo_gpio/link.lds new file mode 100644 index 0000000..90e5c8f --- /dev/null +++ b/FreedomStudio/HiFive1/demo_gpio/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/FreedomStudio/HiFive1/demo_gpio/openocd.cfg b/FreedomStudio/HiFive1/demo_gpio/openocd.cfg new file mode 100644 index 0000000..b0a8e26 --- /dev/null +++ b/FreedomStudio/HiFive1/demo_gpio/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +flash protect 0 64 last off diff --git a/FreedomStudio/HiFive1/hello/.DS_Store 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<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/gpio.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/otp.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/plic.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/prci.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/pwm.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/spi.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/uart.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI> + </link> + </linkedResources> +</projectDescription> diff --git a/FreedomStudio/HiFive1/hello/hello OpenOCD.launch b/FreedomStudio/HiFive1/hello/hello OpenOCD.launch new file mode 100644 index 0000000..96ab4ab --- /dev/null +++ b/FreedomStudio/HiFive1/hello/hello OpenOCD.launch @@ -0,0 +1,59 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<launchConfiguration type="ilg.gnuarmeclipse.debug.gdbjtag.openocd.launchConfigurationType"> +<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doContinue" value="true"/> +<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/> +<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/> +<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/> +<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/> +<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/> +<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/> +<booleanAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/> +<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.firstResetType" value="init"/> +<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off set arch riscv:rv32"/> +<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/> +<stringAttribute key="ilg.gnuarmeclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/> +<stringAttribute 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key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/hello.elf"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="hello"/> +<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="org.eclipse.cdt.cross.riscv.gnu.linux.elf.debug.83943911"/> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> +<listEntry value="/hello"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> +<listEntry value="4"/> +</listAttribute> +<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/> +<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/> +</launchConfiguration> diff --git a/FreedomStudio/HiFive1/hello/link.lds b/FreedomStudio/HiFive1/hello/link.lds new file mode 100644 index 0000000..90e5c8f --- /dev/null +++ b/FreedomStudio/HiFive1/hello/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/FreedomStudio/HiFive1/hello/openocd.cfg b/FreedomStudio/HiFive1/hello/openocd.cfg new file mode 100644 index 0000000..b0a8e26 --- /dev/null +++ b/FreedomStudio/HiFive1/hello/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +flash protect 0 64 last off diff --git a/FreedomStudio/HiFive1/led_fade/.cproject b/FreedomStudio/HiFive1/led_fade/.cproject new file mode 100644 index 0000000..0d35964 --- /dev/null +++ b/FreedomStudio/HiFive1/led_fade/.cproject @@ -0,0 +1,164 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> + <storageModule moduleId="org.eclipse.cdt.core.settings"> + <cconfiguration id="org.eclipse.cdt.cross.riscv.gnu.linux.elf.debug.83943911"> + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="org.eclipse.cdt.cross.riscv.gnu.linux.elf.debug.83943911" moduleId="org.eclipse.cdt.core.settings" name="Debug"> + <externalSettings/> + <extensions> + <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/> + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension 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+ </link> + <link> + <name>bsp/include/sifive/devices/spi.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/uart.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI> + </link> + </linkedResources> +</projectDescription> diff --git a/FreedomStudio/HiFive1/led_fade/link.lds b/FreedomStudio/HiFive1/led_fade/link.lds new file mode 100644 index 0000000..90e5c8f --- /dev/null +++ b/FreedomStudio/HiFive1/led_fade/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/FreedomStudio/HiFive1/led_fade/openocd.cfg b/FreedomStudio/HiFive1/led_fade/openocd.cfg new file mode 100644 index 0000000..b0a8e26 --- /dev/null +++ b/FreedomStudio/HiFive1/led_fade/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +flash protect 0 64 last off diff --git a/FreedomStudio/HiFive1/wrap-hifive1/.cproject b/FreedomStudio/HiFive1/wrap-hifive1/.cproject new file mode 100644 index 0000000..3ac5b88 --- /dev/null +++ b/FreedomStudio/HiFive1/wrap-hifive1/.cproject @@ -0,0 +1,134 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> + <storageModule moduleId="org.eclipse.cdt.core.settings"> + <cconfiguration id="org.eclipse.cdt.cross.riscv.gnu.linux.lib.debug.790194276"> + <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="org.eclipse.cdt.cross.riscv.gnu.linux.lib.debug.790194276" moduleId="org.eclipse.cdt.core.settings" name="Debug"> + <externalSettings/> + <extensions> + <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/> + <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> + <extension id="org.eclipse.cdt.core.GmakeErrorParser" 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superClass="org.eclipse.cdt.cross.riscv.gnu.linux.lib.cpp.compiler.release"> + <option id="org.eclipse.cdt.cross.riscv.gnu.cpp.compiler.option.optimization.level.532043722" name="Optimization level" superClass="org.eclipse.cdt.cross.riscv.gnu.cpp.compiler.option.optimization.level" value="org.eclipse.cdt.cross.riscv.gnu.base.option.optimization.level.size" valueType="enumerated"/> + </tool> + <tool id="org.eclipse.cdt.cross.riscv.gnu.linux.c.linker.base.1922804254" name="RISC-V GCC/Newlib C Linker" superClass="org.eclipse.cdt.cross.riscv.gnu.linux.c.linker.base"> + <inputType id="org.eclipse.cdt.cross.riscv.gnu.c.linker.input.2018904841" superClass="org.eclipse.cdt.cross.riscv.gnu.c.linker.input"> + <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/> + <additionalInput kind="additionalinput" paths="$(LIBS)"/> + </inputType> + </tool> + <tool id="org.eclipse.cdt.cross.riscv.gnu.linux.cpp.linker.base.1855221285" name="RISC-V GCC/Newlib C++ Linker" superClass="org.eclipse.cdt.cross.riscv.gnu.linux.cpp.linker.base"/> + <tool id="org.eclipse.cdt.cross.riscv.gnu.linux.lib.archiver.release.515125988" name="RISC-V GCC/Newlib Archiver" superClass="org.eclipse.cdt.cross.riscv.gnu.linux.lib.archiver.release"/> + <tool id="org.eclipse.cdt.cross.riscv.gnu.linux.createflash.base.1609461089" name="RISC-V GCC/Newlib GNU Create Flash Image" superClass="org.eclipse.cdt.cross.riscv.gnu.linux.createflash.base"/> + <tool id="org.eclipse.cdt.cross.riscv.gnu.linux.createlisting.base.929383567" name="RISC-V GCC/Newlib Create Listing" superClass="org.eclipse.cdt.cross.riscv.gnu.linux.createlisting.base"/> + <tool id="org.eclipse.cdt.cross.riscv.gnu.linux.printsize.base.437482602" name="RISC-V GCC/Newlib Print Size" superClass="org.eclipse.cdt.cross.riscv.gnu.linux.printsize.base"/> + </toolChain> + </folderInfo> + </configuration> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> + </cconfiguration> + </storageModule> + <storageModule moduleId="cdtBuildSystem" version="4.0.0"> + <project id="libwrap.org.eclipse.cdt.cross.riscv.gnu.linux.lib.786104060" name="RISC-V Embedded Static Library" projectType="org.eclipse.cdt.cross.riscv.gnu.linux.lib"/> + </storageModule> + <storageModule moduleId="scannerConfiguration"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> + <scannerConfigBuildInfo instanceId="org.eclipse.cdt.cross.riscv.gnu.linux.lib.debug.790194276;org.eclipse.cdt.cross.riscv.gnu.linux.lib.debug.790194276.;org.eclipse.cdt.cross.riscv.gnu.linux.lib.c.compiler.debug.485151753;org.eclipse.cdt.cross.riscv.gnu.linux.c.compiler.base.input.838444757"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.riscv.gnu.RISCV_GCCManagedMakePerProjectProfileC"/> + </scannerConfigBuildInfo> + <scannerConfigBuildInfo instanceId="org.eclipse.cdt.cross.riscv.gnu.linux.lib.release.944688491;org.eclipse.cdt.cross.riscv.gnu.linux.lib.release.944688491.;org.eclipse.cdt.cross.riscv.gnu.linux.lib.c.compiler.release.2142822111;org.eclipse.cdt.cross.riscv.gnu.linux.c.compiler.base.input.1718877038"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.riscv.gnu.RISCV_GCCManagedMakePerProjectProfileC"/> + </scannerConfigBuildInfo> + <scannerConfigBuildInfo instanceId="org.eclipse.cdt.cross.riscv.gnu.linux.lib.debug.790194276;org.eclipse.cdt.cross.riscv.gnu.linux.lib.debug.790194276.;org.eclipse.cdt.cross.riscv.gnu.linux.lib.assembler.debug.547900475;org.eclipse.cdt.cross.riscv.gnu.linux.assembler.base.input.196452118"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.riscv.gnu.RISCV_GCCManagedMakePerProjectProfileC"/> + </scannerConfigBuildInfo> + <scannerConfigBuildInfo instanceId="org.eclipse.cdt.cross.riscv.gnu.linux.lib.release.944688491;org.eclipse.cdt.cross.riscv.gnu.linux.lib.release.944688491.;org.eclipse.cdt.cross.riscv.gnu.linux.lib.assembler.release.1521212733;org.eclipse.cdt.cross.riscv.gnu.linux.assembler.base.input.1006284223"> + <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.cross.riscv.gnu.RISCV_GCCManagedMakePerProjectProfileC"/> + </scannerConfigBuildInfo> + </storageModule> + <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> + <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/> + <storageModule moduleId="refreshScope"/> +</cproject> diff --git a/FreedomStudio/HiFive1/wrap-hifive1/.gitignore b/FreedomStudio/HiFive1/wrap-hifive1/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/FreedomStudio/HiFive1/wrap-hifive1/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/FreedomStudio/HiFive1/wrap-hifive1/.project b/FreedomStudio/HiFive1/wrap-hifive1/.project new file mode 100644 index 0000000..431aed3 --- /dev/null +++ b/FreedomStudio/HiFive1/wrap-hifive1/.project @@ -0,0 +1,153 @@ +<?xml version="1.0" encoding="UTF-8"?> +<projectDescription> + <name>wrap-hifive1</name> + <comment></comment> + <projects> + </projects> + <buildSpec> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> + <triggers>clean,full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + <buildCommand> + <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> + <triggers>full,incremental,</triggers> + <arguments> + </arguments> + </buildCommand> + </buildSpec> + <natures> + <nature>org.eclipse.cdt.core.cnature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> + <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> + </natures> + <linkedResources> + <link> + <name>misc</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>stdlib</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>sys</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>misc/write_hex.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI> + </link> + <link> + <name>stdlib/malloc.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI> + </link> + <link> + <name>sys/_exit.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI> + </link> + <link> + <name>sys/close.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI> + </link> + <link> + <name>sys/execve.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI> + </link> + <link> + <name>sys/fork.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI> + </link> + <link> + <name>sys/fstat.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI> + </link> + <link> + <name>sys/getpid.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI> + </link> + <link> + <name>sys/isatty.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI> + </link> + <link> + <name>sys/kill.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI> + </link> + <link> + <name>sys/link.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI> + </link> + <link> + <name>sys/lseek.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI> + </link> + <link> + <name>sys/open.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI> + </link> + <link> + <name>sys/openat.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI> + </link> + <link> + <name>sys/read.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI> + </link> + <link> + <name>sys/sbrk.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI> + </link> + <link> + <name>sys/stat.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI> + </link> + <link> + <name>sys/stub.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI> + </link> + <link> + <name>sys/times.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI> + </link> + <link> + <name>sys/unlink.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI> + </link> + <link> + <name>sys/wait.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI> + </link> + <link> + <name>sys/write.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI> + </link> + </linkedResources> +</projectDescription> @@ -1,100 +1,188 @@ -srcdir := $(dir $(realpath $(lastword $(MAKEFILE_LIST)))) -srcdir := $(srcdir:/=) -wrkdir := $(CURDIR)/work +############################################################# +# Configuration +############################################################# -DEFAULT_BOARD := freedom-e300-hifive1 -DEFAULT_PROGRAM := demo_gpio +# Allows users to create Makefile.local or ../Makefile.project with +# configuration variables, so they don't have to be set on the command-line +# every time. +extra_configs := $(wildcard Makefile.local ../Makefile.project) +ifneq ($(extra_configs),) +$(info Obtaining additional make variables from $(extra_configs)) +include $(extra_configs) +endif + +# Default target +BOARD ?= freedom-e300-hifive1 +PROGRAM ?= demo_gpio + +# Variables the user probably shouldn't override. +builddir := work/build +installdir := work/install +toolchain_srcdir := riscv-gnu-toolchain +openocd_srcdir := openocd ############################################################# -# Prints help message +# BSP Loading ############################################################# +# Finds the directory in which this BSP is located, ensuring that there is +# exactly one. +board_dir := $(wildcard bsp/env/$(BOARD)) +ifeq ($(words $(board_dir)),0) +$(error Unable to find BSP for $(BOARD), expected to find either "bsp/$(BOARD)" or "bsp-addons/$(BOARD)") +endif +ifneq ($(words $(board_dir)),1) +$(error Found multiple BSPs for $(BOARD): "$(board_dir)") +endif + +# There must be a settings makefile fragment in the BSP's board directory. +ifeq ($(wildcard $(board_dir)/settings.mk),) +$(error Unable to find BSP for $(BOARD), expected to find $(board_dir)/settings.mk) +endif +include $(board_dir)/settings.mk + +ifeq ($(RISCV_ARCH),) +$(error $(board_dir)/board.mk must set RISCV_ARCH, the RISC-V ISA string to target) +endif + +ifeq ($(RISCV_ABI),) +$(error $(board_dir)/board.mk must set RISCV_ABI, the ABI to target) +endif + +# Determines the XLEN from the toolchain tuple +ifeq ($(patsubst rv32%,rv32,$(RISCV_ARCH)),rv32) +RISCV_XLEN := 32 +else ifeq ($(patsubst rv64%,rv64,$(RISCV_ARCH)),rv64) +RISCV_XLEN := 64 +else +$(error Unable to determine XLEN from $(RISCV_ARCH)) +endif + +############################################################# +# Prints help message +############################################################# .PHONY: help -help : +help: @echo " SiFive Freedom E Software Development Kit " @echo " Makefile targets:" @echo "" - @echo " tools:" - @echo " Install compilation & debugging tools." + @echo " tools [BOARD = $(BOARD)]:" + @echo " Install compilation & debugging tools to target your desired board." @echo "" @echo " uninstall:" @echo " Uninstall the compilation & debugging tools." @echo "" - @echo " software [PROGRAM=$(DEFAULT_PROGRAM) BOARD=$(DEFAULT_BOARD)]:" + @echo " software [PROGRAM=$(PROGRAM) BOARD=$(BOARD)]:" @echo " Build a software program to load with the" @echo " debugger." @echo "" - @echo " upload [PROGRAM=$(DEFAULT_PROGRAM) BOARD=$(DEFAULT_BOARD)]:" + @echo " upload [PROGRAM=$(PROGRAM) BOARD=$(BOARD)]:" @echo " Launch OpenOCD to flash your program to the" @echo " on-board Flash." @echo "" - @echo " run_debug [PROGRAM=$(DEFAULT_PROGRAM) BOARD=$(DEFAULT_BOARD)]:" - @echo " Launch OpenOCD & GDB to load or debug " - @echo " running programs. Does not allow Ctrl-C to halt running programs." - @echo "" - @echo " run_openocd [BOARD=$(DEFAULT_BOARD)]:" - @echo " run_gdb [PROGRAM=$(DEFAULT_PROGRAM) BOARD=$(DEFAULT_BOARD)]:" + @echo " run_openocd [BOARD=$(BOARD)]:" + @echo " run_gdb [PROGRAM=$(PROGRAM) BOARD=$(BOARD)]:" @echo " Launch OpenOCD or GDB seperately. Allows Ctrl-C to halt running" @echo " programs." @echo "" - @echo " dasm [PROGRAM=$(DEFAULT_BOARD)]:" + @echo " dasm [PROGRAM=$(BOARD)]:" @echo " Generates the dissassembly output of 'objdump -D' to stdout." @echo "" @echo " For more information, visit dev.sifive.com" +.PHONY: clean +clean: ############################################################# # This section is for tool installation ############################################################# - -toolchain_srcdir := $(srcdir)/riscv-gnu-toolchain -toolchain32_wrkdir := $(wrkdir)/riscv32-gnu-toolchain -toolchain_dest := $(CURDIR)/toolchain -PATH := $(toolchain_dest)/bin:$(PATH) - -openocd_srcdir := $(srcdir)/openocd -openocd_wrkdir := $(wrkdir)/openocd -openocd_dest := $(CURDIR)/toolchain - -target32 := riscv32-unknown-linux-gnu - - -.PHONY: all -all: tools - @echo All done. - -tools: tools32 openocd - @echo All Tools Installed - -tools32: $(toolchain_dest)/bin/$(target32)-gcc -openocd: $(openocd_dest)/bin/openocd - -$(toolchain_dest)/bin/$(target32)-gcc: $(toolchain_srcdir) - mkdir -p $(toolchain32_wrkdir) - cd $(toolchain32_wrkdir); $(toolchain_srcdir)/configure --prefix=$(toolchain_dest) --with-arch=rv32imac --with-abi=ilp32 - $(MAKE) -C $(toolchain32_wrkdir) - -$(openocd_dest)/bin/openocd: $(openocd_srcdir) - mkdir -p $(openocd_wrkdir) - cd $(openocd_srcdir); \ - $(openocd_srcdir)/bootstrap - cd $(openocd_wrkdir); \ - $(openocd_srcdir)/configure --prefix=$(openocd_dest) - $(MAKE) -C $(openocd_wrkdir) - $(MAKE) -C $(openocd_wrkdir) install - -.PHONY: uninstall -uninstall: - rm -rf $(wrkdir) - rm -rf $(toolchain_dest) +.PHONY: tools +tools: riscv-gnu-toolchain openocd + +# Pointers to various important tools in the toolchain. +toolchain_builddir := $(builddir)/riscv-gnu-toolchain/riscv64-unknown-elf +toolchain_prefix := $(toolchain_builddir)/prefix + +RISCV_GCC := $(abspath $(toolchain_prefix)/bin/riscv64-unknown-elf-gcc) +RISCV_GXX := $(abspath $(toolchain_prefix)/bin/riscv64-unknown-elf-g++) +RISCV_OBJDUMP := $(abspath $(toolchain_prefix)/bin/riscv64-unknown-elf-objdump) +RISCV_GDB := $(abspath $(toolchain_prefix)/bin/riscv64-unknown-elf-gdb) +RISCV_AR := $(abspath $(toolchain_prefix)/bin/riscv64-unknown-elf-ar) + +PATH := $(abspath $(toolchain_prefix)/bin):$(PATH) + +$(RISCV_GCC) $(RISCV_GXX) $(RISCV_OBJDUMP) $(RISCV_GDB) $(RISCV_AR): $(toolchain_builddir)/install.stamp + touch -c $@ + +# Builds riscv-gnu-toolchain, which contains GCC and all the supporting +# software for C code. +.PHONY: riscv-gnu-toolchain +riscv-gnu-toolchain: $(RISCV_GCC) $(RISCV_GXX) $(RISCV_OBJDUMP) $(RISCV_GDB) $(RISCV_AR) + +$(builddir)/riscv-gnu-toolchain/%/install.stamp: $(builddir)/riscv-gnu-toolchain/%/build.stamp + $(MAKE) -C $(dir $@) install + date > $@ + +$(builddir)/riscv-gnu-toolchain/%/build.stamp: $(builddir)/riscv-gnu-toolchain/%/configure.stamp + $(MAKE) -C $(dir $@) + date > $@ + +$(builddir)/riscv-gnu-toolchain/%-elf/configure.stamp: + $(eval $@_TUPLE := $(patsubst $(builddir)/riscv-gnu-toolchain/%-elf/configure.stamp,%,$@)) + rm -rf $(dir $@) + mkdir -p $(dir $@) + cd $(dir $@); $(abspath $(toolchain_srcdir)/configure) \ + --prefix=$(abspath $(dir $@)/prefix) \ + --disable-linux \ + --enable-multilib \ + --with-cmodel=medany \ + --with-libgcc-cmodel + date > $@ + +.PHONY: toolchain-clean +clean: toolchain-clean +toolchain-clean: + rm -rf $(toolchain_builddir) + +# Builds and installs OpenOCD, which translates GDB into JTAG for debugging and +# initializing the target. +openocd_builddir := $(builddir)/openocd +openocd_prefix := $(openocd_builddir)/prefix +RISCV_OPENOCD := $(openocd_prefix)/bin/openocd + +.PHONY: openocd +openocd: $(RISCV_OPENOCD) + +$(RISCV_OPENOCD): $(openocd_builddir)/install.stamp + touch -c $@ + +$(openocd_builddir)/install.stamp: $(openocd_builddir)/build.stamp + $(MAKE) -C $(dir $@) install + date > $@ + +$(openocd_builddir)/build.stamp: $(openocd_builddir)/configure.stamp + $(MAKE) -C $(dir $@) + date > $@ + +$(openocd_builddir)/configure.stamp: + rm -rf $(dir $@) + mkdir -p $(dir $@) + cd $(abspath $(openocd_srcdir)); autoreconf -i + cd $(dir $@); $(abspath $(openocd_srcdir)/configure) \ + --prefix=$(abspath $(dir $@)/prefix) \ + --disable-werror + date > $@ + +.PHONY: openocd-clean +clean: openocd-clean +openocd-clean: + rm -rf $(openocd_builddir) ############################################################# # This Section is for Software Compilation ############################################################# -BOARD ?= $(DEFAULT_BOARD) -PROGRAM ?= $(DEFAULT_PROGRAM) -PROGRAM_DIR = $(srcdir)/software/$(PROGRAM) -PROGRAM_ELF = $(srcdir)/software/$(PROGRAM)/$(PROGRAM) +PROGRAM_DIR = software/$(PROGRAM) +PROGRAM_ELF = software/$(PROGRAM)/$(PROGRAM) .PHONY: software_clean software_clean: @@ -102,41 +190,43 @@ software_clean: .PHONY: software software: software_clean - $(MAKE) -C $(PROGRAM_DIR) + $(MAKE) -C $(PROGRAM_DIR) CC=$(RISCV_GCC) RISCV_ARCH=$(RISCV_ARCH) RISCV_ABI=$(RISCV_ABI) AR=$(RISCV_AR) BSP_BASE=$(abspath bsp) BOARD=$(BOARD) -dasm: software - $(toolchain_dest)/bin/riscv32-unknown-elf-objdump -D $(PROGRAM_ELF) +dasm: software $(RISCV_OBJDUMP) + $(RISCV_OBJDUMP) -D $(PROGRAM_ELF) ############################################################# # This Section is for uploading a program to SPI Flash ############################################################# -OPENOCD_UPLOAD = $(srcdir)/bsp/tools/openocd_upload.sh -OPENOCDCFG ?= $(srcdir)/bsp/env/$(BOARD)/openocd.cfg +OPENOCD_UPLOAD = bsp/tools/openocd_upload.sh +OPENOCDCFG ?= bsp/env/$(BOARD)/openocd.cfg +OPENOCDARGS += -f $(OPENOCDCFG) + +GDB_UPLOAD_ARGS ?= --batch + +GDB_UPLOAD_CMDS += -ex "set remotetimeout 240" +GDB_UPLOAD_CMDS += -ex "target extended-remote localhost:3333" +GDB_UPLOAD_CMDS += -ex "monitor reset halt" +GDB_UPLOAD_CMDS += -ex "monitor flash protect 0 64 last off" +GDB_UPLOAD_CMDS += -ex "load" +GDB_UPLOAD_CMDS += -ex "monitor resume" +GDB_UPLOAD_CMDS += -ex "monitor shutdown" +GDB_UPLOAD_CMDS += -ex "quit" upload: - $(OPENOCD_UPLOAD) $(PROGRAM_ELF) $(OPENOCDCFG) + $(RISCV_OPENOCD) $(OPENOCDARGS) & \ + $(RISCV_GDB) $(PROGRAM_DIR)/$(PROGRAM) $(GDB_UPLOAD_ARGS) $(GDB_UPLOAD_CMDS);\ + echo "Successfully uploaded '$(PROGRAM)' to $(BOARD)." ############################################################# # This Section is for launching the debugger ############################################################# -OPENOCD = $(toolchain_dest)/bin/openocd -OPENOCDARGS += -f $(OPENOCDCFG) +run_openocd: + $(RISCV_OPENOCD) $(OPENOCDARGS) -GDB = $(toolchain_dest)/bin/riscv32-unknown-elf-gdb +GDBCMDS += -ex "set remotetimeout 240" GDBCMDS += -ex "target extended-remote localhost:3333" -GDBARGS = - -run_openocd: - $(OPENOCD) $(OPENOCDARGS) run_gdb: - $(GDB) $(PROGRAM_DIR)/$(PROGRAM) $(GDBARGS) - -run_debug: - $(OPENOCD) $(OPENOCDARGS) & - $(GDB) $(PROGRAM_DIR)/$(PROGRAM) $(GDBARGS) $(GDBCMDS) - -.PHONY: clean -clean: - rm -rf -- $(wrkdir) + $(RISCV_GDB) $(PROGRAM_DIR)/$(PROGRAM) $(GDBARGS) $(GDBCMDS) diff --git a/bsp/drivers/fe300prci/fe300prci_driver.c b/bsp/drivers/fe300prci/fe300prci_driver.c index 2d9c52f..8eeaafc 100644 --- a/bsp/drivers/fe300prci/fe300prci_driver.c +++ b/bsp/drivers/fe300prci/fe300prci_driver.c @@ -2,7 +2,7 @@ #include "platform.h" -#ifdef PRCI_BASE_ADDR +#ifdef PRCI_CTRL_ADDR #include "fe300prci/fe300prci_driver.h" #include <unistd.h> diff --git a/bsp/env/common.mk b/bsp/env/common.mk index 74f5582..32703a6 100644 --- a/bsp/env/common.mk +++ b/bsp/env/common.mk @@ -8,7 +8,6 @@ all: $(TARGET) include $(BSP_BASE)/libwrap/libwrap.mk -BOARD ?= freedom-e300-hifive1 ENV_DIR = $(BSP_BASE)/env PLATFORM_DIR = $(ENV_DIR)/$(BOARD) @@ -25,9 +24,6 @@ INCLUDES += -I$(PLATFORM_DIR) TOOL_DIR = $(BSP_BASE)/../toolchain/bin -CC := $(TOOL_DIR)/riscv32-unknown-elf-gcc -AR := $(TOOL_DIR)/riscv32-unknown-elf-ar - LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles LDFLAGS += -L$(ENV_DIR) @@ -40,6 +36,9 @@ LINK_DEPS += $(LINKER_SCRIPT) CLEAN_OBJS += $(TARGET) $(LINK_OBJS) CFLAGS += -g +CFLAGS += -march=$(RISCV_ARCH) +CFLAGS += -mabi=$(RISCV_ABI) +CFLAGS += -mcmodel=medany $(TARGET): $(LINK_OBJS) $(LINK_DEPS) $(CC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS) diff --git a/bsp/env/coreplexip-arty.h b/bsp/env/coreplexip-arty.h new file mode 100644 index 0000000..12ff9a6 --- /dev/null +++ b/bsp/env/coreplexip-arty.h @@ -0,0 +1,102 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_COREPLEXIP_ARTY_H +#define _SIFIVE_COREPLEXIP_ARTY_H + +#include <stdint.h> + +/**************************************************************************** + * GPIO Connections + *****************************************************************************/ + +// These are the GPIO bit offsets for the directly driven +// RGB LEDs on the Freedom Exx Coreplex IP Evaluation Arty FPGA Dev Kit. +// Additional RGB LEDs are driven by the 3 PWM outputs. + +#define RED_LED_OFFSET 0 +#define GREEN_LED_OFFSET 1 +#define BLUE_LED_OFFSET 2 + +// Switch 3 is used as a GPIO input. (Switch 0 is used to set +// the reset vector, the other switches are unused). + +#define SW_3_OFFSET 3 + +// These are the buttons which are mapped as inputs. + +#define HAS_BOARD_BUTTONS + +#define BUTTON_0_OFFSET 4 +#define BUTTON_1_OFFSET 5 +#define BUTTON_2_OFFSET 6 +#define BUTTON_3_OFFSET 7 + +// These are the bit offsets for the different GPIO pins +// mapped onto the PMOD A header. + +#define JA_0_OFFSET 8 +#define JA_1_OFFSET 9 +#define JA_2_OFFSET 10 +#define JA_3_OFFSET 11 +#define JA_4_OFFSET 12 +#define JA_5_OFFSET 13 +#define JA_6_OFFSET 14 +#define JA_7_OFFSET 15 + +// The below gives a mapping between global interrupt +// sources and their number. Note that on the coreplex +// deliverable, the io_global_interrupts go directly into +// the PLIC. The evaluation image on the FPGA mimics a +// system with peripheral devices which are driving the +// global interrupt lines. +// So, on this image, in order to get an interrupt from +// e.g. pressing BUTTON_0: +// 1) Steps which are external to the delivery coreplex: +// a) The corresponding GPIO pin must be configured as in input +// b) The "interrupt on fall" bit must be set for the GPIO pin +// 2) Steps which would also need to be performed for the delivery coreplex: +// a) The corresponding global interrupt, priority, and threshold must be configured in the PLIC. +// b) The external interrupt bit must be enabled in MSTATUS +// c) Interrupts must be enabled globally in the core. + +// Any of the above GPIO pins can be used as global interrupt +// sources by adding their offset to the INT_GPIO_BASE. +// For example, the buttons are shown here: + +#define INT_DEVICE_BUTTON_0 (GPIO_INT_BASE + BUTTON_0_OFFSET) +#define INT_DEVICE_BUTTON_1 (GPIO_INT_BASE + BUTTON_1_OFFSET) +#define INT_DEVICE_BUTTON_2 (GPIO_INT_BASE + BUTTON_2_OFFSET) +#define INT_DEVICE_BUTTON_3 (GPIO_INT_BASE + BUTTON_3_OFFSET) + +// In addition, the Switches are mapped directly to +// the PLIC (without going through the GPIO Peripheral). + +#define INT_EXT_DEVICE_SW_0 (EXTERNAL_INT_BASE + 0) +#define INT_EXT_DEVICE_SW_1 (EXTERNAL_INT_BASE + 1) +#define INT_EXT_DEVICE_SW_2 (EXTERNAL_INT_BASE + 2) +#define INT_EXT_DEVICE_SW_3 (EXTERNAL_INT_BASE + 3) + +// This gives the mapping from inputs to LOCAL interrupts. + +#define LOCAL_INT_SW_0 0 +#define LOCAL_INT_SW_1 1 +#define LOCAL_INT_SW_2 2 +#define LOCAL_INT_SW_3 3 +#define LOCAL_INT_BTN_0 4 +#define LOCAL_INT_BTN_1 5 +#define LOCAL_INT_BTN_2 6 +#define LOCAL_INT_BTN_3 7 +#define LOCAL_INT_JA_0 8 +#define LOCAL_INT_JA_1 9 +#define LOCAL_INT_JA_2 10 +#define LOCAL_INT_JA_3 11 +#define LOCAL_INT_JA_4 12 +#define LOCAL_INT_JA_5 13 +#define LOCAL_INT_JA_6 14 +#define LOCAL_INT_JA_7 15 + +#define RTC_FREQ 32768 + +void write_hex(int fd, uint32_t hex); + +#endif /* _SIFIVE_COREPLEXIP_ARTY_H */ diff --git a/bsp/env/coreplexip-e31-arty/init.c b/bsp/env/coreplexip-e31-arty/init.c new file mode 100644 index 0000000..05b2b3e --- /dev/null +++ b/bsp/env/coreplexip-e31-arty/init.c @@ -0,0 +1,94 @@ +//See LICENSE for license details. +#include <stdint.h> +#include <stdio.h> +#include <unistd.h> + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long get_cpu_freq() +{ + return 65000000; +} + +unsigned long get_timer_freq() +{ + return get_cpu_freq(); +} + +uint64_t get_timer_value() +{ +#if __riscv_xlen == 32 + while (1) { + uint32_t hi = read_csr(mcycleh); + uint32_t lo = read_csr(mcycle); + if (hi == read_csr(mcycleh)) + return ((uint64_t)hi << 32) | lo; + } +#else + return read_csr(mcycle); +#endif +} + +static void uart_init(size_t baud_rate) +{ + UART0_REG(UART_REG_DIV) = (get_cpu_freq() / 2) / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +#ifdef USE_LOCAL_ISR +typedef void (*my_interrupt_function_ptr_t) (void); +extern my_interrupt_function_ptr_t localISR[]; +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif +#ifdef USE_LOCAL_ISR + } else if (mcause & MCAUSE_INT) { + localISR[mcause & MCAUSE_CAUSE] (); +#endif + } + else { + write(1, "Unhandled Trap:\n", 16); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + #ifndef NO_INIT + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + #endif +} + +void _fini() +{ +} diff --git a/bsp/env/coreplexip-e31-arty/link.lds b/bsp/env/coreplexip-e31-arty/link.lds new file mode 100644 index 0000000..45a82d7 --- /dev/null +++ b/bsp/env/coreplexip-e31-arty/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/bsp/env/coreplexip-e31-arty/openocd.cfg b/bsp/env/coreplexip-e31-arty/openocd.cfg new file mode 100644 index 0000000..0481a72 --- /dev/null +++ b/bsp/env/coreplexip-e31-arty/openocd.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/bsp/env/coreplexip-e31-arty/platform.h b/bsp/env/coreplexip-e31-arty/platform.h new file mode 100644 index 0000000..02a0a62 --- /dev/null +++ b/bsp/env/coreplexip-e31-arty/platform.h @@ -0,0 +1,84 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#define IRQ_M_LOCAL 16 +#define MIP_MLIP(x) (1 << (IRQ_M_LOCAL + x)) + +#include "sifive/const.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define GPIO_CTRL_ADDR _AC(0x20002000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define PWM0_CTRL_ADDR _AC(0x20005000,UL) +#define RAM_MEM_ADDR _AC(0x80000000,UL) +#define RAM_MEM_SIZE _AC(0x10000,UL) +#define SPI0_CTRL_ADDR _AC(0x20004000,UL) +#define SPI0_MEM_ADDR _AC(0x40000000,UL) +#define SPI0_MEM_SIZE _AC(0x20000000,UL) +#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL) +#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define UART0_CTRL_ADDR _AC(0x20000000,UL) + +// IOF masks + +// Interrupt numbers +#define RESERVED_INT_BASE 0 +#define UART0_INT_BASE 1 +#define EXTERNAL_INT_BASE 2 +#define SPI0_INT_BASE 6 +#define GPIO_INT_BASE 7 +#define PWM0_INT_BASE 23 + +// Helper functions +#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i))) +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) +#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i))) +// Bulk set bits in `reg` to either 0 or 1. +// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7 +// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7 +#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); } +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define TRAPVEC_TABLE_REG(offset) _REG32(TRAPVEC_TABLE_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset) +#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset) +#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset) +#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset) +#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset) +#define TRAPVEC_TABLE_REG64(offset) _REG64(TRAPVEC_TABLE_CTRL_ADDR, offset) +#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset) + +// Misc + +#define NUM_GPIO 16 + +#define PLIC_NUM_INTERRUPTS 28 +#define PLIC_NUM_PRIORITIES 7 + +#define HAS_BOARD_BUTTONS + +#include "coreplexip-arty.h" + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/bsp/env/coreplexip-e31-arty/settings.mk b/bsp/env/coreplexip-e31-arty/settings.mk new file mode 100644 index 0000000..230fccc --- /dev/null +++ b/bsp/env/coreplexip-e31-arty/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv32imac +RISCV_ABI := ilp32 diff --git a/bsp/env/coreplexip-e51-arty/init.c b/bsp/env/coreplexip-e51-arty/init.c new file mode 120000 index 0000000..de048a9 --- /dev/null +++ b/bsp/env/coreplexip-e51-arty/init.c @@ -0,0 +1 @@ +../coreplexip-e31-arty/init.c
\ No newline at end of file diff --git a/bsp/env/coreplexip-e51-arty/link.lds b/bsp/env/coreplexip-e51-arty/link.lds new file mode 120000 index 0000000..f3e0254 --- /dev/null +++ b/bsp/env/coreplexip-e51-arty/link.lds @@ -0,0 +1 @@ +../coreplexip-e31-arty/link.lds
\ No newline at end of file diff --git a/bsp/env/coreplexip-e51-arty/openocd.cfg b/bsp/env/coreplexip-e51-arty/openocd.cfg new file mode 120000 index 0000000..2f4de8d --- /dev/null +++ b/bsp/env/coreplexip-e51-arty/openocd.cfg @@ -0,0 +1 @@ +../coreplexip-e31-arty/openocd.cfg
\ No newline at end of file diff --git a/bsp/env/coreplexip-e51-arty/platform.h b/bsp/env/coreplexip-e51-arty/platform.h new file mode 120000 index 0000000..311ca36 --- /dev/null +++ b/bsp/env/coreplexip-e51-arty/platform.h @@ -0,0 +1 @@ +../coreplexip-e31-arty/platform.h
\ No newline at end of file diff --git a/bsp/env/coreplexip-e51-arty/settings.mk b/bsp/env/coreplexip-e51-arty/settings.mk new file mode 100644 index 0000000..96aea84 --- /dev/null +++ b/bsp/env/coreplexip-e51-arty/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv64imac +RISCV_ABI := lp64 diff --git a/bsp/env/freedom-e300-arty/platform.h b/bsp/env/freedom-e300-arty/platform.h index d5d6dda..a3a3c07 100644 --- a/bsp/env/freedom-e300-arty/platform.h +++ b/bsp/env/freedom-e300-arty/platform.h @@ -20,21 +20,21 @@ * Platform definitions *****************************************************************************/ -#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) -#define CLINT_BASE_ADDR _AC(0x02000000,UL) -#define PLIC_BASE_ADDR _AC(0x0C000000,UL) -#define AON_BASE_ADDR _AC(0x10000000,UL) -#define GPIO_BASE_ADDR _AC(0x10012000,UL) -#define UART0_BASE_ADDR _AC(0x10013000,UL) -#define SPI0_BASE_ADDR _AC(0x10014000,UL) -#define PWM0_BASE_ADDR _AC(0x10015000,UL) -#define UART1_BASE_ADDR _AC(0x10023000,UL) -#define SPI1_BASE_ADDR _AC(0x10024000,UL) -#define PWM1_BASE_ADDR _AC(0x10025000,UL) -#define SPI2_BASE_ADDR _AC(0x10034000,UL) -#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define AON_CTRL_ADDR _AC(0x10000000,UL) +#define GPIO_CTRL_ADDR _AC(0x10012000,UL) +#define UART0_CTRL_ADDR _AC(0x10013000,UL) +#define SPI0_CTRL_ADDR _AC(0x10014000,UL) +#define PWM0_CTRL_ADDR _AC(0x10015000,UL) +#define UART1_CTRL_ADDR _AC(0x10023000,UL) +#define SPI1_CTRL_ADDR _AC(0x10024000,UL) +#define PWM1_CTRL_ADDR _AC(0x10025000,UL) +#define SPI2_CTRL_ADDR _AC(0x10034000,UL) +#define PWM2_CTRL_ADDR _AC(0x10035000,UL) #define SPI0_MMAP_ADDR _AC(0x20000000,UL) -#define MEM_BASE_ADDR _AC(0x80000000,UL) +#define MEM_CTRL_ADDR _AC(0x80000000,UL) // IOF Mappings #define IOF0_SPI1_MASK _AC(0x000007FC,UL) @@ -91,20 +91,20 @@ // Helper functions #define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) #define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) -#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) -#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) -#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) -#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) -#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) -#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) -#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) -#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) -#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) -#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) -#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) -#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) -#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) -#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) +#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset) // Misc diff --git a/bsp/env/freedom-e300-arty/settings.mk b/bsp/env/freedom-e300-arty/settings.mk new file mode 100644 index 0000000..230fccc --- /dev/null +++ b/bsp/env/freedom-e300-arty/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv32imac +RISCV_ABI := ilp32 diff --git a/bsp/env/freedom-e300-hifive1/init.c b/bsp/env/freedom-e300-hifive1/init.c index de046cc..621a6e2 100644 --- a/bsp/env/freedom-e300-hifive1/init.c +++ b/bsp/env/freedom-e300-hifive1/init.c @@ -10,14 +10,14 @@ extern void trap_entry(); static unsigned long mtime_lo(void) { - return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); + return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME); } #ifdef __riscv32 static uint32_t mtime_hi(void) { - return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); + return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); } uint64_t get_timer_value() diff --git a/bsp/env/freedom-e300-hifive1/platform.h b/bsp/env/freedom-e300-hifive1/platform.h index 63efc9e..806fcfc 100644 --- a/bsp/env/freedom-e300-hifive1/platform.h +++ b/bsp/env/freedom-e300-hifive1/platform.h @@ -23,25 +23,25 @@ *****************************************************************************/ // Memory map -#define MASKROM_BASE_ADDR _AC(0x00001000,UL) -#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) -#define OTP_MMAP_ADDR _AC(0x00020000,UL) -#define CLINT_BASE_ADDR _AC(0x02000000,UL) -#define PLIC_BASE_ADDR _AC(0x0C000000,UL) -#define AON_BASE_ADDR _AC(0x10000000,UL) -#define PRCI_BASE_ADDR _AC(0x10008000,UL) -#define OTP_BASE_ADDR _AC(0x10010000,UL) -#define GPIO_BASE_ADDR _AC(0x10012000,UL) -#define UART0_BASE_ADDR _AC(0x10013000,UL) -#define SPI0_BASE_ADDR _AC(0x10014000,UL) -#define PWM0_BASE_ADDR _AC(0x10015000,UL) -#define UART1_BASE_ADDR _AC(0x10023000,UL) -#define SPI1_BASE_ADDR _AC(0x10024000,UL) -#define PWM1_BASE_ADDR _AC(0x10025000,UL) -#define SPI2_BASE_ADDR _AC(0x10034000,UL) -#define PWM2_BASE_ADDR _AC(0x10035000,UL) -#define SPI0_MMAP_ADDR _AC(0x20000000,UL) -#define MEM_BASE_ADDR _AC(0x80000000,UL) +#define MASKROM_MEM_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define OTP_MEM_ADDR _AC(0x00020000,UL) +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define AON_CTRL_ADDR _AC(0x10000000,UL) +#define PRCI_CTRL_ADDR _AC(0x10008000,UL) +#define OTP_CTRL_ADDR _AC(0x10010000,UL) +#define GPIO_CTRL_ADDR _AC(0x10012000,UL) +#define UART0_CTRL_ADDR _AC(0x10013000,UL) +#define SPI0_CTRL_ADDR _AC(0x10014000,UL) +#define PWM0_CTRL_ADDR _AC(0x10015000,UL) +#define UART1_CTRL_ADDR _AC(0x10023000,UL) +#define SPI1_CTRL_ADDR _AC(0x10024000,UL) +#define PWM1_CTRL_ADDR _AC(0x10025000,UL) +#define SPI2_CTRL_ADDR _AC(0x10034000,UL) +#define PWM2_CTRL_ADDR _AC(0x10035000,UL) +#define SPI0_MEM_ADDR _AC(0x20000000,UL) +#define MEM_CTRL_ADDR _AC(0x80000000,UL) // IOF masks #define IOF0_SPI1_MASK _AC(0x000007FC,UL) @@ -100,20 +100,20 @@ // Helper functions #define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) #define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) -#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) -#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) -#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) -#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) -#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) -#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) -#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) -#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) -#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) -#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) -#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) -#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) -#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) -#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) +#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset) // Misc diff --git a/bsp/env/freedom-e300-hifive1/settings.mk b/bsp/env/freedom-e300-hifive1/settings.mk new file mode 100644 index 0000000..230fccc --- /dev/null +++ b/bsp/env/freedom-e300-hifive1/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv32imac +RISCV_ABI := ilp32 diff --git a/bsp/env/start.S b/bsp/env/start.S index b526411..9ec6c1c 100644 --- a/bsp/env/start.S +++ b/bsp/env/start.S @@ -1,5 +1,7 @@ // See LICENSE for license details. +// See LICENSE for license details. + .section .init .globl _start .type _start,@function @@ -50,5 +52,7 @@ _start: /* argc = argv = 0 */ li a0, 0 li a1, 0 + call _init call main + call _fini tail exit diff --git a/bsp/include/sifive/bits.h b/bsp/include/sifive/bits.h index e550f80..bfe656f 100644 --- a/bsp/include/sifive/bits.h +++ b/bsp/include/sifive/bits.h @@ -1,3 +1,4 @@ +// See LICENSE for license details. #ifndef _RISCV_BITS_H #define _RISCV_BITS_H @@ -17,7 +18,7 @@ #define STR(x) XSTR(x) #define XSTR(x) #x -#ifdef __riscv64 +#if __riscv_xlen == 64 # define SLL32 sllw # define STORE sd # define LOAD ld diff --git a/bsp/include/sifive/const.h b/bsp/include/sifive/const.h index 3e0a681..8dcffbb 100644 --- a/bsp/include/sifive/const.h +++ b/bsp/include/sifive/const.h @@ -1,3 +1,4 @@ +// See LICENSE for license details. /* Derived from <linux/const.h> */ #ifndef _SIFIVE_CONST_H diff --git a/bsp/include/sifive/sections.h b/bsp/include/sifive/sections.h index 848c237..6e1f051 100644 --- a/bsp/include/sifive/sections.h +++ b/bsp/include/sifive/sections.h @@ -1,3 +1,4 @@ +// See LICENSE for license details. #ifndef _SECTIONS_H #define _SECTIONS_H diff --git a/bsp/include/sifive/smp.h b/bsp/include/sifive/smp.h new file mode 100644 index 0000000..8e34388 --- /dev/null +++ b/bsp/include/sifive/smp.h @@ -0,0 +1,65 @@ +#ifndef SIFIVE_SMP +#define SIFIVE_SMP + +// The maximum number of HARTs this code supports +#ifndef MAX_HARTS +#define MAX_HARTS 32 +#endif +#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4) + +// The hart that non-SMP tests should run on +#ifndef NONSMP_HART +#define NONSMP_HART 0 +#endif + +/* If your test cannot handle multiple-threads, use this: + * smp_disable(reg1) + */ +#define smp_disable(reg1, reg2) \ + csrr reg1, mhartid ;\ + li reg2, NONSMP_HART ;\ + beq reg1, reg2, hart0_entry ;\ +42: ;\ + wfi ;\ + j 42b ;\ +hart0_entry: + +/* If your test needs to temporarily block multiple-threads, do this: + * smp_pause(reg1, reg2) + * ... single-threaded work ... + * smp_resume(reg1, reg2) + * ... multi-threaded work ... + */ + +#define smp_pause(reg1, reg2) \ + li reg2, 0x8 ;\ + csrw mie, reg2 ;\ + csrr reg2, mhartid ;\ + bnez reg2, 42f + +#define smp_resume(reg1, reg2) \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + li reg1, CLINT_CTRL_ADDR ;\ + csrr reg2, mhartid ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b + +#endif diff --git a/bsp/libwrap/sys/_exit.c b/bsp/libwrap/sys/_exit.c index 7261891..a548a91 100644 --- a/bsp/libwrap/sys/_exit.c +++ b/bsp/libwrap/sys/_exit.c @@ -5,9 +5,7 @@ void __wrap__exit(int code) { -//volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET); const char message[] = "\nProgam has exited with code:"; -//*leds = (~(code)); write(STDERR_FILENO, message, sizeof(message) - 1); write_hex(STDERR_FILENO, code); diff --git a/bsp/libwrap/sys/read.c b/bsp/libwrap/sys/read.c index 4e57f08..4e35364 100644 --- a/bsp/libwrap/sys/read.c +++ b/bsp/libwrap/sys/read.c @@ -11,8 +11,8 @@ ssize_t __wrap_read(int fd, void* ptr, size_t len) { uint8_t * current = (uint8_t *)ptr; - volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO); - volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2); + volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO); + volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2); ssize_t result = 0; diff --git a/bsp/tools/openocd_upload.sh b/bsp/tools/openocd_upload.sh deleted file mode 100755 index ecbe3b4..0000000 --- a/bsp/tools/openocd_upload.sh +++ /dev/null @@ -1,5 +0,0 @@ -#! /bin/bash -x - -openocd -f ${2} \ - -c "flash protect 0 64 last off; program ${1} verify; resume 0x20400000; exit" \ - 2>&1 | tee openocd_upload.log diff --git a/openocd b/openocd -Subproject 9bab0782d313679bb0bfb634e6e87c757b8d550 +Subproject 95a2eb157ab0f1569faf17ecb666b9953275513 diff --git a/riscv-gnu-toolchain b/riscv-gnu-toolchain -Subproject 3f7b3696217548bc31aeccf9a0c89bdfa4e16a8 +Subproject ef9bf992816a4f1ce110003d69561eb1ba12936 diff --git a/software/coreplexip_welcome/Makefile b/software/coreplexip_welcome/Makefile new file mode 100644 index 0000000..e56ed12 --- /dev/null +++ b/software/coreplexip_welcome/Makefile @@ -0,0 +1,8 @@ +TARGET = coreplexip_welcome +CFLAGS += -O2 -fno-builtin-printf -DNO_INIT + +BSP_BASE = ../../bsp + +C_SRCS += coreplexip_welcome.c + +include $(BSP_BASE)/env/common.mk diff --git a/software/coreplexip_welcome/coreplexip_welcome.c b/software/coreplexip_welcome/coreplexip_welcome.c new file mode 100644 index 0000000..c090b37 --- /dev/null +++ b/software/coreplexip_welcome/coreplexip_welcome.c @@ -0,0 +1,124 @@ +// See LICENSE for license details. + +#include <stdint.h> +#include <stdbool.h> +#include <stdatomic.h> +#include "encoding.h" +#include <platform.h> + +#ifndef _SIFIVE_COREPLEXIP_ARTY_H +#error 'coreplexip_welcome' demo only supported for Coreplex IP Eval Kits +#endif + +static const char sifive_msg[] = "\n\r\ +\n\r\ + SIFIVE, INC.\n\r\ +\n\r\ + 5555555555555555555555555\n\r\ + 5555 5555\n\r\ + 5555 5555\n\r\ + 5555 5555\n\r\ + 5555 5555555555555555555555\n\r\ + 5555 555555555555555555555555\n\r\ + 5555 5555\n\r\ + 5555 5555\n\r\ + 5555 5555\n\r\ +5555555555555555555555555555 55555\n\r\ + 55555 555555555 55555\n\r\ + 55555 55555 55555\n\r\ + 55555 5 55555\n\r\ + 55555 55555\n\r\ + 55555 55555\n\r\ + 55555 55555\n\r\ + 55555 55555\n\r\ + 55555 55555\n\r\ + 555555555\n\r\ + 55555\n\r\ + 5\n\r\ +\n\r\ +"; + +#if __riscv_xlen == 32 + static const char welcome_msg[] = "\n\r\ +\n\r\ +Welcome to the E31 Coreplex IP FPGA Evaluation Kit!\n\r\ +\n\r"; +#else +static const char welcome_msg[] = "\n\r\ +\n\r\ +Welcome to the E51 Coreplex IP FPGA Evaluation Kit!\n\r\ +\n\r"; +#endif + +static void _putc(char c) { + while ((int32_t) UART0_REG(UART_REG_TXFIFO) < 0); + UART0_REG(UART_REG_TXFIFO) = c; +} + +int _getc(char * c){ + int32_t val = (int32_t) UART0_REG(UART_REG_RXFIFO); + if (val > 0) { + *c = val & 0xFF; + return 1; + } + return 0; +} + +static void _puts(const char * s) { + while (*s != '\0'){ + _putc(*s++); + } +} + +int main (void){ + + // 115200 Baud Rate at (65 / 2) MHz + UART0_REG(UART_REG_DIV) = 282; + UART0_REG(UART_REG_TXCTRL) = UART_TXEN; + UART0_REG(UART_REG_RXCTRL) = UART_RXEN; + + // Wait a bit because we were changing the GPIOs + volatile int i=0; + while(i < 10000){i++;} + + _puts(sifive_msg); + + _puts(welcome_msg); + + uint16_t r=0x3F; + uint16_t g=0; + uint16_t b=0; + // Set up RGB PWM + + PWM0_REG(PWM_CFG) = 0; + PWM0_REG(PWM_CFG) = (PWM_CFG_ENALWAYS) | (PWM_CFG_ZEROCMP) | (PWM_CFG_DEGLITCH); + PWM0_REG(PWM_COUNT) = 0; + + // The LEDs are intentionally left somewhat dim. + PWM0_REG(PWM_CMP0) = 0xFE; + + while(1){ + volatile uint64_t * now = (volatile uint64_t*)(CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t then = *now + 400; + while (*now < then) { } + + if(r > 0 && b == 0){ + r--; + g++; + } + if(g > 0 && r == 0){ + g--; + b++; + } + if(b > 0 && g == 0){ + r++; + b--; + } + + PWM0_REG(PWM_CMP1) = 0xFF - (r >> 2); + PWM0_REG(PWM_CMP2) = 0xFF - (g >> 2); + PWM0_REG(PWM_CMP3) = 0xFF - (b >> 2); + + }// While (1) +} + diff --git a/software/demo_gpio/demo_gpio.c b/software/demo_gpio/demo_gpio.c index bfa388e..8fe03e1 100644 --- a/software/demo_gpio/demo_gpio.c +++ b/software/demo_gpio/demo_gpio.c @@ -9,8 +9,6 @@ #include <unistd.h> #include "stdatomic.h" -#define RTC_FREQUENCY 32768 - void reset_demo (void); // Structures for registering different interrupt handlers @@ -48,10 +46,10 @@ void handle_m_time_interrupt(){ // Reset the timer for 3s in the future. // This also clears the existing timer interrupt. - volatile uint64_t * mtime = (uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIME); - volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIMECMP); + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); uint64_t now = *mtime; - uint64_t then = now + 1.5 * RTC_FREQUENCY; + uint64_t then = now + 2 * RTC_FREQ; *mtimecmp = then; // read the current value of the LEDS and invert them. @@ -94,7 +92,7 @@ const char * instructions_msg = " \ 5\n\ \n\ SiFive E-Series Software Development Kit 'demo_gpio' program.\n\ -Every 1.5 second, the Timer Interrupt will invert the LEDs.\n\ +Every 2 second, the Timer Interrupt will invert the LEDs.\n\ (Arty Dev Kit Only): Press Buttons 0, 1, 2 to Set the LEDs.\n\ Pin 19 (HiFive1) or A5 (Arty Dev Kit) is being bit-banged\n\ for GPIO speed demonstration.\n\ @@ -179,10 +177,10 @@ void reset_demo (){ // Set the machine timer to go off in 3 seconds. // The - volatile uint64_t * mtime = (uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIME); - volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIMECMP); + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); uint64_t now = *mtime; - uint64_t then = now + 1.5*RTC_FREQUENCY; + uint64_t then = now + 2*RTC_FREQ; *mtimecmp = then; // Enable the Machine-External bit in MIE @@ -199,6 +197,7 @@ int main(int argc, char **argv) { // Set up the GPIOs such that the LED GPIO // can be used as both Inputs and Outputs. + #ifdef HAS_BOARD_BUTTONS GPIO_REG(GPIO_OUTPUT_EN) &= ~((0x1 << BUTTON_0_OFFSET) | (0x1 << BUTTON_1_OFFSET) | (0x1 << BUTTON_2_OFFSET)); @@ -211,15 +210,26 @@ int main(int argc, char **argv) GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << BLUE_LED_OFFSET) ; GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET)) ; + // For Bit-banging with Atomics demo. - GPIO_REG(GPIO_OUTPUT_EN) |= (0x1 << PIN_19_OFFSET); - + + uint32_t bitbang_mask = 0; +#ifdef _SIFIVE_HIFIVE1_H + bitbang_mask = (1 << PIN_19_OFFSET); +#else +#ifdef _SIFIVE_COREPLEXIP_ARTY_H + bitbang_mask = (0x1 << JA_0_OFFSET); +#endif +#endif + + GPIO_REG(GPIO_OUTPUT_EN) |= bitbang_mask; + /************************************************************************** * Set up the PLIC * *************************************************************************/ PLIC_init(&g_plic, - PLIC_BASE_ADDR, + PLIC_CTRL_ADDR, PLIC_NUM_INTERRUPTS, PLIC_NUM_PRIORITIES); @@ -231,10 +241,10 @@ int main(int argc, char **argv) * the entire OUTPUT_VAL that you want to write, but * Atomics give a quick way to control a single bit. *************************************************************************/ - uint32_t mask = (1 << PIN_19_OFFSET); - + // For Bit-banging with Atomics demo. + while (1){ - atomic_fetch_xor_explicit(&GPIO_REG(GPIO_OUTPUT_VAL), mask, memory_order_relaxed); + atomic_fetch_xor_explicit(&GPIO_REG(GPIO_OUTPUT_VAL), bitbang_mask, memory_order_relaxed); } return 0; diff --git a/software/dhrystone/Makefile b/software/dhrystone/Makefile index 78a7b23..d401720 100644 --- a/software/dhrystone/Makefile +++ b/software/dhrystone/Makefile @@ -5,11 +5,11 @@ C_SRCS := dhry_stubs.c dhry_printf.c HEADERS := dhry.h DHRY_SRCS := dhry_1.c dhry_2.c -DHRY_CFLAGS := -O2 -DTIME -fno-inline -fno-builtin-printf -Wno-implicit -march=rv32ima +DHRY_CFLAGS := -O2 -DTIME -fno-inline -fno-builtin-printf -Wno-implicit -mcmodel=medany -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) XLEN ?= 32 -CFLAGS := -Os -fno-common -LDFLAGS := -Wl,--wrap=scanf -Wl,--wrap=printf +CFLAGS := -Os -fno-common -mcmodel=medany -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) +LDFLAGS := -Wl,--wrap=scanf -Wl,--wrap=printf -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=medany DHRY_OBJS := $(patsubst %.c,%.o,$(DHRY_SRCS)) LINK_OBJS := $(DHRY_OBJS) diff --git a/software/double_tap_dontboot/double_tap_dontboot.c b/software/double_tap_dontboot/double_tap_dontboot.c index 0cae5b5..53c2c64 100644 --- a/software/double_tap_dontboot/double_tap_dontboot.c +++ b/software/double_tap_dontboot/double_tap_dontboot.c @@ -42,6 +42,11 @@ #include "platform.h" #include "encoding.h" +#ifndef _SIFIVE_HIFIVE1_H +#error "double_tap_dontboot is designed to run on HiFive1 and/or E300 Arty Dev Kit." +#endif + + #define BACKUP15_MAGIC 0xD027B007 #define FINAL_ADDRESS 0x20400000 @@ -97,9 +102,9 @@ int main(void) // because it makes it clear that the processor is actually // running this code, not just the PWM hardware. - now = *((volatile uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIME)); + now = *((volatile uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME)); then = now + 32768/500; - while (*((volatile uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIME)) < then) { + while (*((volatile uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME)) < then) { asm volatile (""); } pwm_val = (pwm_val == 0) ? 255 : (pwm_val -1); @@ -121,9 +126,9 @@ int main(void) // Wait 500 ms. If reset is tapped at this point, // we will execute the "magic" loop above. - now = *((volatile uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIME)); + now = *((volatile uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME)); then = now + 32768/2; - while (*((volatile uint64_t*) (CLINT_BASE_ADDR + CLINT_MTIME)) < then) { + while (*((volatile uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME)) < then) { asm volatile (""); } diff --git a/software/global_interrupts/Makefile b/software/global_interrupts/Makefile new file mode 100644 index 0000000..6a09f97 --- /dev/null +++ b/software/global_interrupts/Makefile @@ -0,0 +1,9 @@ +TARGET = global_interrupts +CFLAGS += -O2 -fno-builtin-printf -DUSE_LOCAL_ISR + +BSP_BASE = ../../bsp + +C_SRCS += global_interrupts.c +C_SRCS += $(BSP_BASE)/drivers/plic/plic_driver.c + +include $(BSP_BASE)/env/common.mk diff --git a/software/global_interrupts/global_interrupts.c b/software/global_interrupts/global_interrupts.c new file mode 100644 index 0000000..4d3a554 --- /dev/null +++ b/software/global_interrupts/global_interrupts.c @@ -0,0 +1,250 @@ +// See LICENSE for license details. + +#include <stdio.h> +#include <stdlib.h> +#include "platform.h" +#include <string.h> +#include "plic/plic_driver.h" +#include "encoding.h" +#include <unistd.h> + +#ifndef _SIFIVE_COREPLEXIP_ARTY_H +#error 'global_interrupts' demo only supported for Coreplex IP Eval Kits +#endif + +// Global Instance data for the PLIC +// for use by the PLIC Driver. +plic_instance_t g_plic; + +// Flag for state +int g_switch1Wins; + +// Debounce counter (PWM can't go slow enough) +int g_debounce; + +void debounce(); + +// Structures for registering different interrupt handlers +// for different parts of the application. +typedef void (*interrupt_function_ptr_t) (void); + +// See bsp/env/<BOARD>/init.c for how this +// interrupt vector is used. +interrupt_function_ptr_t localISR[32]; + +interrupt_function_ptr_t g_ext_interrupt_handlers[PLIC_NUM_INTERRUPTS]; + +void set_timer() { + + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); + uint64_t now = *mtime; + uint64_t then = now + 10*RTC_FREQ; + *mtimecmp = then; + +} + +/*Entry Point for Machine Timer Interrupt Handler*/ +void mti_isr(){ + + if (g_switch1Wins) { + printf("#### Giving Switch 1 Priority for 10 seconds ####\n"); + // All other things being equal, lower IDs have + // higher priority. We have already set + // Switch 1 to priority 2 + // in the setup, so by giving these equal priority Switch 1 will win. + PLIC_set_priority(&g_plic, INT_EXT_DEVICE_SW_2, 2); + } else { + printf("**** Giving Switch 2 Priority for 10 seconds ****\n"); + // By setting Switch 2 a higher integer priority, it will win over switch 1. + PLIC_set_priority(&g_plic, INT_EXT_DEVICE_SW_2, 3); + } + g_switch1Wins ^= 0x1; + + set_timer(); + +} + +/*Entry Point for PLIC Interrupt Handler*/ +void mei_isr(){ + plic_source int_num = PLIC_claim_interrupt(&g_plic); + if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS)) { + g_ext_interrupt_handlers[int_num](); + } + else { + exit(1 + (uintptr_t) int_num); + } + PLIC_complete_interrupt(&g_plic, int_num); +} + +const char * instructions_msg = " \ +\n\ + SIFIVE, INC.\n\ +E31/E51 Coreplex IP Eval Kit 'global_interrupts' demo.\n\ +\n\ +Switches 1 and 2 are enabled as External Global Interrupts \n\ +(they don't go through the PLIC). You an observe priorities.\n\ +Priorities invert every few seconds, which is driven by the \n\ +PWM0 global interrupt. \n\ +\n"; + +void print_instructions() { + + write (STDOUT_FILENO, instructions_msg, strlen(instructions_msg)); + +} + +void invalid_global_isr() { + printf("Unexpected global interrupt!\n"); +} + +void invalid_local_isr() { + printf ("Unexpected local interrupt!\n"); +} + +void switch_1_handler() { + + printf("Switch 1 is on! Even if Switch 2 is on, Switch 1 must have higher priority right now.\n"); + + // Set Green LED + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << GREEN_LED_OFFSET) ; + GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1<< RED_LED_OFFSET)); + + debounce(); + +} + +void switch_2_handler() { + printf("Switch 2 is on! Even if Switch 1 is on, Switch 2 must have higher priority right now.\n"); + + // Set RED LED + GPIO_REG(GPIO_OUTPUT_VAL) &= ~(0x1 << GREEN_LED_OFFSET) ; + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1<< RED_LED_OFFSET); + + debounce(); +} + +// We use PWM 0 as a +// timer interrupt for debouncing. + +void pwm_0_handler() { + + + if (g_debounce == 0) { + printf(" Done debouncing.\n"); + + //Lower the threshold s.t. the switches can hit. + PLIC_set_threshold(&g_plic, 1); + + // Clear the PWM interrupt + PWM0_REG(PWM_CFG) = 0; + + } else { + // Keep waiting + g_debounce --; + // This clears out the interrupt and re-arms the timer. + PWM0_REG(PWM_CFG) = ((PWM_CFG_ONESHOT) | (PWM_CFG_ZEROCMP)| 0x7 | (PWM_CFG_STICKY)); + + } + +} + +void debounce(int local_interrupt_num) { + + printf(" Starting a debounce.\n"); + + g_debounce = 600; + + // This clears out the interrupt and re-arms the timer. + PWM0_REG(PWM_CFG) = ((PWM_CFG_ONESHOT) | (PWM_CFG_ZEROCMP)| 0x7 | (PWM_CFG_STICKY)); + + // Set the threshold high enough that the + // switches won't cause the interrupt to fire, + // only the PWM or timer interrupts. + PLIC_set_threshold(&g_plic, 4); + +} + +int main(int argc, char **argv) +{ + + for (int gisr = 0; gisr < PLIC_NUM_INTERRUPTS; gisr++){ + g_ext_interrupt_handlers[PLIC_NUM_INTERRUPTS] = invalid_global_isr; + } + g_ext_interrupt_handlers[PWM0_INT_BASE + 0] = pwm_0_handler; + g_ext_interrupt_handlers[INT_EXT_DEVICE_SW_1] = switch_1_handler; + g_ext_interrupt_handlers[INT_EXT_DEVICE_SW_2] = switch_2_handler; + + for (int lisr = 0; lisr < 32; lisr++){ + localISR[lisr] = invalid_local_isr; + } + + localISR[IRQ_M_TIMER] = mti_isr; + localISR[IRQ_M_EXT] = mei_isr; + + print_instructions(); + + // Set up RGB LEDs for a visual. + + GPIO_REG(GPIO_OUTPUT_EN) |= ((0x1<< RED_LED_OFFSET)| (0x1<< GREEN_LED_OFFSET)); + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << GREEN_LED_OFFSET) ; + GPIO_REG(GPIO_OUTPUT_VAL) &= ~(0x1<< RED_LED_OFFSET); + + /************************************************************************** + * Set up the PLIC + * + *************************************************************************/ + PLIC_init(&g_plic, + PLIC_CTRL_ADDR, + PLIC_NUM_INTERRUPTS, + PLIC_NUM_PRIORITIES); + + /************************************************************************** + * Give Switch 1 and Switch 2 Equal priority of 2. + * + *************************************************************************/ + + PLIC_enable_interrupt (&g_plic, PWM0_INT_BASE + 0); + PLIC_enable_interrupt (&g_plic, INT_EXT_DEVICE_SW_1); + PLIC_enable_interrupt (&g_plic, INT_EXT_DEVICE_SW_2); + + // PWM always beats the switches, because we use it + // as a debouncer, and we lower the threshold + // to do so. + + PWM0_REG(PWM_CFG) = 0; + + // Make sure people aren't blinded by LEDs connected here. + PWM0_REG(PWM_CMP0) = 0xFE; + PWM0_REG(PWM_CMP1) = 0xFF; + PWM0_REG(PWM_CMP2) = 0xFF; + PWM0_REG(PWM_CMP3) = 0xFF; + PLIC_set_priority(&g_plic, PWM0_INT_BASE + 0 , 5); + + // Start the switches out at the same priority. Switch1 + // would win. + PLIC_set_priority(&g_plic, INT_EXT_DEVICE_SW_1, 2); + PLIC_set_priority(&g_plic, INT_EXT_DEVICE_SW_2, 2); + + // Set up machine timer interrupt. Every few seconds it + // will invert the switch priorities. + set_timer(); + + // Enable timer interrupts. + set_csr(mie, MIP_MTIP); + + // Enable Global (PLIC) interrupts. + set_csr(mie, MIP_MEIP); + + g_switch1Wins = 1; + + // Enable all interrupts + set_csr(mstatus, MSTATUS_MIE); + + while(1){ + asm volatile ("wfi"); + } + + return 0; + +} diff --git a/software/led_fade/led_fade.c b/software/led_fade/led_fade.c index 775647a..3c7b8c8 100644 --- a/software/led_fade/led_fade.c +++ b/software/led_fade/led_fade.c @@ -6,6 +6,10 @@ #include <stdint.h> #include "platform.h" +#ifndef _SIFIVE_HIFIVE1_H +#error "'led_fade' is designed to run on HiFive1 and/or E300 Arty Dev Kit." +#endif + static const char led_msg[] = "\a\n\r\n\r\ 55555555555555555555555555555555555555555555555\n\r\ 5555555 Are the LEDs Changing? [y/n] 555555555\n\r\ @@ -118,7 +122,7 @@ int main (void){ GPIO_REG(GPIO_OUTPUT_XOR) |= (1 << RED_LED_OFFSET); while(1){ - volatile uint64_t * now = (volatile uint64_t*)(CLINT_BASE_ADDR + CLINT_MTIME); + volatile uint64_t * now = (volatile uint64_t*)(CLINT_CTRL_ADDR + CLINT_MTIME); volatile uint64_t then = *now + 100; while (*now < then) { } diff --git a/software/local_interrupts/Makefile b/software/local_interrupts/Makefile new file mode 100644 index 0000000..4605ee9 --- /dev/null +++ b/software/local_interrupts/Makefile @@ -0,0 +1,8 @@ +TARGET = local_interrupts +CFLAGS += -O2 -fno-builtin-printf -DUSE_LOCAL_ISR + +BSP_BASE = ../../bsp + +C_SRCS += local_interrupts.c + +include $(BSP_BASE)/env/common.mk diff --git a/software/local_interrupts/local_interrupts.c b/software/local_interrupts/local_interrupts.c new file mode 100644 index 0000000..cb2aca3 --- /dev/null +++ b/software/local_interrupts/local_interrupts.c @@ -0,0 +1,216 @@ +// See LICENSE for license details. + +#include <stdio.h> +#include <stdlib.h> +#include "platform.h" +#include <string.h> +#include "encoding.h" +#include <unistd.h> + +#ifndef _SIFIVE_COREPLEXIP_ARTY_H +#error 'local_interrupts' demo only supported for Coreplex IP Eval Kits +#endif + +// Global Variable used to show +// software interrupts. +volatile uint32_t g_debouncing; + +void debounce(); + +// Structures for registering different interrupt handlers +// for different parts of the application. +typedef void (*interrupt_function_ptr_t) (void); + +// This function enables some of the local interrupts sources +// used in this demo -- just those for the buttons and +// Switch 3. + +void enable_local_interrupts(){ + + // lowest priority + set_csr(mie, MIP_MLIP(LOCAL_INT_SW_3 )); + set_csr(mie, MIP_MLIP(LOCAL_INT_BTN_0)); + set_csr(mie, MIP_MLIP(LOCAL_INT_BTN_1)); + set_csr(mie, MIP_MLIP(LOCAL_INT_BTN_2)); + set_csr(mie, MIP_MLIP(LOCAL_INT_BTN_3)); + // highest priority + +} + +void disable_local_interrupts() { + + // lowest priority + clear_csr(mie, MIP_MLIP(LOCAL_INT_SW_3 )); + clear_csr(mie, MIP_MLIP(LOCAL_INT_BTN_0)); + clear_csr(mie, MIP_MLIP(LOCAL_INT_BTN_1)); + clear_csr(mie, MIP_MLIP(LOCAL_INT_BTN_2)); + clear_csr(mie, MIP_MLIP(LOCAL_INT_BTN_3)); + // highest priority + +} + +/*Entry Point for Machine Software Interrupt Handler*/ +void msi_isr() { + + const char msi_msg[] = " Debouncing: (this message due to Software Interrupt))\n\n"; + write (STDOUT_FILENO, msi_msg, strlen(msi_msg)); + + //clear the SW interrupt + CLINT_REG(CLINT_MSIP) = 0; + +} + +/*Entry Point for Machine Timer Interrupt Handler*/ +void mti_isr(){ + + // Disable the timer interrupt. The Debounce logic sets it. + clear_csr(mie, MIP_MTIP); + + // Enable all the local interrupts + enable_local_interrupts(); +} + + +const char * instructions_msg = " \ +\n\ + SiFive, Inc\n\ + E31/E51 Coreplex IP Eval Kit 'local_interrupts' demo.\n\ +\n\ +The Buttons 0-3 and Switch 3 are enabled as local\n\ +interrupts sources. A .5 s 'debounce' timer is used \n\ +between these interrupts. Software interrupts are +used to print a message while debouncing.\n\ +Note the priority of the interrupts sources.\n\ +\n"; + +void print_instructions() { + + write (STDERR_FILENO, instructions_msg, strlen(instructions_msg)); + +} + +void button_0_isr(void) { + + // Toggle Red LED + const char button_0_msg[] = "Button 0 was pressed. Toggle Red.\n"; + write (STDOUT_FILENO, button_0_msg, strlen(button_0_msg)); + GPIO_REG(GPIO_OUTPUT_VAL) = GPIO_REG(GPIO_OUTPUT_VAL) ^ (0x1 << RED_LED_OFFSET); + debounce(); +}; + +void button_1_isr(void) { + + // Toggle Green LED + const char button_1_msg[] = "Button 1 was pressed. Toggle Green.\n"; + write (STDOUT_FILENO, button_1_msg, strlen(button_1_msg)); + GPIO_REG(GPIO_OUTPUT_VAL) = GPIO_REG(GPIO_OUTPUT_VAL) ^ (0x1 << GREEN_LED_OFFSET); + debounce(); +}; + + +void button_2_isr(void) { + + // Toggle Blue LED + const char button_2_msg[] = "Button 2 was pressed. Toggle Blue.\n"; + write (STDOUT_FILENO, button_2_msg, strlen(button_2_msg)); + GPIO_REG(GPIO_OUTPUT_VAL) = GPIO_REG(GPIO_OUTPUT_VAL) ^ (0x1 << BLUE_LED_OFFSET); + debounce(); + +}; + +void button_3_isr(void) { + const char button_3_msg[] = "Button 3 was pressed! (No LEDs change).\n"; + write (STDOUT_FILENO, button_3_msg, strlen(button_3_msg)); + debounce(); +} + +void switch_3_isr(void) { + const char sw_3_msg[] = "Switch 3 is on! But buttons have higher priority.\n"; + write (STDOUT_FILENO, sw_3_msg, strlen(sw_3_msg)); + debounce(); +} + +void debounce(int local_interrupt_num) { + + // Disable the most recent interrupt. + // Don't enable it again until the timer goes off, + // in .5 second. + + // Set the machine timer to go off in .5 seconds. + // If the timer was already set to go off, this "cancels" + // the current one. + + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); + uint64_t now = *mtime; + uint64_t then = now + .5*RTC_FREQ; + *mtimecmp = then; + + disable_local_interrupts(); + g_debouncing = 1; + + // Enable the Machine-Timer bit in MIE + set_csr(mie, MIP_MTIP); + +} + +// See bsp/env/<BOARD>/init.c for how this +// interrupt vector is used. + +interrupt_function_ptr_t localISR[32]; + +int main(int argc, char **argv) +{ + + // Configure LEDs as outputs. + GPIO_REG(GPIO_INPUT_EN) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ; + GPIO_REG(GPIO_OUTPUT_EN) |= ((0x1<< RED_LED_OFFSET)| (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ; + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << BLUE_LED_OFFSET) ; + GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET)) ; + + // The Buttons and Switches which are used as local interrupt sources + // do not go through the GPIO peripheral, so they do not need to + // be configured as inputs. + + // Disable the timer & local interrupts until setup is done (they're + // not reset by default) + + // Disable all interrupts. MIE is not reset. + write_csr(mie, 0); + + for (int isr = 0; isr < 32; isr++){ + localISR[isr] = 0; + } + + localISR[IRQ_M_SOFT] = msi_isr; + localISR[IRQ_M_TIMER] = mti_isr; + localISR[IRQ_M_LOCAL + LOCAL_INT_SW_3] = switch_3_isr; + localISR[IRQ_M_LOCAL + LOCAL_INT_BTN_0] = button_0_isr; + localISR[IRQ_M_LOCAL + LOCAL_INT_BTN_1] = button_1_isr; + localISR[IRQ_M_LOCAL + LOCAL_INT_BTN_2] = button_2_isr; + localISR[IRQ_M_LOCAL + LOCAL_INT_BTN_3] = button_3_isr; + + print_instructions(); + + enable_local_interrupts(); + + g_debouncing = 0; + + // Enable SW interrupts as well in this demo. + set_csr(mie, MIP_MSIP); + + // Enable all global interrupts + set_csr(mstatus, MSTATUS_MIE); + + volatile int foo = 1; + while(foo){ + if (g_debouncing){ + //Trigger a SW interrupt + CLINT_REG(CLINT_MSIP) = 1; + g_debouncing = 0; + } + } + + return 0; + +} |