Setup default options for dhrystone release.

26 files changed, 74 insertions, 23 deletions

diff --git a/bsp/coreip-e20-arty/settings.mk b/bsp/coreip-e20-arty/settings.mk
index 5a405fe..bc4125f 100644
--- a/bsp/coreip-e20-arty/settings.mk
+++ b/bsp/coreip-e20-arty/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-09        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imc
@@ -9,3 +9,4 @@ RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
 
 TARGET_TAGS=fpga openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/coreip-e20-rtl/settings.mk b/bsp/coreip-e20-rtl/settings.mk
index 6520e6d..26ee991 100644
--- a/bsp/coreip-e20-rtl/settings.mk
+++ b/bsp/coreip-e20-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-09        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imc
@@ -11,3 +11,4 @@ RISCV_CMODEL=medlow
 COREIP_MEM_WIDTH=32
 
 TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk
index b9be584..3e8ebf8 100644
--- a/bsp/coreip-e21-arty/settings.mk
+++ b/bsp/coreip-e21-arty/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imac
@@ -9,3 +9,4 @@ RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
 
 TARGET_TAGS=fpga openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/coreip-e21-rtl/settings.mk b/bsp/coreip-e21-rtl/settings.mk
index bb8d89a..fd09a82 100644
--- a/bsp/coreip-e21-rtl/settings.mk
+++ b/bsp/coreip-e21-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imac
@@ -11,3 +11,4 @@ RISCV_CMODEL=medlow
 COREIP_MEM_WIDTH=32
 
 TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
diff --git a/bsp/coreip-e24-arty/settings.mk b/bsp/coreip-e24-arty/settings.mk
index 115db75..8f23cea 100644
--- a/bsp/coreip-e24-arty/settings.mk
+++ b/bsp/coreip-e24-arty/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imafc
@@ -9,3 +9,4 @@ RISCV_ABI=ilp32f
 RISCV_CMODEL=medlow
 
 TARGET_TAGS=fpga openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/coreip-e24-rtl/settings.mk b/bsp/coreip-e24-rtl/settings.mk
index 4d6b13e..715b312 100644
--- a/bsp/coreip-e24-rtl/settings.mk
+++ b/bsp/coreip-e24-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imafc
@@ -11,3 +11,4 @@ RISCV_CMODEL=medlow
 COREIP_MEM_WIDTH=32
 
 TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk
index b9be584..3e8ebf8 100644
--- a/bsp/coreip-e31-arty/settings.mk
+++ b/bsp/coreip-e31-arty/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imac
@@ -9,3 +9,4 @@ RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
 
 TARGET_TAGS=fpga openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk
index bb8d89a..fd09a82 100644
--- a/bsp/coreip-e31-rtl/settings.mk
+++ b/bsp/coreip-e31-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imac
@@ -11,3 +11,4 @@ RISCV_CMODEL=medlow
 COREIP_MEM_WIDTH=32
 
 TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
diff --git a/bsp/coreip-e34-arty/settings.mk b/bsp/coreip-e34-arty/settings.mk
index 115db75..8f23cea 100644
--- a/bsp/coreip-e34-arty/settings.mk
+++ b/bsp/coreip-e34-arty/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imafc
@@ -9,3 +9,4 @@ RISCV_ABI=ilp32f
 RISCV_CMODEL=medlow
 
 TARGET_TAGS=fpga openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/coreip-e34-rtl/settings.mk b/bsp/coreip-e34-rtl/settings.mk
index 4d6b13e..715b312 100644
--- a/bsp/coreip-e34-rtl/settings.mk
+++ b/bsp/coreip-e34-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imafc
@@ -11,3 +11,4 @@ RISCV_CMODEL=medlow
 COREIP_MEM_WIDTH=32
 
 TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk
index 115db75..8f23cea 100644
--- a/bsp/coreip-e76-arty/settings.mk
+++ b/bsp/coreip-e76-arty/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imafc
@@ -9,3 +9,4 @@ RISCV_ABI=ilp32f
 RISCV_CMODEL=medlow
 
 TARGET_TAGS=fpga openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/coreip-e76-rtl/settings.mk b/bsp/coreip-e76-rtl/settings.mk
index 18bea9e..0ef35b7 100644
--- a/bsp/coreip-e76-rtl/settings.mk
+++ b/bsp/coreip-e76-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imafc
@@ -11,3 +11,4 @@ RISCV_CMODEL=medlow
 COREIP_MEM_WIDTH=64
 
 TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk
index 19205af..a18cf05 100644
--- a/bsp/coreip-s51-arty/settings.mk
+++ b/bsp/coreip-s51-arty/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv64imac
@@ -9,3 +9,4 @@ RISCV_ABI=lp64
 RISCV_CMODEL=medany
 
 TARGET_TAGS=fpga openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/coreip-s51-rtl/settings.mk b/bsp/coreip-s51-rtl/settings.mk
index 6af5958..b69debb 100644
--- a/bsp/coreip-s51-rtl/settings.mk
+++ b/bsp/coreip-s51-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv64imac
@@ -11,3 +11,4 @@ RISCV_CMODEL=medany
 COREIP_MEM_WIDTH=64
 
 TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
diff --git a/bsp/coreip-s54-arty/settings.mk b/bsp/coreip-s54-arty/settings.mk
index 4ce0f71..1679ade 100644
--- a/bsp/coreip-s54-arty/settings.mk
+++ b/bsp/coreip-s54-arty/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-02        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv64imafdc
@@ -9,3 +9,4 @@ RISCV_ABI=lp64d
 RISCV_CMODEL=medany
 
 TARGET_TAGS=fpga openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/coreip-s54-rtl/settings.mk b/bsp/coreip-s54-rtl/settings.mk
index c7a4614..7602565 100644
--- a/bsp/coreip-s54-rtl/settings.mk
+++ b/bsp/coreip-s54-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-03        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv64imafdc
@@ -11,3 +11,4 @@ RISCV_CMODEL=medany
 COREIP_MEM_WIDTH=64
 
 TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
diff --git a/bsp/coreip-s76-arty/settings.mk b/bsp/coreip-s76-arty/settings.mk
index 4ce0f71..a3f9bc1 100644
--- a/bsp/coreip-s76-arty/settings.mk
+++ b/bsp/coreip-s76-arty/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-03        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv64imafdc
@@ -9,3 +9,4 @@ RISCV_ABI=lp64d
 RISCV_CMODEL=medany
 
 TARGET_TAGS=fpga openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/coreip-s76-rtl/settings.mk b/bsp/coreip-s76-rtl/settings.mk
index c7a4614..7602565 100644
--- a/bsp/coreip-s76-rtl/settings.mk
+++ b/bsp/coreip-s76-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-10        #
+# [XXXXX] 22-05-2019 00-09-03        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv64imafdc
@@ -11,3 +11,4 @@ RISCV_CMODEL=medany
 COREIP_MEM_WIDTH=64
 
 TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
diff --git a/bsp/coreip-u54-rtl/settings.mk b/bsp/coreip-u54-rtl/settings.mk
index 6c25a1f..9ae1de9 100644
--- a/bsp/coreip-u54-rtl/settings.mk
+++ b/bsp/coreip-u54-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-11        #
+# [XXXXX] 22-05-2019 00-09-03        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv64imafdc
@@ -11,3 +11,4 @@ RISCV_CMODEL=medany
 COREIP_MEM_WIDTH=128
 
 TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk
index e59f66a..7da27c4 100644
--- a/bsp/coreip-u54mc-rtl/settings.mk
+++ b/bsp/coreip-u54mc-rtl/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-11        #
+# [XXXXX] 22-05-2019 00-09-03        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv64imac
@@ -11,3 +11,4 @@ RISCV_CMODEL=medany
 COREIP_MEM_WIDTH=128
 
 TARGET_TAGS=rtl
+TARGET_DHRY_ITERS=2000
diff --git a/bsp/freedom-e310-arty/settings.mk b/bsp/freedom-e310-arty/settings.mk
index 6307e3a..da84dbc 100644
--- a/bsp/freedom-e310-arty/settings.mk
+++ b/bsp/freedom-e310-arty/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-11        #
+# [XXXXX] 22-05-2019 00-09-03        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imac
@@ -9,3 +9,4 @@ RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
 
 TARGET_TAGS=fpga openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/sifive-hifive-unleashed/settings.mk b/bsp/sifive-hifive-unleashed/settings.mk
index 38a72d6..07f05fd 100644
--- a/bsp/sifive-hifive-unleashed/settings.mk
+++ b/bsp/sifive-hifive-unleashed/settings.mk
@@ -1,5 +1,12 @@
+# Copyright 2019 SiFive, Inc #
+# SPDX-License-Identifier: Apache-2.0 #
+# ----------------------------------- #
+# [XXXXX] 22-05-2019 00-09-03        #
+# ----------------------------------- #
+
 RISCV_ARCH=rv64imac
 RISCV_ABI=lp64
 RISCV_CMODEL=medany
 
 TARGET_TAGS=board openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk
index 442f2d3..fbfcb79 100644
--- a/bsp/sifive-hifive1-revb/settings.mk
+++ b/bsp/sifive-hifive1-revb/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-11        #
+# [XXXXX] 22-05-2019 00-09-03        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imac
@@ -9,3 +9,4 @@ RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
 
 TARGET_TAGS=board jlink
+TARGET_DHRY_ITERS=20000000
diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk
index ed70259..b4b69dc 100644
--- a/bsp/sifive-hifive1/settings.mk
+++ b/bsp/sifive-hifive1/settings.mk
@@ -1,7 +1,7 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 20-05-2019 14-26-11        #
+# [XXXXX] 22-05-2019 00-09-03        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imac
@@ -9,3 +9,4 @@ RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
 
 TARGET_TAGS=board openocd
+TARGET_DHRY_ITERS=20000000
diff --git a/scripts/standalone.mk b/scripts/standalone.mk
index 913b24b..6b83a29 100644
--- a/scripts/standalone.mk
+++ b/scripts/standalone.mk
@@ -37,6 +37,12 @@ ifeq ($(RISCV_CMODEL),)
 RISCV_CMODEL = medany
 endif
 
+ifeq ($(PROGRAM),dhrystone)
+ifeq ($(LINK_TARGET),)
+LINK_TARGET = ramrodata
+endif
+endif
+
 ifeq ($(LINK_TARGET),)
 LINK_TARGET = default
 endif
@@ -101,6 +107,20 @@ RISCV_CCASFLAGS += --specs=nano.specs
 RISCV_CFLAGS    += --specs=nano.specs
 RISCV_CXXFLAGS  += --specs=nano.specs
 
+ifeq ($(PROGRAM),dhrystone)
+ifeq ($(DHRY_OPTION),)
+# Ground rules (default)
+RISCV_XCFLAGS += -mexplicit-relocs -fno-inline
+else ifeq ($(DHRY_OPTION),fast)
+# With inline and without lto
+RISCV_XCFLAGS += -mexplicit-relocs -finline
+else ifeq ($(DHRY_OPTION),best)
+# Best Score
+RISCV_XCFLAGS += -finline -flto -fwhole-program
+endif
+RISCV_XCFLAGS += -DDHRY_ITERS=$(TARGET_DHRY_ITERS)
+endif
+
 # Turn on garbage collection for unused sections
 RISCV_LDFLAGS += -Wl,--gc-sections
 # Turn on linker map file generation
@@ -152,6 +172,7 @@ $(PROGRAM_ELF): \
 		CCASFLAGS="$(RISCV_CCASFLAGS)" \
 		CFLAGS="$(RISCV_CFLAGS)" \
 		CXXFLAGS="$(RISCV_CXXFLAGS)" \
+		XCFLAGS="$(RISCV_XCFLAGS)" \
 		LDFLAGS="$(RISCV_LDFLAGS)" \
 		LDLIBS="$(RISCV_LDLIBS)"
 	mv $(SRC_DIR)/$(basename $(notdir $@)).map $(dir $@)
diff --git a/software/dhrystone b/software/dhrystone
-Subproject 70d0c0e68ae6a6e7eb1d3083b93849ecc9bde16
+Subproject 9065af831e30aabfef7772ddef874bc6bf5c071