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authorNathaniel Graff <nathaniel.graff@sifive.com>2018-12-19 15:15:32 -0800
committerNathaniel Graff <nathaniel.graff@sifive.com>2019-01-03 12:50:22 -0800
commitf04c1a9df045903204d8018c71b2a028494bbac9 (patch)
tree385507dde477edfeea11843e7574608d226374ed
parent9d9aaf6e13a52af606cc795b7f8d6ac5f37d4c3d (diff)
Add fixed-clocks to Arty boards
The serial device needs a clock in the DTS to initialize. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
-rw-r--r--bsp/coreip-e31-arty/design.dts6
-rw-r--r--bsp/coreip-s51-arty/design.dts6
2 files changed, 12 insertions, 0 deletions
diff --git a/bsp/coreip-e31-arty/design.dts b/bsp/coreip-e31-arty/design.dts
index 2e9eaff..fcefbb7 100644
--- a/bsp/coreip-e31-arty/design.dts
+++ b/bsp/coreip-e31-arty/design.dts
@@ -40,6 +40,11 @@
#size-cells = <1>;
compatible = "SiFive,FE310G-soc", "fe310-soc", "sifive-soc", "simple-bus";
ranges;
+ hfclk: clock@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32500000>;
+ };
L1: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L3 3 &L3 7>;
@@ -105,6 +110,7 @@
interrupts = <5>;
reg = <0x20000000 0x1000>;
reg-names = "control";
+ clocks = <&hfclk>;
};
L12: spi@20004000 {
compatible = "sifive,spi0";
diff --git a/bsp/coreip-s51-arty/design.dts b/bsp/coreip-s51-arty/design.dts
index 23362f2..c0813ca 100644
--- a/bsp/coreip-s51-arty/design.dts
+++ b/bsp/coreip-s51-arty/design.dts
@@ -40,6 +40,11 @@
#size-cells = <1>;
compatible = "SiFive,FE510G-soc", "fe510-soc", "sifive-soc", "simple-bus";
ranges;
+ hfclk: clock@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32500000>;
+ };
L1: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L3 3 &L3 7>;
@@ -105,6 +110,7 @@
interrupts = <5>;
reg = <0x20000000 0x1000>;
reg-names = "control";
+ clocks = <&hfclk>;
};
L12: spi@20004000 {
compatible = "sifive,spi0";