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| author | dbarbi1 <dbarbi1@gmail.com> | 2018-01-23 00:04:06 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-01-23 00:04:06 -0600 |
| commit | 9421a2918575b94ecc4588bbf1556261d4f02c85 (patch) | |
| tree | 27d8141a10d3caa7564e97e3a9a7b252cb87c8b9 /FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg | |
| parent | 86b06dccf1f09d5e7ac88acfb4d261062fc4a0aa (diff) | |
| parent | a121ed6c7ebc8990bab5afed358ba025323c7435 (diff) | |
Merge pull request #86 from sifive/fs3
Fs3
Diffstat (limited to 'FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg')
| -rw-r--r-- | FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg new file mode 100644 index 0000000..8b382dc --- /dev/null +++ b/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" |