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| author | Bunnaroath Sou <bsou@sifive.com> | 2019-03-18 18:35:55 -0700 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-03-18 18:35:55 -0700 |
| commit | 453ec9a253c7d8b1e1b5ddc6f14d4d14f670f9a3 (patch) | |
| tree | b4533403e6354376fefb83ec0f1cc5ab53c883c7 /FreedomStudio/E51FPGA/coreplexip_welcome | |
| parent | 44c064f651cf4756f44fb96d542a8db2d4a33471 (diff) | |
Make rtl target to use ram from dtim, flash from testram
Diffstat (limited to 'FreedomStudio/E51FPGA/coreplexip_welcome')
0 files changed, 0 insertions, 0 deletions