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| author | Andrew Waterman <andrew@sifive.com> | 2017-01-03 17:58:18 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-01-03 18:53:37 -0800 |
| commit | 628d2b3559be5e9e651801d289a075d68df820e8 (patch) | |
| tree | dae389ef596acd1f773b647d7c6cc4bbcc74a732 /FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg | |
| parent | 005b1a8f84ff743710ebd693b70d208da583098d (diff) | |
Compile Dhrystone without RVC
Branch target misalignment reduces performance by about 10%.
Diffstat (limited to 'FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg')
0 files changed, 0 insertions, 0 deletions