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| author | Scott Johnson <scottj@sifive.com> | 2016-12-07 18:05:38 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-12-07 18:05:38 -0800 |
| commit | 7011ca48a2ef9205184a03a854ba310ebcda0e40 (patch) | |
| tree | 3264e0a12875a55a1d2458bb254faabbab2cc081 /FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg | |
| parent | 9ad15e8896557e9526a12e868801ed5e7d320298 (diff) | |
| parent | e0f235fc5344ccf79fa0e5bdd64591aef3814799 (diff) | |
Merge pull request #17 from sifive/enable-fpu
Enable FPU in MSTATUS CSR during init
Diffstat (limited to 'FreedomStudio/E51FPGA/dhrystone/sifive-coreplexip-e51-arty.cfg')
0 files changed, 0 insertions, 0 deletions