diff options
| author | Drew Barbier <dbarbi1@gmail.com> | 2018-07-11 21:34:21 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-11 21:34:21 -0700 |
| commit | 67a27655c3b7d3955703850ca0ac6d4c8b6b38ca (patch) | |
| tree | ba4b67cf6acd69ffb52c4d2177564d00aad02b1f /FreedomStudio | |
| parent | b091d1cabe70c84825a7f304d725010d2cf163d9 (diff) | |
| parent | 7bf718778b9710238d791cefc67ac9c8720985e2 (diff) | |
Merge pull request #96 from sifive/clic-vectored
Clic vectored
Diffstat (limited to 'FreedomStudio')
| -rw-r--r-- | FreedomStudio/E2FPGA/clic_vectored/.cproject | 208 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/clic_vectored/.gitignore | 1 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/clic_vectored/.project | 358 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/clic_vectored/clic_vectored OpenOCD.launch | 61 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/clic_vectored/sifive-coreip-e2-arty.cfg | 31 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/coreplexip_welcome/.cproject | 210 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/coreplexip_welcome/.gitignore | 1 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/coreplexip_welcome/.project | 358 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch | 61 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg | 31 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/dhrystone/.cproject | 216 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/dhrystone/.gitignore | 1 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/dhrystone/.project | 373 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/dhrystone/dhrystone OpenOCD.launch | 61 | ||||
| -rw-r--r-- | FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg | 31 |
15 files changed, 2002 insertions, 0 deletions
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b/FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git 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<locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>bsp/drivers/fe300prci/fe300prci_driver.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c</locationURI> + </link> + <link> + <name>bsp/env/coreip-e2-arty/tim-split.lds</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim-split.lds</locationURI> + </link> + <link> + <name>bsp/env/coreip-e2-arty/tim.lds</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim.lds</locationURI> + </link> + <link> + <name>bsp/env/coreip-e2-arty/flash.lds</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/flash.lds</locationURI> + </link> + <link> + <name>bsp/env/coreip-e2-arty/init.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/init.c</locationURI> + </link> + <link> + <name>bsp/env/coreip-e2-arty/openocd.cfg</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/openocd.cfg</locationURI> + </link> + <link> + <name>bsp/env/coreip-e2-arty/platform.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/platform.h</locationURI> + </link> + <link> + <name>bsp/env/coreip-e2-arty/scratchpad.lds</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/scratchpad.lds</locationURI> + </link> + <link> + <name>bsp/env/coreip-e2-arty/settings.mk</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/settings.mk</locationURI> + </link> + <link> + <name>bsp/include/sifive/bits.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/const.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices</name> + <type>2</type> + <locationURI>virtual:/virtual</locationURI> + </link> + <link> + <name>bsp/include/sifive/sections.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/smp.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI> + </link> + <link> + <name>bsp/libwrap/misc/write_hex.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI> + </link> + <link> + <name>bsp/libwrap/stdlib/malloc.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/_exit.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/close.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/execve.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/fork.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/fstat.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/getpid.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/isatty.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/kill.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/link.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/lseek.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/open.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/openat.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/puts.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/read.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/sbrk.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/stat.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/stub.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/times.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/unlink.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/wait.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/weak_under_alias.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI> + </link> + <link> + <name>bsp/libwrap/sys/write.c</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/aon.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/clint.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/gpio.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/otp.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/plic.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/prci.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/pwm.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/spi.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h</locationURI> + </link> + <link> + <name>bsp/include/sifive/devices/uart.h</name> + <type>1</type> + <locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h</locationURI> + </link> + </linkedResources> +</projectDescription> diff --git a/FreedomStudio/E2FPGA/dhrystone/dhrystone OpenOCD.launch b/FreedomStudio/E2FPGA/dhrystone/dhrystone OpenOCD.launch new file mode 100644 index 0000000..f996fc4 --- /dev/null +++ b/FreedomStudio/E2FPGA/dhrystone/dhrystone OpenOCD.launch @@ -0,0 +1,61 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType"> +<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/> +<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="true"/> +<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/> +<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/> +<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/> +<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/> +<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/> +<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/> +<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off set arch riscv:rv32"/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${openocd_path}/${openocd_executable}"/> +<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreip-e2-arty.cfg"/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/> +<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/> +<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/> +<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/> +<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/> +<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/> +<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/> +<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/> +<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/dhrystone.elf"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dhrystone"/> +<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> +<listEntry value="/dhrystone"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> +<listEntry value="4"/> +</listAttribute> +<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/> +<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/> +</launchConfiguration> diff --git a/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg b/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg new file mode 100644 index 0000000..8b382dc --- /dev/null +++ b/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" |