project and debug launch updates for beta 3

38 files changed, 21031 insertions, 10 deletions

diff --git a/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome JLINK.launch b/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome JLINK.launch
new file mode 100644
index 0000000..dad28c2
--- /dev/null
+++ b/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome JLINK.launch
@@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;peripherals/&gt;&#10;"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihosting" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSwo" value="true"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv32"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="jtag"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="FE310"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="4000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun -strict -timeout 0 -nogui"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="4000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e31arty-xsvd.json"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/coreplexip_welcome.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="coreplexip_welcome"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/coreplexip_welcome"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome Debug.launch b/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
index 0bad4ba..b416a5c 100644
--- a/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome Debug.launch
+++ b/FreedomStudio/E31FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
@@ -1,11 +1,13 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;peripherals/&gt;&#10;"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
@@ -16,10 +18,12 @@
 <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-coreplexip-e31-arty.cfg"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
 <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e31arty-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
@@ -47,7 +51,7 @@
 <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/coreplexip_welcome.elf"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="coreplexip_welcome"/>
 <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"/>
 <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
 <listEntry value="/coreplexip_welcome"/>
 </listAttribute>
diff --git a/FreedomStudio/E31FPGA/coreplexip_welcome/e31arty-xsvd.json b/FreedomStudio/E31FPGA/coreplexip_welcome/e31arty-xsvd.json
new file mode 100644
index 0000000..4879d45
--- /dev/null
+++ b/FreedomStudio/E31FPGA/coreplexip_welcome/e31arty-xsvd.json
@@ -0,0 +1,1250 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e31arty": {
+      "displayName": "Core Complex E31 Arty",
+      "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "32",
+      "resetMask": "all",
+      "resetValue": "0x00000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
+      "headerTypePrefix": "sifive_e31arty_",
+      "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e31": {
+          "harts": "1",
+          "isa": "RV32IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            }
+          },
+          "clusters": {
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "registers": {
+                "low": {
+                  "description": "Machine Compare Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Compare Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "registers": {
+                "low": {
+                  "description": "Machine Time Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Time Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "8",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "8",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/global_interrupts/e31arty-xsvd.json b/FreedomStudio/E31FPGA/global_interrupts/e31arty-xsvd.json
new file mode 100644
index 0000000..4879d45
--- /dev/null
+++ b/FreedomStudio/E31FPGA/global_interrupts/e31arty-xsvd.json
@@ -0,0 +1,1250 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e31arty": {
+      "displayName": "Core Complex E31 Arty",
+      "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "32",
+      "resetMask": "all",
+      "resetValue": "0x00000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
+      "headerTypePrefix": "sifive_e31arty_",
+      "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e31": {
+          "harts": "1",
+          "isa": "RV32IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            }
+          },
+          "clusters": {
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "registers": {
+                "low": {
+                  "description": "Machine Compare Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Compare Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "registers": {
+                "low": {
+                  "description": "Machine Time Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Time Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "8",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "8",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/global_interrupts/global_interrupts JLINK.launch b/FreedomStudio/E31FPGA/global_interrupts/global_interrupts JLINK.launch
new file mode 100644
index 0000000..64ac376
--- /dev/null
+++ b/FreedomStudio/E31FPGA/global_interrupts/global_interrupts JLINK.launch
@@ -0,0 +1,80 @@
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+<listEntry value="4"/>
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+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
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diff --git a/FreedomStudio/E31FPGA/global_interrupts/global_interrupts Debug.launch b/FreedomStudio/E31FPGA/global_interrupts/global_interrupts OpenOcd.launch
index e197508..85d68df 100644
--- a/FreedomStudio/E31FPGA/global_interrupts/global_interrupts Debug.launch
+++ b/FreedomStudio/E31FPGA/global_interrupts/global_interrupts OpenOcd.launch
@@ -20,6 +20,7 @@
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 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e31arty-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
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diff --git a/FreedomStudio/E31FPGA/local_interrupts/e31arty-xsvd.json b/FreedomStudio/E31FPGA/local_interrupts/e31arty-xsvd.json
new file mode 100644
index 0000000..4879d45
--- /dev/null
+++ b/FreedomStudio/E31FPGA/local_interrupts/e31arty-xsvd.json
@@ -0,0 +1,1250 @@
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+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e31arty": {
+      "displayName": "Core Complex E31 Arty",
+      "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "32",
+      "resetMask": "all",
+      "resetValue": "0x00000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
+      "headerTypePrefix": "sifive_e31arty_",
+      "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e31": {
+          "harts": "1",
+          "isa": "RV32IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            }
+          },
+          "clusters": {
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "registers": {
+                "low": {
+                  "description": "Machine Compare Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Compare Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "registers": {
+                "low": {
+                  "description": "Machine Time Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Time Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "8",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "8",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/local_interrupts/local_interrupts JLINK.launch b/FreedomStudio/E31FPGA/local_interrupts/local_interrupts JLINK.launch
new file mode 100644
index 0000000..7ea0908
--- /dev/null
+++ b/FreedomStudio/E31FPGA/local_interrupts/local_interrupts JLINK.launch
@@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv32"/>
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+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
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+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
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+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
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+<listEntry value="/local_interrupts"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
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+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/FreedomStudio/E31FPGA/local_interrupts/local_interrupts Debug.launch b/FreedomStudio/E31FPGA/local_interrupts/local_interrupts OpenOCD.launch
index 192ffc6..7dd3232 100644
--- a/FreedomStudio/E31FPGA/local_interrupts/local_interrupts Debug.launch
+++ b/FreedomStudio/E31FPGA/local_interrupts/local_interrupts OpenOCD.launch
@@ -20,6 +20,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e31arty-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/E31FPGA/performance_counters/e31arty-xsvd.json b/FreedomStudio/E31FPGA/performance_counters/e31arty-xsvd.json
new file mode 100644
index 0000000..4879d45
--- /dev/null
+++ b/FreedomStudio/E31FPGA/performance_counters/e31arty-xsvd.json
@@ -0,0 +1,1250 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e31arty": {
+      "displayName": "Core Complex E31 Arty",
+      "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "32",
+      "resetMask": "all",
+      "resetValue": "0x00000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
+      "headerTypePrefix": "sifive_e31arty_",
+      "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e31": {
+          "harts": "1",
+          "isa": "RV32IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            }
+          },
+          "clusters": {
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "registers": {
+                "low": {
+                  "description": "Machine Compare Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Compare Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "registers": {
+                "low": {
+                  "description": "Machine Time Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Time Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "8",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "8",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/performance_counters/performance_counters JLINK.launch b/FreedomStudio/E31FPGA/performance_counters/performance_counters JLINK.launch
new file mode 100644
index 0000000..d3f38d9
--- /dev/null
+++ b/FreedomStudio/E31FPGA/performance_counters/performance_counters JLINK.launch
@@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
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+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
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+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
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+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv32"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="jtag"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
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+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun -strict -timeout 0 -nogui"/>
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+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
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+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e31arty-xsvd.json"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
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+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
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+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
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+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/performance_counters.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="performance_counters"/>
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+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/performance_counters"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/FreedomStudio/E31FPGA/performance_counters/performance_counters Debug.launch b/FreedomStudio/E31FPGA/performance_counters/performance_counters OpenOCD.launch
index b747520..8b9c5cb 100644
--- a/FreedomStudio/E31FPGA/performance_counters/performance_counters Debug.launch
+++ b/FreedomStudio/E31FPGA/performance_counters/performance_counters OpenOCD.launch
@@ -20,6 +20,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
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 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e31arty-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
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diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/e31arty-xsvd.json b/FreedomStudio/E31FPGA/vectored_interrupts/e31arty-xsvd.json
new file mode 100644
index 0000000..4879d45
--- /dev/null
+++ b/FreedomStudio/E31FPGA/vectored_interrupts/e31arty-xsvd.json
@@ -0,0 +1,1250 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e31arty": {
+      "displayName": "Core Complex E31 Arty",
+      "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "32",
+      "resetMask": "all",
+      "resetValue": "0x00000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
+      "headerTypePrefix": "sifive_e31arty_",
+      "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e31": {
+          "harts": "1",
+          "isa": "RV32IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            }
+          },
+          "clusters": {
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "registers": {
+                "low": {
+                  "description": "Machine Compare Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Compare Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "registers": {
+                "low": {
+                  "description": "Machine Time Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Time Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "8",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "8",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts JLINK.launch b/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts JLINK.launch
new file mode 100644
index 0000000..3751177
--- /dev/null
+++ b/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts JLINK.launch
@@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;peripherals/&gt;&#10;"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihosting" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSwo" value="true"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#10;set arch riscv:rv32"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="jtag"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="FE310"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="4000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun -strict -timeout 0 -nogui"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="4000"/>
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+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e31arty-xsvd.json"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/vectored_interrupts.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="vectored_interrupts"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.1419430722"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/vectored_interrupts"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts Debug.launch b/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch
index 73f5aaa..df86386 100644
--- a/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts Debug.launch
+++ b/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch
@@ -20,6 +20,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e31arty-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
index 514d098..94913a8 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
@@ -41,7 +41,7 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.632559401" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1722118225" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.lp64" valueType="enumerated"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.427474672" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
 							<builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch b/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
index 81a28b7..af063ab 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
@@ -20,6 +20,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json b/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e51arty": {
+      "displayName": "Core Complex E51 Arty",
+      "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "64",
+      "resetMask": "all",
+      "resetValue": "0x0000000000000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+      "headerTypePrefix": "sifive_e51arty_",
+      "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e51": {
+          "harts": "1",
+          "isa": "RV64IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            },
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "regWidth": "64"
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "regWidth": "64"
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "16",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "16",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/global_interrupts/.cproject b/FreedomStudio/E51FPGA/global_interrupts/.cproject
index fc04722..f3ce67a 100644
--- a/FreedomStudio/E51FPGA/global_interrupts/.cproject
+++ b/FreedomStudio/E51FPGA/global_interrupts/.cproject
@@ -41,7 +41,7 @@
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+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
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diff --git a/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json b/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/global_interrupts/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e51arty": {
+      "displayName": "Core Complex E51 Arty",
+      "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "64",
+      "resetMask": "all",
+      "resetValue": "0x0000000000000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+      "headerTypePrefix": "sifive_e51arty_",
+      "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e51": {
+          "harts": "1",
+          "isa": "RV64IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            },
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "regWidth": "64"
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "regWidth": "64"
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "16",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "16",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/global_interrupts/global_interrupts Debug.launch b/FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch
index 93d9f58..6a7abd3 100644
--- a/FreedomStudio/E51FPGA/global_interrupts/global_interrupts Debug.launch
+++ b/FreedomStudio/E51FPGA/global_interrupts/global_interrupts OpenOCD.launch
@@ -20,6 +20,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/E51FPGA/local_interrupts/.cproject b/FreedomStudio/E51FPGA/local_interrupts/.cproject
index fc04722..f3ce67a 100644
--- a/FreedomStudio/E51FPGA/local_interrupts/.cproject
+++ b/FreedomStudio/E51FPGA/local_interrupts/.cproject
@@ -41,7 +41,7 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.632559401" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1722118225" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.lp64" valueType="enumerated"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.1122876700" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
 							<builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
diff --git a/FreedomStudio/E51FPGA/local_interrupts/e51arty-xsvd.json b/FreedomStudio/E51FPGA/local_interrupts/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/local_interrupts/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e51arty": {
+      "displayName": "Core Complex E51 Arty",
+      "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "64",
+      "resetMask": "all",
+      "resetValue": "0x0000000000000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+      "headerTypePrefix": "sifive_e51arty_",
+      "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e51": {
+          "harts": "1",
+          "isa": "RV64IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            },
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "regWidth": "64"
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "regWidth": "64"
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "16",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "16",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/local_interrupts/local_interrupts Debug.launch b/FreedomStudio/E51FPGA/local_interrupts/local_interrupts OpenOCD.launch
index 04cb6e6..04cb6e6 100644
--- a/FreedomStudio/E51FPGA/local_interrupts/local_interrupts Debug.launch
+++ b/FreedomStudio/E51FPGA/local_interrupts/local_interrupts OpenOCD.launch
diff --git a/FreedomStudio/E51FPGA/performance_counters/.cproject b/FreedomStudio/E51FPGA/performance_counters/.cproject
index 84f7a26..d0fac1c 100644
--- a/FreedomStudio/E51FPGA/performance_counters/.cproject
+++ b/FreedomStudio/E51FPGA/performance_counters/.cproject
@@ -41,7 +41,7 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.632559401" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1722118225" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.lp64" valueType="enumerated"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.1122876700" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
 							<builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
diff --git a/FreedomStudio/E51FPGA/performance_counters/e51arty-xsvd.json b/FreedomStudio/E51FPGA/performance_counters/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/performance_counters/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e51arty": {
+      "displayName": "Core Complex E51 Arty",
+      "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "64",
+      "resetMask": "all",
+      "resetValue": "0x0000000000000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+      "headerTypePrefix": "sifive_e51arty_",
+      "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e51": {
+          "harts": "1",
+          "isa": "RV64IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            },
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "regWidth": "64"
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "regWidth": "64"
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "16",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "16",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/performance_counters/performance_counters Debug.launch b/FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch
index 4b980ad..c31f256 100644
--- a/FreedomStudio/E51FPGA/performance_counters/performance_counters Debug.launch
+++ b/FreedomStudio/E51FPGA/performance_counters/performance_counters OpenOCD.launch
@@ -20,6 +20,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.cproject b/FreedomStudio/E51FPGA/vectored_interrupts/.cproject
index c50fa56..c9a217f 100644
--- a/FreedomStudio/E51FPGA/vectored_interrupts/.cproject
+++ b/FreedomStudio/E51FPGA/vectored_interrupts/.cproject
@@ -41,7 +41,7 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.632559401" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1722118225" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.lp64" valueType="enumerated"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.1122876700" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
 							<builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json b/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/vectored_interrupts/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e51arty": {
+      "displayName": "Core Complex E51 Arty",
+      "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "64",
+      "resetMask": "all",
+      "resetValue": "0x0000000000000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+      "headerTypePrefix": "sifive_e51arty_",
+      "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e51": {
+          "harts": "1",
+          "isa": "RV64IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            },
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "regWidth": "64"
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "regWidth": "64"
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "16",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "16",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch b/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch
index b25a5d2..4f1862d 100644
--- a/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch
+++ b/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch
@@ -20,6 +20,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/E51FPGA/wrap-E51FPGA/.cproject b/FreedomStudio/E51FPGA/wrap-E51FPGA/.cproject
index 5eaec6b..d756c3e 100644
--- a/FreedomStudio/E51FPGA/wrap-E51FPGA/.cproject
+++ b/FreedomStudio/E51FPGA/wrap-E51FPGA/.cproject
@@ -46,10 +46,10 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1794512381" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.487010586" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.364487762" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.1947169168" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.lp64" valueType="enumerated"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.1947169168" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.1938916358" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.699758630" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
-							<builder buildPath="${workspace_loc:/wrap-E51FPGA}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1315668301" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
+							<builder buildPath="${workspace_loc:/wrap-E51FPGA}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.1315668301" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="false" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
 							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.591864289" name="GNU RISC-V Cross Assembler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler">
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1857953841" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 								<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input.624389828" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input"/>
diff --git a/FreedomStudio/E51FPGA/wrap-E51FPGA/e51arty-xsvd.json b/FreedomStudio/E51FPGA/wrap-E51FPGA/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/wrap-E51FPGA/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e51arty": {
+      "displayName": "Core Complex E51 Arty",
+      "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "64",
+      "resetMask": "all",
+      "resetValue": "0x0000000000000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+      "headerTypePrefix": "sifive_e51arty_",
+      "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e51": {
+          "harts": "1",
+          "isa": "RV64IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            },
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "regWidth": "64"
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "regWidth": "64"
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "16",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "16",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/HiFive1/demo_gpio/demo_gpio OpenOCD.launch b/FreedomStudio/HiFive1/demo_gpio/demo_gpio OpenOCD.launch
index b082d2a..daada7b 100644
--- a/FreedomStudio/HiFive1/demo_gpio/demo_gpio OpenOCD.launch
+++ b/FreedomStudio/HiFive1/demo_gpio/demo_gpio OpenOCD.launch
@@ -6,6 +6,7 @@
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="false"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
@@ -16,10 +17,12 @@
 <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-f sifive-freedom-e300-hifive1.cfg"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
 <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/fe310-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
@@ -40,10 +43,9 @@
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
 <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
 <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
 <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
 <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/demo_gpio.elf"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="demo_gpio"/>
 <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
diff --git a/FreedomStudio/HiFive1/demo_gpio/fe310-xsvd.json b/FreedomStudio/HiFive1/demo_gpio/fe310-xsvd.json
new file mode 100644
index 0000000..1722e54
--- /dev/null
+++ b/FreedomStudio/HiFive1/demo_gpio/fe310-xsvd.json
@@ -0,0 +1,2325 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "fe310": {
+      "displayName": "Freedom E310-G000",
+      "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "32",
+      "resetMask": "all",
+      "resetValue": "0x00000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_FE310_",
+      "headerTypePrefix": "sifive_fe310_",
+      "headerInterruptPrefix": "sifive_fe310_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "51",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e31": {
+          "harts": "1",
+          "isa": "RV32IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            }
+          },
+          "numLocalInterrupts": "0"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            }
+          },
+          "clusters": {
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "registers": {
+                "low": {
+                  "description": "Machine Compare Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Compare Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "registers": {
+                "low": {
+                  "description": "Machine Time Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Time Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "52",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "2",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "2",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          }
+        },
+        "wdog": {
+          "description": "Watchdog Timer (WDT), part of Always-On Domain",
+          "baseAddress": "0x10000000",
+          "size": "0x0040",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "Watchdog Configuration Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "scale": {
+                  "description": "Watchdog counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "rsten": {
+                  "description": "Watchdog full reset enable",
+                  "bitOffset": "8",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "zerocmp": {
+                  "description": "Watchdog zero on comparator",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Watchdog enable counter always",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "encoreawake": {
+                  "description": "Watchdog counter only when awake",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmpip": {
+                  "description": "Watchdog interrupt pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Watchdog Count Register",
+              "addressOffset": "0x0008"
+            },
+            "scale": {
+              "description": "Watchdog Scale Register",
+              "addressOffset": "0x0010",
+              "fields": {
+                "value": {
+                  "description": "Watchdog scale value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "feed": {
+              "description": "Watchdog Feed Address Register",
+              "addressOffset": "0x0018"
+            },
+            "key": {
+              "description": "Watchdog Key Register",
+              "addressOffset": "0x001C"
+            },
+            "cmp": {
+              "description": "Watchdog Compare Register",
+              "addressOffset": "0x0020",
+              "fields": {
+                "value": {
+                  "description": "Watchdog compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "wdogcmp": {
+              "description": "Watchdog Compare Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "rtc": {
+          "description": "Real-Time Clock (RTC), part of Always-On Domain",
+          "baseAddress": "0x10000040",
+          "size": "0x0030",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "RTC Configuration Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "scale": {
+                  "description": "RTC clock rate scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "enalways": {
+                  "description": "RTC counter enable",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmpip": {
+                  "description": "RTC comparator interrupt pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "low": {
+              "description": "RTC Counter Register Low",
+              "addressOffset": "0x0008"
+            },
+            "high": {
+              "description": "RTC Counter Register High",
+              "addressOffset": "0x000C",
+              "fields": {
+                "value": {
+                  "description": "RTC counter register, high bits",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "scale": {
+              "description": "RTC Scale Register",
+              "addressOffset": "0x0010"
+            },
+            "cmp": {
+              "description": "RTC Compare Register",
+              "addressOffset": "0x0020"
+            }
+          },
+          "interrupts": {
+            "rtccmp": {
+              "description": "RTC Compare Interrupt",
+              "value": "2"
+            }
+          }
+        },
+        "pmu": {
+          "description": "Power-Management Unit (PMU), part of Always-On Domain",
+          "baseAddress": "0x10000100",
+          "size": "0x0050",
+          "resetMask": "none",
+          "registers": {
+            "wakeupi": {
+              "description": "Wakeup program instruction Registers",
+              "addressOffset": "0x0000",
+              "arraySize": "8"
+            },
+            "sleepi": {
+              "description": "Sleep Program Instruction Registers",
+              "addressOffset": "0x0020",
+              "arraySize": "8"
+            },
+            "ie": {
+              "description": "PMU Interrupt Enables Register",
+              "addressOffset": "0x0040",
+              "fields": {
+                "rtc": {
+                  "description": "RTC Comparator active",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                },
+                "dwakeup": {
+                  "description": "dwakeup_n pin active",
+                  "bitOffset": "2",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "cause": {
+              "description": "PMU Wakeup Cause Register",
+              "addressOffset": "0x0044",
+              "fields": {
+                "wakeupcause": {
+                  "description": "Wakeup cause",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "access": "r",
+                  "enumerations": {
+                    "wakeupcause-enum": {
+                      "description": "Wakeup Cause Values Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "reset",
+                          "description": "Reset Wakeup"
+                        },
+                        "1": {
+                          "displayName": "rtc",
+                          "description": "RTC Wakeup"
+                        },
+                        "2": {
+                          "displayName": "dwakeup",
+                          "description": "Digital input Wakeup"
+                        },
+                        "*": {
+                          "displayName": "undefined"
+                        }
+                      }
+                    }
+                  }
+                },
+                "resetcause": {
+                  "description": "Reset cause",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "access": "r",
+                  "enumerations": {
+                    "resetcause-enum": {
+                      "description": "Reset Cause Values Enumeration",
+                      "values": {
+                        "1": {
+                          "displayName": "external",
+                          "description": "External reset"
+                        },
+                        "2": {
+                          "displayName": "watchdog",
+                          "description": "Watchdog timer reset"
+                        },
+                        "*": {
+                          "displayName": "undefined"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "sleep": {
+              "description": "PMU Initiate Sleep Sequence Register",
+              "addressOffset": "0x0048"
+            },
+            "key": {
+              "description": "PMU Key Register",
+              "addressOffset": "0x004C"
+            }
+          }
+        },
+        "aon": {
+          "description": "Always-On (AON) Domain",
+          "baseAddress": "0x10000070",
+          "size": "0x0090",
+          "resetMask": "none",
+          "registers": {
+            "lfrosccfg": {
+              "description": "Internal Programmable Low-Frequency Ring Oscillator Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "div": {
+                  "description": "LFROSC divider",
+                  "bitOffset": "0",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x04"
+                },
+                "trim": {
+                  "description": "LFROSC trim value",
+                  "bitOffset": "16",
+                  "bitWidth": "5",
+                  "resetMask": "all",
+                  "resetValue": "0x10"
+                },
+                "en": {
+                  "description": "LFROSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "LFROSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "backup": {
+              "description": "Backup Registers",
+              "addressOffset": "0x0010",
+              "arraySize": "32"
+            }
+          }
+        },
+        "prci": {
+          "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",
+          "baseAddress": "0x10008000",
+          "size": "0x8000",
+          "registers": {
+            "hfrosccfg": {
+              "description": "Internal Trimmable Programmable 72 MHz Oscillator Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "div": {
+                  "description": "HFROSC divider",
+                  "bitOffset": "0",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x04"
+                },
+                "trim": {
+                  "description": "HFROSC trim value",
+                  "bitOffset": "16",
+                  "bitWidth": "5",
+                  "resetMask": "all",
+                  "resetValue": "0x10"
+                },
+                "en": {
+                  "description": "HFROSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "HFROSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "hfxosccfg": {
+              "description": "External 16 MHz Crystal Oscillator Register",
+              "addressOffset": "0x0004",
+              "fields": {
+                "en": {
+                  "description": "HFXOSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "HFXOSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "pllcfg": {
+              "description": "Internal High-Frequency PLL (HFPLL) Register",
+              "addressOffset": "0x0008",
+              "fields": {
+                "r": {
+                  "description": "PLL R input divider value",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "pllr-enum": {
+                      "description": "Reference Clock R Divide Ratio Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "/1",
+                          "headerName": "div1",
+                          "description": "Unchanged"
+                        },
+                        "1": {
+                          "displayName": "/2",
+                          "headerName": "div2",
+                          "description": "Divided by 2"
+                        },
+                        "2": {
+                          "displayName": "/3",
+                          "headerName": "div3",
+                          "description": "Divided by 3"
+                        },
+                        "3": {
+                          "displayName": "/4",
+                          "headerName": "div4",
+                          "description": "Divided by 4"
+                        }
+                      }
+                    }
+                  }
+                },
+                "f": {
+                  "description": "PLL F multiplier value",
+                  "bitOffset": "4",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x1F",
+                  "enumerations": {
+                    "pllf-enum": {
+                      "description": "Reference Clock F Multiplier Ratio Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "*2",
+                          "headerName": "mul2",
+                          "description": "Multiplied by 2"
+                        },
+                        "1": {
+                          "displayName": "*4",
+                          "headerName": "mul4",
+                          "description": "Multiplied by 4"
+                        },
+                        "2": {
+                          "displayName": "*6",
+                          "headerName": "mul6",
+                          "description": "Multiplied by 6"
+                        },
+                        "3": {
+                          "displayName": "*8",
+                          "headerName": "mul8",
+                          "description": "Multiplied by 8"
+                        },
+                        "4": {
+                          "displayName": "*10",
+                          "headerName": "mul10",
+                          "description": "Multiplied by 10"
+                        },
+                        "5": {
+                          "displayName": "*12",
+                          "headerName": "mul12",
+                          "description": "Multiplied by 12"
+                        },
+                        "6": {
+                          "displayName": "*14",
+                          "headerName": "mul14",
+                          "description": "Multiplied by 14"
+                        },
+                        "7": {
+                          "displayName": "*16",
+                          "headerName": "mul16",
+                          "description": "Multiplied by 16"
+                        },
+                        "8": {
+                          "displayName": "*18",
+                          "headerName": "mul18",
+                          "description": "Multiplied by 18"
+                        },
+                        "9": {
+                          "displayName": "*20",
+                          "headerName": "mul20",
+                          "description": "Multiplied by 20"
+                        },
+                        "10": {
+                          "displayName": "*22",
+                          "headerName": "mul22",
+                          "description": "Multiplied by 22"
+                        },
+                        "11": {
+                          "displayName": "*24",
+                          "headerName": "mul24",
+                          "description": "Multiplied by 24"
+                        },
+                        "12": {
+                          "displayName": "*26",
+                          "headerName": "mul26",
+                          "description": "Multiplied by 26"
+                        },
+                        "13": {
+                          "displayName": "*28",
+                          "headerName": "mul28",
+                          "description": "Multiplied by 28"
+                        },
+                        "14": {
+                          "displayName": "*30",
+                          "headerName": "mul30",
+                          "description": "Multiplied by 30"
+                        },
+                        "15": {
+                          "displayName": "*32",
+                          "headerName": "mul32",
+                          "description": "Multiplied by 32"
+                        },
+                        "16": {
+                          "displayName": "*34",
+                          "headerName": "mul34",
+                          "description": "Multiplied by 34"
+                        },
+                        "17": {
+                          "displayName": "*36",
+                          "headerName": "mul36",
+                          "description": "Multiplied by 36"
+                        },
+                        "18": {
+                          "displayName": "*38",
+                          "headerName": "mul38",
+                          "description": "Multiplied by 38"
+                        },
+                        "19": {
+                          "displayName": "*40",
+                          "headerName": "mul40",
+                          "description": "Multiplied by 40"
+                        },
+                        "20": {
+                          "displayName": "*42",
+                          "headerName": "mul42",
+                          "description": "Multiplied by 42"
+                        },
+                        "21": {
+                          "displayName": "*44",
+                          "headerName": "mul44",
+                          "description": "Multiplied by 44"
+                        },
+                        "22": {
+                          "displayName": "*46",
+                          "headerName": "mul46",
+                          "description": "Multiplied by 46"
+                        },
+                        "23": {
+                          "displayName": "*48",
+                          "headerName": "mul48",
+                          "description": "Multiplied by 48"
+                        },
+                        "24": {
+                          "displayName": "*50",
+                          "headerName": "mul50",
+                          "description": "Multiplied by 50"
+                        },
+                        "25": {
+                          "displayName": "*52",
+                          "headerName": "mul52",
+                          "description": "Multiplied by 52"
+                        },
+                        "26": {
+                          "displayName": "*54",
+                          "headerName": "mul54",
+                          "description": "Multiplied by 54"
+                        },
+                        "27": {
+                          "displayName": "*56",
+                          "headerName": "mul56",
+                          "description": "Multiplied by 56"
+                        },
+                        "28": {
+                          "displayName": "*58",
+                          "headerName": "mul58",
+                          "description": "Multiplied by 58"
+                        },
+                        "29": {
+                          "displayName": "*60",
+                          "headerName": "mul60",
+                          "description": "Multiplied by 60"
+                        },
+                        "30": {
+                          "displayName": "*62",
+                          "headerName": "mul62",
+                          "description": "Multiplied by 62"
+                        },
+                        "31": {
+                          "displayName": "*64",
+                          "headerName": "mul64",
+                          "description": "Multiplied by 64"
+                        },
+                        "32": {
+                          "displayName": "*66",
+                          "headerName": "mul66",
+                          "description": "Multiplied by 66"
+                        },
+                        "33": {
+                          "displayName": "*68",
+                          "headerName": "mul68",
+                          "description": "Multiplied by 68"
+                        },
+                        "34": {
+                          "displayName": "*70",
+                          "headerName": "mul70",
+                          "description": "Multiplied by 70"
+                        },
+                        "35": {
+                          "displayName": "*72",
+                          "headerName": "mul72",
+                          "description": "Multiplied by 72"
+                        },
+                        "36": {
+                          "displayName": "*74",
+                          "headerName": "mul74",
+                          "description": "Multiplied by 74"
+                        },
+                        "37": {
+                          "displayName": "*76",
+                          "headerName": "mul76",
+                          "description": "Multiplied by 76"
+                        },
+                        "38": {
+                          "displayName": "*78",
+                          "headerName": "mul78",
+                          "description": "Multiplied by 78"
+                        },
+                        "39": {
+                          "displayName": "*80",
+                          "headerName": "mul80",
+                          "description": "Multiplied by 80"
+                        },
+                        "40": {
+                          "displayName": "*82",
+                          "headerName": "mul82",
+                          "description": "Multiplied by 82"
+                        },
+                        "41": {
+                          "displayName": "*84",
+                          "headerName": "mul84",
+                          "description": "Multiplied by 84"
+                        },
+                        "42": {
+                          "displayName": "*86",
+                          "headerName": "mul86",
+                          "description": "Multiplied by 86"
+                        },
+                        "43": {
+                          "displayName": "*88",
+                          "headerName": "mul88",
+                          "description": "Multiplied by 88"
+                        },
+                        "44": {
+                          "displayName": "*90",
+                          "headerName": "mul90",
+                          "description": "Multiplied by 90"
+                        },
+                        "45": {
+                          "displayName": "*92",
+                          "headerName": "mul92",
+                          "description": "Multiplied by 92"
+                        },
+                        "46": {
+                          "displayName": "*94",
+                          "headerName": "mul94",
+                          "description": "Multiplied by 94"
+                        },
+                        "47": {
+                          "displayName": "*96",
+                          "headerName": "mul96",
+                          "description": "Multiplied by 96"
+                        },
+                        "48": {
+                          "displayName": "*98",
+                          "headerName": "mul98",
+                          "description": "Multiplied by 98"
+                        },
+                        "49": {
+                          "displayName": "*100",
+                          "headerName": "mul100",
+                          "description": "Multiplied by 100"
+                        },
+                        "50": {
+                          "displayName": "*102",
+                          "headerName": "mul102",
+                          "description": "Multiplied by 102"
+                        },
+                        "51": {
+                          "displayName": "*104",
+                          "headerName": "mul104",
+                          "description": "Multiplied by 104"
+                        },
+                        "52": {
+                          "displayName": "*106",
+                          "headerName": "mul106",
+                          "description": "Multiplied by 106"
+                        },
+                        "53": {
+                          "displayName": "*108",
+                          "headerName": "mul108",
+                          "description": "Multiplied by 108"
+                        },
+                        "54": {
+                          "displayName": "*110",
+                          "headerName": "mul110",
+                          "description": "Multiplied by 110"
+                        },
+                        "55": {
+                          "displayName": "*112",
+                          "headerName": "mul112",
+                          "description": "Multiplied by 112"
+                        },
+                        "56": {
+                          "displayName": "*114",
+                          "headerName": "mul114",
+                          "description": "Multiplied by 114"
+                        },
+                        "57": {
+                          "displayName": "*116",
+                          "headerName": "mul116",
+                          "description": "Multiplied by 116"
+                        },
+                        "58": {
+                          "displayName": "*118",
+                          "headerName": "mul118",
+                          "description": "Multiplied by 118"
+                        },
+                        "59": {
+                          "displayName": "*120",
+                          "headerName": "mul120",
+                          "description": "Multiplied by 120"
+                        },
+                        "60": {
+                          "displayName": "*122",
+                          "headerName": "mul122",
+                          "description": "Multiplied by 122"
+                        },
+                        "61": {
+                          "displayName": "*124",
+                          "headerName": "mul124",
+                          "description": "Multiplied by 124"
+                        },
+                        "62": {
+                          "displayName": "*126",
+                          "headerName": "mul126",
+                          "description": "Multiplied by 126"
+                        },
+                        "63": {
+                          "displayName": "*128",
+                          "headerName": "mul128",
+                          "description": "Multiplied by 128"
+                        }
+                      }
+                    }
+                  }
+                },
+                "q": {
+                  "description": "PLL Q output divider value",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x3",
+                  "enumerations": {
+                    "pllq-enum": {
+                      "description": "Reference Clock Q Divide Ratio Enumeration",
+                      "values": {
+                        "*": {
+                          "displayName": "n/a",
+                          "description": "Not supported"
+                        },
+                        "1": {
+                          "displayName": "/2",
+                          "headerName": "div2",
+                          "description": "Divided by 2"
+                        },
+                        "2": {
+                          "displayName": "/4",
+                          "headerName": "div4",
+                          "description": "Divided by 4"
+                        },
+                        "3": {
+                          "displayName": "/8",
+                          "headerName": "div8",
+                          "description": "Divided by 8"
+                        }
+                      }
+                    }
+                  }
+                },
+                "sel": {
+                  "description": "PLL select",
+                  "bitOffset": "16",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "refsel": {
+                  "description": "PLL reference select",
+                  "bitOffset": "17",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "bypass": {
+                  "description": "PLL bypass",
+                  "bitOffset": "18",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "lock": {
+                  "description": "PLL lock indicator",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "plloutdiv": {
+              "description": "PLL Output Divider",
+              "addressOffset": "0x000C"
+            }
+          }
+        },
+        "otp": {
+          "description": "One-Time Programmable Memory (OTP) Peripheral",
+          "baseAddress": "0x10010000",
+          "size": "0x1000",
+          "registers": {
+            "lock": {
+              "description": "Programmed-I/O Lock Register",
+              "addressOffset": "0x0000"
+            },
+            "ck": {
+              "description": "Device Clock Signal Register",
+              "addressOffset": "0x0004"
+            },
+            "oe": {
+              "description": "Device Output-Enable Signal Register",
+              "addressOffset": "0x0008"
+            },
+            "sel": {
+              "description": "Device Chip-Select Signal Register",
+              "addressOffset": "0x000C"
+            },
+            "we": {
+              "description": "Device Write-Enable Signal Register",
+              "addressOffset": "0x0010"
+            },
+            "mr": {
+              "description": "Device Mode Register",
+              "addressOffset": "0x0014"
+            },
+            "mrr": {
+              "description": "Read-Voltage Regulator Control Register",
+              "addressOffset": "0x0018"
+            },
+            "mpp": {
+              "description": "Write-Voltage Charge Pump Control Register",
+              "addressOffset": "0x001C"
+            },
+            "vrren": {
+              "description": "Read-Voltage Enable Register",
+              "addressOffset": "0x0020"
+            },
+            "vppen": {
+              "description": "Write-Voltage Enable Register",
+              "addressOffset": "0x0024"
+            },
+            "a": {
+              "description": "Device Address Register",
+              "addressOffset": "0x0028"
+            },
+            "d": {
+              "description": "Device Data Input Register",
+              "addressOffset": "0x002C"
+            },
+            "q": {
+              "description": "Device Data Output Register",
+              "addressOffset": "0x0030"
+            },
+            "rsctrl": {
+              "description": "Read Sequencer Control Register",
+              "addressOffset": "0x0034",
+              "fields": {
+                "scale": {
+                  "description": "OTP timescale",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "tas": {
+                  "description": "Address setup time",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "trp": {
+                  "description": "Read pulse time",
+                  "bitOffset": "4",
+                  "bitWidth": "1"
+                },
+                "tracc": {
+                  "description": "Read access time",
+                  "bitOffset": "5",
+                  "bitWidth": "1"
+                }
+              }
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x10012000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "8"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "9"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "10"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "11"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "12"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "13"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "14"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "15"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "16"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "17"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "18"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "19"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "20"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "21"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "22"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "23"
+            },
+            "gpio16": {
+              "description": "GPIO16 Interrupt",
+              "value": "24"
+            },
+            "gpio17": {
+              "description": "GPIO17 Interrupt",
+              "value": "25"
+            },
+            "gpio18": {
+              "description": "GPIO18 Interrupt",
+              "value": "26"
+            },
+            "gpio19": {
+              "description": "GPIO19 Interrupt",
+              "value": "27"
+            },
+            "gpio20": {
+              "description": "GPIO20 Interrupt",
+              "value": "28"
+            },
+            "gpio21": {
+              "description": "GPIO21 Interrupt",
+              "value": "29"
+            },
+            "gpio22": {
+              "description": "GPIO22 Interrupt",
+              "value": "30"
+            },
+            "gpio23": {
+              "description": "GPIO23 Interrupt",
+              "value": "31"
+            },
+            "gpio24": {
+              "description": "GPIO24 Interrupt",
+              "value": "32"
+            },
+            "gpio25": {
+              "description": "GPIO25 Interrupt",
+              "value": "33"
+            },
+            "gpio26": {
+              "description": "GPIO26 Interrupt",
+              "value": "34"
+            },
+            "gpio27": {
+              "description": "GPIO27 Interrupt",
+              "value": "35"
+            },
+            "gpio28": {
+              "description": "GPIO28 Interrupt",
+              "value": "36"
+            },
+            "gpio29": {
+              "description": "GPIO29 Interrupt",
+              "value": "37"
+            },
+            "gpio30": {
+              "description": "GPIO30 Interrupt",
+              "value": "38"
+            },
+            "gpio31": {
+              "description": "GPIO31 Interrupt",
+              "value": "39"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x10013000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "3"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x10014000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x10015000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "40"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "41"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "42"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "43"
+            }
+          }
+        },
+        "uart1": {
+          "baseAddress": "0x10023000",
+          "derivedFrom": "uart0",
+          "groupName": "uart",
+          "interrupts": {
+            "uart1": {
+              "description": "UART1 Interrupt",
+              "value": "4"
+            }
+          }
+        },
+        "spi1": {
+          "baseAddress": "0x10024000",
+          "derivedFrom": "spi0",
+          "groupName": "spi",
+          "interrupts": {
+            "spi1": {
+              "description": "SPI1 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm1": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x10025000",
+          "groupName": "pwm",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm1cmp0": {
+              "description": "PWM1 Compare 0 Interrupt",
+              "value": "44"
+            },
+            "pwm1cmp1": {
+              "description": "PWM1 Compare 1 Interrupt",
+              "value": "45"
+            },
+            "pwm1cmp2": {
+              "description": "PWM1 Compare 2 Interrupt",
+              "value": "46"
+            },
+            "pwm1cmp3": {
+              "description": "PWM1 Compare 3 Interrupt",
+              "value": "47"
+            }
+          }
+        },
+        "spi2": {
+          "baseAddress": "0x10034000",
+          "derivedFrom": "spi0",
+          "groupName": "spi",
+          "interrupts": {
+            "spi2": {
+              "description": "SPI2 Interrupt",
+              "value": "7"
+            }
+          }
+        },
+        "pwm2": {
+          "baseAddress": "0x10035000",
+          "derivedFrom": "pwm1",
+          "groupName": "pwm",
+          "interrupts": {
+            "pwm2cmp0": {
+              "description": "PWM2 Compare 0 Interrupt",
+              "value": "48"
+            },
+            "pwm2cmp1": {
+              "description": "PWM2 Compare 1 Interrupt",
+              "value": "49"
+            },
+            "pwm2cmp2": {
+              "description": "PWM2 Compare 2 Interrupt",
+              "value": "50"
+            },
+            "pwm2cmp3": {
+              "description": "PWM2 Compare 3 Interrupt",
+              "value": "51"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/HiFive1/hello/fe310-xsvd.json b/FreedomStudio/HiFive1/hello/fe310-xsvd.json
new file mode 100644
index 0000000..1722e54
--- /dev/null
+++ b/FreedomStudio/HiFive1/hello/fe310-xsvd.json
@@ -0,0 +1,2325 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "fe310": {
+      "displayName": "Freedom E310-G000",
+      "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "32",
+      "resetMask": "all",
+      "resetValue": "0x00000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_FE310_",
+      "headerTypePrefix": "sifive_fe310_",
+      "headerInterruptPrefix": "sifive_fe310_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "51",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e31": {
+          "harts": "1",
+          "isa": "RV32IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            }
+          },
+          "numLocalInterrupts": "0"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            }
+          },
+          "clusters": {
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "registers": {
+                "low": {
+                  "description": "Machine Compare Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Compare Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "registers": {
+                "low": {
+                  "description": "Machine Time Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Time Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "52",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "2",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "2",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          }
+        },
+        "wdog": {
+          "description": "Watchdog Timer (WDT), part of Always-On Domain",
+          "baseAddress": "0x10000000",
+          "size": "0x0040",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "Watchdog Configuration Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "scale": {
+                  "description": "Watchdog counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "rsten": {
+                  "description": "Watchdog full reset enable",
+                  "bitOffset": "8",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "zerocmp": {
+                  "description": "Watchdog zero on comparator",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Watchdog enable counter always",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "encoreawake": {
+                  "description": "Watchdog counter only when awake",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmpip": {
+                  "description": "Watchdog interrupt pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Watchdog Count Register",
+              "addressOffset": "0x0008"
+            },
+            "scale": {
+              "description": "Watchdog Scale Register",
+              "addressOffset": "0x0010",
+              "fields": {
+                "value": {
+                  "description": "Watchdog scale value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "feed": {
+              "description": "Watchdog Feed Address Register",
+              "addressOffset": "0x0018"
+            },
+            "key": {
+              "description": "Watchdog Key Register",
+              "addressOffset": "0x001C"
+            },
+            "cmp": {
+              "description": "Watchdog Compare Register",
+              "addressOffset": "0x0020",
+              "fields": {
+                "value": {
+                  "description": "Watchdog compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "wdogcmp": {
+              "description": "Watchdog Compare Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "rtc": {
+          "description": "Real-Time Clock (RTC), part of Always-On Domain",
+          "baseAddress": "0x10000040",
+          "size": "0x0030",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "RTC Configuration Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "scale": {
+                  "description": "RTC clock rate scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "enalways": {
+                  "description": "RTC counter enable",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmpip": {
+                  "description": "RTC comparator interrupt pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "low": {
+              "description": "RTC Counter Register Low",
+              "addressOffset": "0x0008"
+            },
+            "high": {
+              "description": "RTC Counter Register High",
+              "addressOffset": "0x000C",
+              "fields": {
+                "value": {
+                  "description": "RTC counter register, high bits",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "scale": {
+              "description": "RTC Scale Register",
+              "addressOffset": "0x0010"
+            },
+            "cmp": {
+              "description": "RTC Compare Register",
+              "addressOffset": "0x0020"
+            }
+          },
+          "interrupts": {
+            "rtccmp": {
+              "description": "RTC Compare Interrupt",
+              "value": "2"
+            }
+          }
+        },
+        "pmu": {
+          "description": "Power-Management Unit (PMU), part of Always-On Domain",
+          "baseAddress": "0x10000100",
+          "size": "0x0050",
+          "resetMask": "none",
+          "registers": {
+            "wakeupi": {
+              "description": "Wakeup program instruction Registers",
+              "addressOffset": "0x0000",
+              "arraySize": "8"
+            },
+            "sleepi": {
+              "description": "Sleep Program Instruction Registers",
+              "addressOffset": "0x0020",
+              "arraySize": "8"
+            },
+            "ie": {
+              "description": "PMU Interrupt Enables Register",
+              "addressOffset": "0x0040",
+              "fields": {
+                "rtc": {
+                  "description": "RTC Comparator active",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                },
+                "dwakeup": {
+                  "description": "dwakeup_n pin active",
+                  "bitOffset": "2",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "cause": {
+              "description": "PMU Wakeup Cause Register",
+              "addressOffset": "0x0044",
+              "fields": {
+                "wakeupcause": {
+                  "description": "Wakeup cause",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "access": "r",
+                  "enumerations": {
+                    "wakeupcause-enum": {
+                      "description": "Wakeup Cause Values Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "reset",
+                          "description": "Reset Wakeup"
+                        },
+                        "1": {
+                          "displayName": "rtc",
+                          "description": "RTC Wakeup"
+                        },
+                        "2": {
+                          "displayName": "dwakeup",
+                          "description": "Digital input Wakeup"
+                        },
+                        "*": {
+                          "displayName": "undefined"
+                        }
+                      }
+                    }
+                  }
+                },
+                "resetcause": {
+                  "description": "Reset cause",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "access": "r",
+                  "enumerations": {
+                    "resetcause-enum": {
+                      "description": "Reset Cause Values Enumeration",
+                      "values": {
+                        "1": {
+                          "displayName": "external",
+                          "description": "External reset"
+                        },
+                        "2": {
+                          "displayName": "watchdog",
+                          "description": "Watchdog timer reset"
+                        },
+                        "*": {
+                          "displayName": "undefined"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "sleep": {
+              "description": "PMU Initiate Sleep Sequence Register",
+              "addressOffset": "0x0048"
+            },
+            "key": {
+              "description": "PMU Key Register",
+              "addressOffset": "0x004C"
+            }
+          }
+        },
+        "aon": {
+          "description": "Always-On (AON) Domain",
+          "baseAddress": "0x10000070",
+          "size": "0x0090",
+          "resetMask": "none",
+          "registers": {
+            "lfrosccfg": {
+              "description": "Internal Programmable Low-Frequency Ring Oscillator Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "div": {
+                  "description": "LFROSC divider",
+                  "bitOffset": "0",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x04"
+                },
+                "trim": {
+                  "description": "LFROSC trim value",
+                  "bitOffset": "16",
+                  "bitWidth": "5",
+                  "resetMask": "all",
+                  "resetValue": "0x10"
+                },
+                "en": {
+                  "description": "LFROSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "LFROSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "backup": {
+              "description": "Backup Registers",
+              "addressOffset": "0x0010",
+              "arraySize": "32"
+            }
+          }
+        },
+        "prci": {
+          "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",
+          "baseAddress": "0x10008000",
+          "size": "0x8000",
+          "registers": {
+            "hfrosccfg": {
+              "description": "Internal Trimmable Programmable 72 MHz Oscillator Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "div": {
+                  "description": "HFROSC divider",
+                  "bitOffset": "0",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x04"
+                },
+                "trim": {
+                  "description": "HFROSC trim value",
+                  "bitOffset": "16",
+                  "bitWidth": "5",
+                  "resetMask": "all",
+                  "resetValue": "0x10"
+                },
+                "en": {
+                  "description": "HFROSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "HFROSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "hfxosccfg": {
+              "description": "External 16 MHz Crystal Oscillator Register",
+              "addressOffset": "0x0004",
+              "fields": {
+                "en": {
+                  "description": "HFXOSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "HFXOSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "pllcfg": {
+              "description": "Internal High-Frequency PLL (HFPLL) Register",
+              "addressOffset": "0x0008",
+              "fields": {
+                "r": {
+                  "description": "PLL R input divider value",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "pllr-enum": {
+                      "description": "Reference Clock R Divide Ratio Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "/1",
+                          "headerName": "div1",
+                          "description": "Unchanged"
+                        },
+                        "1": {
+                          "displayName": "/2",
+                          "headerName": "div2",
+                          "description": "Divided by 2"
+                        },
+                        "2": {
+                          "displayName": "/3",
+                          "headerName": "div3",
+                          "description": "Divided by 3"
+                        },
+                        "3": {
+                          "displayName": "/4",
+                          "headerName": "div4",
+                          "description": "Divided by 4"
+                        }
+                      }
+                    }
+                  }
+                },
+                "f": {
+                  "description": "PLL F multiplier value",
+                  "bitOffset": "4",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x1F",
+                  "enumerations": {
+                    "pllf-enum": {
+                      "description": "Reference Clock F Multiplier Ratio Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "*2",
+                          "headerName": "mul2",
+                          "description": "Multiplied by 2"
+                        },
+                        "1": {
+                          "displayName": "*4",
+                          "headerName": "mul4",
+                          "description": "Multiplied by 4"
+                        },
+                        "2": {
+                          "displayName": "*6",
+                          "headerName": "mul6",
+                          "description": "Multiplied by 6"
+                        },
+                        "3": {
+                          "displayName": "*8",
+                          "headerName": "mul8",
+                          "description": "Multiplied by 8"
+                        },
+                        "4": {
+                          "displayName": "*10",
+                          "headerName": "mul10",
+                          "description": "Multiplied by 10"
+                        },
+                        "5": {
+                          "displayName": "*12",
+                          "headerName": "mul12",
+                          "description": "Multiplied by 12"
+                        },
+                        "6": {
+                          "displayName": "*14",
+                          "headerName": "mul14",
+                          "description": "Multiplied by 14"
+                        },
+                        "7": {
+                          "displayName": "*16",
+                          "headerName": "mul16",
+                          "description": "Multiplied by 16"
+                        },
+                        "8": {
+                          "displayName": "*18",
+                          "headerName": "mul18",
+                          "description": "Multiplied by 18"
+                        },
+                        "9": {
+                          "displayName": "*20",
+                          "headerName": "mul20",
+                          "description": "Multiplied by 20"
+                        },
+                        "10": {
+                          "displayName": "*22",
+                          "headerName": "mul22",
+                          "description": "Multiplied by 22"
+                        },
+                        "11": {
+                          "displayName": "*24",
+                          "headerName": "mul24",
+                          "description": "Multiplied by 24"
+                        },
+                        "12": {
+                          "displayName": "*26",
+                          "headerName": "mul26",
+                          "description": "Multiplied by 26"
+                        },
+                        "13": {
+                          "displayName": "*28",
+                          "headerName": "mul28",
+                          "description": "Multiplied by 28"
+                        },
+                        "14": {
+                          "displayName": "*30",
+                          "headerName": "mul30",
+                          "description": "Multiplied by 30"
+                        },
+                        "15": {
+                          "displayName": "*32",
+                          "headerName": "mul32",
+                          "description": "Multiplied by 32"
+                        },
+                        "16": {
+                          "displayName": "*34",
+                          "headerName": "mul34",
+                          "description": "Multiplied by 34"
+                        },
+                        "17": {
+                          "displayName": "*36",
+                          "headerName": "mul36",
+                          "description": "Multiplied by 36"
+                        },
+                        "18": {
+                          "displayName": "*38",
+                          "headerName": "mul38",
+                          "description": "Multiplied by 38"
+                        },
+                        "19": {
+                          "displayName": "*40",
+                          "headerName": "mul40",
+                          "description": "Multiplied by 40"
+                        },
+                        "20": {
+                          "displayName": "*42",
+                          "headerName": "mul42",
+                          "description": "Multiplied by 42"
+                        },
+                        "21": {
+                          "displayName": "*44",
+                          "headerName": "mul44",
+                          "description": "Multiplied by 44"
+                        },
+                        "22": {
+                          "displayName": "*46",
+                          "headerName": "mul46",
+                          "description": "Multiplied by 46"
+                        },
+                        "23": {
+                          "displayName": "*48",
+                          "headerName": "mul48",
+                          "description": "Multiplied by 48"
+                        },
+                        "24": {
+                          "displayName": "*50",
+                          "headerName": "mul50",
+                          "description": "Multiplied by 50"
+                        },
+                        "25": {
+                          "displayName": "*52",
+                          "headerName": "mul52",
+                          "description": "Multiplied by 52"
+                        },
+                        "26": {
+                          "displayName": "*54",
+                          "headerName": "mul54",
+                          "description": "Multiplied by 54"
+                        },
+                        "27": {
+                          "displayName": "*56",
+                          "headerName": "mul56",
+                          "description": "Multiplied by 56"
+                        },
+                        "28": {
+                          "displayName": "*58",
+                          "headerName": "mul58",
+                          "description": "Multiplied by 58"
+                        },
+                        "29": {
+                          "displayName": "*60",
+                          "headerName": "mul60",
+                          "description": "Multiplied by 60"
+                        },
+                        "30": {
+                          "displayName": "*62",
+                          "headerName": "mul62",
+                          "description": "Multiplied by 62"
+                        },
+                        "31": {
+                          "displayName": "*64",
+                          "headerName": "mul64",
+                          "description": "Multiplied by 64"
+                        },
+                        "32": {
+                          "displayName": "*66",
+                          "headerName": "mul66",
+                          "description": "Multiplied by 66"
+                        },
+                        "33": {
+                          "displayName": "*68",
+                          "headerName": "mul68",
+                          "description": "Multiplied by 68"
+                        },
+                        "34": {
+                          "displayName": "*70",
+                          "headerName": "mul70",
+                          "description": "Multiplied by 70"
+                        },
+                        "35": {
+                          "displayName": "*72",
+                          "headerName": "mul72",
+                          "description": "Multiplied by 72"
+                        },
+                        "36": {
+                          "displayName": "*74",
+                          "headerName": "mul74",
+                          "description": "Multiplied by 74"
+                        },
+                        "37": {
+                          "displayName": "*76",
+                          "headerName": "mul76",
+                          "description": "Multiplied by 76"
+                        },
+                        "38": {
+                          "displayName": "*78",
+                          "headerName": "mul78",
+                          "description": "Multiplied by 78"
+                        },
+                        "39": {
+                          "displayName": "*80",
+                          "headerName": "mul80",
+                          "description": "Multiplied by 80"
+                        },
+                        "40": {
+                          "displayName": "*82",
+                          "headerName": "mul82",
+                          "description": "Multiplied by 82"
+                        },
+                        "41": {
+                          "displayName": "*84",
+                          "headerName": "mul84",
+                          "description": "Multiplied by 84"
+                        },
+                        "42": {
+                          "displayName": "*86",
+                          "headerName": "mul86",
+                          "description": "Multiplied by 86"
+                        },
+                        "43": {
+                          "displayName": "*88",
+                          "headerName": "mul88",
+                          "description": "Multiplied by 88"
+                        },
+                        "44": {
+                          "displayName": "*90",
+                          "headerName": "mul90",
+                          "description": "Multiplied by 90"
+                        },
+                        "45": {
+                          "displayName": "*92",
+                          "headerName": "mul92",
+                          "description": "Multiplied by 92"
+                        },
+                        "46": {
+                          "displayName": "*94",
+                          "headerName": "mul94",
+                          "description": "Multiplied by 94"
+                        },
+                        "47": {
+                          "displayName": "*96",
+                          "headerName": "mul96",
+                          "description": "Multiplied by 96"
+                        },
+                        "48": {
+                          "displayName": "*98",
+                          "headerName": "mul98",
+                          "description": "Multiplied by 98"
+                        },
+                        "49": {
+                          "displayName": "*100",
+                          "headerName": "mul100",
+                          "description": "Multiplied by 100"
+                        },
+                        "50": {
+                          "displayName": "*102",
+                          "headerName": "mul102",
+                          "description": "Multiplied by 102"
+                        },
+                        "51": {
+                          "displayName": "*104",
+                          "headerName": "mul104",
+                          "description": "Multiplied by 104"
+                        },
+                        "52": {
+                          "displayName": "*106",
+                          "headerName": "mul106",
+                          "description": "Multiplied by 106"
+                        },
+                        "53": {
+                          "displayName": "*108",
+                          "headerName": "mul108",
+                          "description": "Multiplied by 108"
+                        },
+                        "54": {
+                          "displayName": "*110",
+                          "headerName": "mul110",
+                          "description": "Multiplied by 110"
+                        },
+                        "55": {
+                          "displayName": "*112",
+                          "headerName": "mul112",
+                          "description": "Multiplied by 112"
+                        },
+                        "56": {
+                          "displayName": "*114",
+                          "headerName": "mul114",
+                          "description": "Multiplied by 114"
+                        },
+                        "57": {
+                          "displayName": "*116",
+                          "headerName": "mul116",
+                          "description": "Multiplied by 116"
+                        },
+                        "58": {
+                          "displayName": "*118",
+                          "headerName": "mul118",
+                          "description": "Multiplied by 118"
+                        },
+                        "59": {
+                          "displayName": "*120",
+                          "headerName": "mul120",
+                          "description": "Multiplied by 120"
+                        },
+                        "60": {
+                          "displayName": "*122",
+                          "headerName": "mul122",
+                          "description": "Multiplied by 122"
+                        },
+                        "61": {
+                          "displayName": "*124",
+                          "headerName": "mul124",
+                          "description": "Multiplied by 124"
+                        },
+                        "62": {
+                          "displayName": "*126",
+                          "headerName": "mul126",
+                          "description": "Multiplied by 126"
+                        },
+                        "63": {
+                          "displayName": "*128",
+                          "headerName": "mul128",
+                          "description": "Multiplied by 128"
+                        }
+                      }
+                    }
+                  }
+                },
+                "q": {
+                  "description": "PLL Q output divider value",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x3",
+                  "enumerations": {
+                    "pllq-enum": {
+                      "description": "Reference Clock Q Divide Ratio Enumeration",
+                      "values": {
+                        "*": {
+                          "displayName": "n/a",
+                          "description": "Not supported"
+                        },
+                        "1": {
+                          "displayName": "/2",
+                          "headerName": "div2",
+                          "description": "Divided by 2"
+                        },
+                        "2": {
+                          "displayName": "/4",
+                          "headerName": "div4",
+                          "description": "Divided by 4"
+                        },
+                        "3": {
+                          "displayName": "/8",
+                          "headerName": "div8",
+                          "description": "Divided by 8"
+                        }
+                      }
+                    }
+                  }
+                },
+                "sel": {
+                  "description": "PLL select",
+                  "bitOffset": "16",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "refsel": {
+                  "description": "PLL reference select",
+                  "bitOffset": "17",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "bypass": {
+                  "description": "PLL bypass",
+                  "bitOffset": "18",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "lock": {
+                  "description": "PLL lock indicator",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "plloutdiv": {
+              "description": "PLL Output Divider",
+              "addressOffset": "0x000C"
+            }
+          }
+        },
+        "otp": {
+          "description": "One-Time Programmable Memory (OTP) Peripheral",
+          "baseAddress": "0x10010000",
+          "size": "0x1000",
+          "registers": {
+            "lock": {
+              "description": "Programmed-I/O Lock Register",
+              "addressOffset": "0x0000"
+            },
+            "ck": {
+              "description": "Device Clock Signal Register",
+              "addressOffset": "0x0004"
+            },
+            "oe": {
+              "description": "Device Output-Enable Signal Register",
+              "addressOffset": "0x0008"
+            },
+            "sel": {
+              "description": "Device Chip-Select Signal Register",
+              "addressOffset": "0x000C"
+            },
+            "we": {
+              "description": "Device Write-Enable Signal Register",
+              "addressOffset": "0x0010"
+            },
+            "mr": {
+              "description": "Device Mode Register",
+              "addressOffset": "0x0014"
+            },
+            "mrr": {
+              "description": "Read-Voltage Regulator Control Register",
+              "addressOffset": "0x0018"
+            },
+            "mpp": {
+              "description": "Write-Voltage Charge Pump Control Register",
+              "addressOffset": "0x001C"
+            },
+            "vrren": {
+              "description": "Read-Voltage Enable Register",
+              "addressOffset": "0x0020"
+            },
+            "vppen": {
+              "description": "Write-Voltage Enable Register",
+              "addressOffset": "0x0024"
+            },
+            "a": {
+              "description": "Device Address Register",
+              "addressOffset": "0x0028"
+            },
+            "d": {
+              "description": "Device Data Input Register",
+              "addressOffset": "0x002C"
+            },
+            "q": {
+              "description": "Device Data Output Register",
+              "addressOffset": "0x0030"
+            },
+            "rsctrl": {
+              "description": "Read Sequencer Control Register",
+              "addressOffset": "0x0034",
+              "fields": {
+                "scale": {
+                  "description": "OTP timescale",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "tas": {
+                  "description": "Address setup time",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "trp": {
+                  "description": "Read pulse time",
+                  "bitOffset": "4",
+                  "bitWidth": "1"
+                },
+                "tracc": {
+                  "description": "Read access time",
+                  "bitOffset": "5",
+                  "bitWidth": "1"
+                }
+              }
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x10012000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "8"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "9"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "10"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "11"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "12"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "13"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "14"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "15"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "16"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "17"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "18"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "19"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "20"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "21"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "22"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "23"
+            },
+            "gpio16": {
+              "description": "GPIO16 Interrupt",
+              "value": "24"
+            },
+            "gpio17": {
+              "description": "GPIO17 Interrupt",
+              "value": "25"
+            },
+            "gpio18": {
+              "description": "GPIO18 Interrupt",
+              "value": "26"
+            },
+            "gpio19": {
+              "description": "GPIO19 Interrupt",
+              "value": "27"
+            },
+            "gpio20": {
+              "description": "GPIO20 Interrupt",
+              "value": "28"
+            },
+            "gpio21": {
+              "description": "GPIO21 Interrupt",
+              "value": "29"
+            },
+            "gpio22": {
+              "description": "GPIO22 Interrupt",
+              "value": "30"
+            },
+            "gpio23": {
+              "description": "GPIO23 Interrupt",
+              "value": "31"
+            },
+            "gpio24": {
+              "description": "GPIO24 Interrupt",
+              "value": "32"
+            },
+            "gpio25": {
+              "description": "GPIO25 Interrupt",
+              "value": "33"
+            },
+            "gpio26": {
+              "description": "GPIO26 Interrupt",
+              "value": "34"
+            },
+            "gpio27": {
+              "description": "GPIO27 Interrupt",
+              "value": "35"
+            },
+            "gpio28": {
+              "description": "GPIO28 Interrupt",
+              "value": "36"
+            },
+            "gpio29": {
+              "description": "GPIO29 Interrupt",
+              "value": "37"
+            },
+            "gpio30": {
+              "description": "GPIO30 Interrupt",
+              "value": "38"
+            },
+            "gpio31": {
+              "description": "GPIO31 Interrupt",
+              "value": "39"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x10013000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "3"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x10014000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x10015000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "40"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "41"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "42"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "43"
+            }
+          }
+        },
+        "uart1": {
+          "baseAddress": "0x10023000",
+          "derivedFrom": "uart0",
+          "groupName": "uart",
+          "interrupts": {
+            "uart1": {
+              "description": "UART1 Interrupt",
+              "value": "4"
+            }
+          }
+        },
+        "spi1": {
+          "baseAddress": "0x10024000",
+          "derivedFrom": "spi0",
+          "groupName": "spi",
+          "interrupts": {
+            "spi1": {
+              "description": "SPI1 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm1": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x10025000",
+          "groupName": "pwm",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm1cmp0": {
+              "description": "PWM1 Compare 0 Interrupt",
+              "value": "44"
+            },
+            "pwm1cmp1": {
+              "description": "PWM1 Compare 1 Interrupt",
+              "value": "45"
+            },
+            "pwm1cmp2": {
+              "description": "PWM1 Compare 2 Interrupt",
+              "value": "46"
+            },
+            "pwm1cmp3": {
+              "description": "PWM1 Compare 3 Interrupt",
+              "value": "47"
+            }
+          }
+        },
+        "spi2": {
+          "baseAddress": "0x10034000",
+          "derivedFrom": "spi0",
+          "groupName": "spi",
+          "interrupts": {
+            "spi2": {
+              "description": "SPI2 Interrupt",
+              "value": "7"
+            }
+          }
+        },
+        "pwm2": {
+          "baseAddress": "0x10035000",
+          "derivedFrom": "pwm1",
+          "groupName": "pwm",
+          "interrupts": {
+            "pwm2cmp0": {
+              "description": "PWM2 Compare 0 Interrupt",
+              "value": "48"
+            },
+            "pwm2cmp1": {
+              "description": "PWM2 Compare 1 Interrupt",
+              "value": "49"
+            },
+            "pwm2cmp2": {
+              "description": "PWM2 Compare 2 Interrupt",
+              "value": "50"
+            },
+            "pwm2cmp3": {
+              "description": "PWM2 Compare 3 Interrupt",
+              "value": "51"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/HiFive1/hello/hello Debug.launch b/FreedomStudio/HiFive1/hello/hello OpenOCD.launch
index 6b567b6..55bd731 100644
--- a/FreedomStudio/HiFive1/hello/hello Debug.launch
+++ b/FreedomStudio/HiFive1/hello/hello OpenOCD.launch
@@ -20,6 +20,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/fe310-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/HiFive1/led_fade/fe310-xsvd.json b/FreedomStudio/HiFive1/led_fade/fe310-xsvd.json
new file mode 100644
index 0000000..1722e54
--- /dev/null
+++ b/FreedomStudio/HiFive1/led_fade/fe310-xsvd.json
@@ -0,0 +1,2325 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "fe310": {
+      "displayName": "Freedom E310-G000",
+      "description": "The FE310-G000 is the first Freedom E300 SoC, and is the industry's first commercially available RISC-V SoC. The FE310-G000 is built around the E31 Core Complex instantiated in the Freedom E300 platform.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "32",
+      "resetMask": "all",
+      "resetValue": "0x00000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_FE310_",
+      "headerTypePrefix": "sifive_fe310_",
+      "headerInterruptPrefix": "sifive_fe310_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "51",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e31": {
+          "harts": "1",
+          "isa": "RV32IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            }
+          },
+          "numLocalInterrupts": "0"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            }
+          },
+          "clusters": {
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "registers": {
+                "low": {
+                  "description": "Machine Compare Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Compare Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "registers": {
+                "low": {
+                  "description": "Machine Time Register Low",
+                  "addressOffset": "0x0000"
+                },
+                "high": {
+                  "description": "Machine Time Register High",
+                  "addressOffset": "0x0004"
+                }
+              }
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "52",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "2",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "2",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          }
+        },
+        "wdog": {
+          "description": "Watchdog Timer (WDT), part of Always-On Domain",
+          "baseAddress": "0x10000000",
+          "size": "0x0040",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "Watchdog Configuration Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "scale": {
+                  "description": "Watchdog counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "rsten": {
+                  "description": "Watchdog full reset enable",
+                  "bitOffset": "8",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "zerocmp": {
+                  "description": "Watchdog zero on comparator",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Watchdog enable counter always",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "encoreawake": {
+                  "description": "Watchdog counter only when awake",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmpip": {
+                  "description": "Watchdog interrupt pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Watchdog Count Register",
+              "addressOffset": "0x0008"
+            },
+            "scale": {
+              "description": "Watchdog Scale Register",
+              "addressOffset": "0x0010",
+              "fields": {
+                "value": {
+                  "description": "Watchdog scale value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "feed": {
+              "description": "Watchdog Feed Address Register",
+              "addressOffset": "0x0018"
+            },
+            "key": {
+              "description": "Watchdog Key Register",
+              "addressOffset": "0x001C"
+            },
+            "cmp": {
+              "description": "Watchdog Compare Register",
+              "addressOffset": "0x0020",
+              "fields": {
+                "value": {
+                  "description": "Watchdog compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "wdogcmp": {
+              "description": "Watchdog Compare Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "rtc": {
+          "description": "Real-Time Clock (RTC), part of Always-On Domain",
+          "baseAddress": "0x10000040",
+          "size": "0x0030",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "RTC Configuration Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "scale": {
+                  "description": "RTC clock rate scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "enalways": {
+                  "description": "RTC counter enable",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmpip": {
+                  "description": "RTC comparator interrupt pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "low": {
+              "description": "RTC Counter Register Low",
+              "addressOffset": "0x0008"
+            },
+            "high": {
+              "description": "RTC Counter Register High",
+              "addressOffset": "0x000C",
+              "fields": {
+                "value": {
+                  "description": "RTC counter register, high bits",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "scale": {
+              "description": "RTC Scale Register",
+              "addressOffset": "0x0010"
+            },
+            "cmp": {
+              "description": "RTC Compare Register",
+              "addressOffset": "0x0020"
+            }
+          },
+          "interrupts": {
+            "rtccmp": {
+              "description": "RTC Compare Interrupt",
+              "value": "2"
+            }
+          }
+        },
+        "pmu": {
+          "description": "Power-Management Unit (PMU), part of Always-On Domain",
+          "baseAddress": "0x10000100",
+          "size": "0x0050",
+          "resetMask": "none",
+          "registers": {
+            "wakeupi": {
+              "description": "Wakeup program instruction Registers",
+              "addressOffset": "0x0000",
+              "arraySize": "8"
+            },
+            "sleepi": {
+              "description": "Sleep Program Instruction Registers",
+              "addressOffset": "0x0020",
+              "arraySize": "8"
+            },
+            "ie": {
+              "description": "PMU Interrupt Enables Register",
+              "addressOffset": "0x0040",
+              "fields": {
+                "rtc": {
+                  "description": "RTC Comparator active",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                },
+                "dwakeup": {
+                  "description": "dwakeup_n pin active",
+                  "bitOffset": "2",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "cause": {
+              "description": "PMU Wakeup Cause Register",
+              "addressOffset": "0x0044",
+              "fields": {
+                "wakeupcause": {
+                  "description": "Wakeup cause",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "access": "r",
+                  "enumerations": {
+                    "wakeupcause-enum": {
+                      "description": "Wakeup Cause Values Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "reset",
+                          "description": "Reset Wakeup"
+                        },
+                        "1": {
+                          "displayName": "rtc",
+                          "description": "RTC Wakeup"
+                        },
+                        "2": {
+                          "displayName": "dwakeup",
+                          "description": "Digital input Wakeup"
+                        },
+                        "*": {
+                          "displayName": "undefined"
+                        }
+                      }
+                    }
+                  }
+                },
+                "resetcause": {
+                  "description": "Reset cause",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "access": "r",
+                  "enumerations": {
+                    "resetcause-enum": {
+                      "description": "Reset Cause Values Enumeration",
+                      "values": {
+                        "1": {
+                          "displayName": "external",
+                          "description": "External reset"
+                        },
+                        "2": {
+                          "displayName": "watchdog",
+                          "description": "Watchdog timer reset"
+                        },
+                        "*": {
+                          "displayName": "undefined"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "sleep": {
+              "description": "PMU Initiate Sleep Sequence Register",
+              "addressOffset": "0x0048"
+            },
+            "key": {
+              "description": "PMU Key Register",
+              "addressOffset": "0x004C"
+            }
+          }
+        },
+        "aon": {
+          "description": "Always-On (AON) Domain",
+          "baseAddress": "0x10000070",
+          "size": "0x0090",
+          "resetMask": "none",
+          "registers": {
+            "lfrosccfg": {
+              "description": "Internal Programmable Low-Frequency Ring Oscillator Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "div": {
+                  "description": "LFROSC divider",
+                  "bitOffset": "0",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x04"
+                },
+                "trim": {
+                  "description": "LFROSC trim value",
+                  "bitOffset": "16",
+                  "bitWidth": "5",
+                  "resetMask": "all",
+                  "resetValue": "0x10"
+                },
+                "en": {
+                  "description": "LFROSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "LFROSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "backup": {
+              "description": "Backup Registers",
+              "addressOffset": "0x0010",
+              "arraySize": "32"
+            }
+          }
+        },
+        "prci": {
+          "description": "Power, Reset, Clock, Interrupt (PRCI) Peripheral",
+          "baseAddress": "0x10008000",
+          "size": "0x8000",
+          "registers": {
+            "hfrosccfg": {
+              "description": "Internal Trimmable Programmable 72 MHz Oscillator Register",
+              "addressOffset": "0x0000",
+              "fields": {
+                "div": {
+                  "description": "HFROSC divider",
+                  "bitOffset": "0",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x04"
+                },
+                "trim": {
+                  "description": "HFROSC trim value",
+                  "bitOffset": "16",
+                  "bitWidth": "5",
+                  "resetMask": "all",
+                  "resetValue": "0x10"
+                },
+                "en": {
+                  "description": "HFROSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "HFROSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "hfxosccfg": {
+              "description": "External 16 MHz Crystal Oscillator Register",
+              "addressOffset": "0x0004",
+              "fields": {
+                "en": {
+                  "description": "HFXOSC enable",
+                  "bitOffset": "30",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "rdy": {
+                  "description": "HFXOSC ready",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "pllcfg": {
+              "description": "Internal High-Frequency PLL (HFPLL) Register",
+              "addressOffset": "0x0008",
+              "fields": {
+                "r": {
+                  "description": "PLL R input divider value",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "pllr-enum": {
+                      "description": "Reference Clock R Divide Ratio Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "/1",
+                          "headerName": "div1",
+                          "description": "Unchanged"
+                        },
+                        "1": {
+                          "displayName": "/2",
+                          "headerName": "div2",
+                          "description": "Divided by 2"
+                        },
+                        "2": {
+                          "displayName": "/3",
+                          "headerName": "div3",
+                          "description": "Divided by 3"
+                        },
+                        "3": {
+                          "displayName": "/4",
+                          "headerName": "div4",
+                          "description": "Divided by 4"
+                        }
+                      }
+                    }
+                  }
+                },
+                "f": {
+                  "description": "PLL F multiplier value",
+                  "bitOffset": "4",
+                  "bitWidth": "6",
+                  "resetMask": "all",
+                  "resetValue": "0x1F",
+                  "enumerations": {
+                    "pllf-enum": {
+                      "description": "Reference Clock F Multiplier Ratio Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "*2",
+                          "headerName": "mul2",
+                          "description": "Multiplied by 2"
+                        },
+                        "1": {
+                          "displayName": "*4",
+                          "headerName": "mul4",
+                          "description": "Multiplied by 4"
+                        },
+                        "2": {
+                          "displayName": "*6",
+                          "headerName": "mul6",
+                          "description": "Multiplied by 6"
+                        },
+                        "3": {
+                          "displayName": "*8",
+                          "headerName": "mul8",
+                          "description": "Multiplied by 8"
+                        },
+                        "4": {
+                          "displayName": "*10",
+                          "headerName": "mul10",
+                          "description": "Multiplied by 10"
+                        },
+                        "5": {
+                          "displayName": "*12",
+                          "headerName": "mul12",
+                          "description": "Multiplied by 12"
+                        },
+                        "6": {
+                          "displayName": "*14",
+                          "headerName": "mul14",
+                          "description": "Multiplied by 14"
+                        },
+                        "7": {
+                          "displayName": "*16",
+                          "headerName": "mul16",
+                          "description": "Multiplied by 16"
+                        },
+                        "8": {
+                          "displayName": "*18",
+                          "headerName": "mul18",
+                          "description": "Multiplied by 18"
+                        },
+                        "9": {
+                          "displayName": "*20",
+                          "headerName": "mul20",
+                          "description": "Multiplied by 20"
+                        },
+                        "10": {
+                          "displayName": "*22",
+                          "headerName": "mul22",
+                          "description": "Multiplied by 22"
+                        },
+                        "11": {
+                          "displayName": "*24",
+                          "headerName": "mul24",
+                          "description": "Multiplied by 24"
+                        },
+                        "12": {
+                          "displayName": "*26",
+                          "headerName": "mul26",
+                          "description": "Multiplied by 26"
+                        },
+                        "13": {
+                          "displayName": "*28",
+                          "headerName": "mul28",
+                          "description": "Multiplied by 28"
+                        },
+                        "14": {
+                          "displayName": "*30",
+                          "headerName": "mul30",
+                          "description": "Multiplied by 30"
+                        },
+                        "15": {
+                          "displayName": "*32",
+                          "headerName": "mul32",
+                          "description": "Multiplied by 32"
+                        },
+                        "16": {
+                          "displayName": "*34",
+                          "headerName": "mul34",
+                          "description": "Multiplied by 34"
+                        },
+                        "17": {
+                          "displayName": "*36",
+                          "headerName": "mul36",
+                          "description": "Multiplied by 36"
+                        },
+                        "18": {
+                          "displayName": "*38",
+                          "headerName": "mul38",
+                          "description": "Multiplied by 38"
+                        },
+                        "19": {
+                          "displayName": "*40",
+                          "headerName": "mul40",
+                          "description": "Multiplied by 40"
+                        },
+                        "20": {
+                          "displayName": "*42",
+                          "headerName": "mul42",
+                          "description": "Multiplied by 42"
+                        },
+                        "21": {
+                          "displayName": "*44",
+                          "headerName": "mul44",
+                          "description": "Multiplied by 44"
+                        },
+                        "22": {
+                          "displayName": "*46",
+                          "headerName": "mul46",
+                          "description": "Multiplied by 46"
+                        },
+                        "23": {
+                          "displayName": "*48",
+                          "headerName": "mul48",
+                          "description": "Multiplied by 48"
+                        },
+                        "24": {
+                          "displayName": "*50",
+                          "headerName": "mul50",
+                          "description": "Multiplied by 50"
+                        },
+                        "25": {
+                          "displayName": "*52",
+                          "headerName": "mul52",
+                          "description": "Multiplied by 52"
+                        },
+                        "26": {
+                          "displayName": "*54",
+                          "headerName": "mul54",
+                          "description": "Multiplied by 54"
+                        },
+                        "27": {
+                          "displayName": "*56",
+                          "headerName": "mul56",
+                          "description": "Multiplied by 56"
+                        },
+                        "28": {
+                          "displayName": "*58",
+                          "headerName": "mul58",
+                          "description": "Multiplied by 58"
+                        },
+                        "29": {
+                          "displayName": "*60",
+                          "headerName": "mul60",
+                          "description": "Multiplied by 60"
+                        },
+                        "30": {
+                          "displayName": "*62",
+                          "headerName": "mul62",
+                          "description": "Multiplied by 62"
+                        },
+                        "31": {
+                          "displayName": "*64",
+                          "headerName": "mul64",
+                          "description": "Multiplied by 64"
+                        },
+                        "32": {
+                          "displayName": "*66",
+                          "headerName": "mul66",
+                          "description": "Multiplied by 66"
+                        },
+                        "33": {
+                          "displayName": "*68",
+                          "headerName": "mul68",
+                          "description": "Multiplied by 68"
+                        },
+                        "34": {
+                          "displayName": "*70",
+                          "headerName": "mul70",
+                          "description": "Multiplied by 70"
+                        },
+                        "35": {
+                          "displayName": "*72",
+                          "headerName": "mul72",
+                          "description": "Multiplied by 72"
+                        },
+                        "36": {
+                          "displayName": "*74",
+                          "headerName": "mul74",
+                          "description": "Multiplied by 74"
+                        },
+                        "37": {
+                          "displayName": "*76",
+                          "headerName": "mul76",
+                          "description": "Multiplied by 76"
+                        },
+                        "38": {
+                          "displayName": "*78",
+                          "headerName": "mul78",
+                          "description": "Multiplied by 78"
+                        },
+                        "39": {
+                          "displayName": "*80",
+                          "headerName": "mul80",
+                          "description": "Multiplied by 80"
+                        },
+                        "40": {
+                          "displayName": "*82",
+                          "headerName": "mul82",
+                          "description": "Multiplied by 82"
+                        },
+                        "41": {
+                          "displayName": "*84",
+                          "headerName": "mul84",
+                          "description": "Multiplied by 84"
+                        },
+                        "42": {
+                          "displayName": "*86",
+                          "headerName": "mul86",
+                          "description": "Multiplied by 86"
+                        },
+                        "43": {
+                          "displayName": "*88",
+                          "headerName": "mul88",
+                          "description": "Multiplied by 88"
+                        },
+                        "44": {
+                          "displayName": "*90",
+                          "headerName": "mul90",
+                          "description": "Multiplied by 90"
+                        },
+                        "45": {
+                          "displayName": "*92",
+                          "headerName": "mul92",
+                          "description": "Multiplied by 92"
+                        },
+                        "46": {
+                          "displayName": "*94",
+                          "headerName": "mul94",
+                          "description": "Multiplied by 94"
+                        },
+                        "47": {
+                          "displayName": "*96",
+                          "headerName": "mul96",
+                          "description": "Multiplied by 96"
+                        },
+                        "48": {
+                          "displayName": "*98",
+                          "headerName": "mul98",
+                          "description": "Multiplied by 98"
+                        },
+                        "49": {
+                          "displayName": "*100",
+                          "headerName": "mul100",
+                          "description": "Multiplied by 100"
+                        },
+                        "50": {
+                          "displayName": "*102",
+                          "headerName": "mul102",
+                          "description": "Multiplied by 102"
+                        },
+                        "51": {
+                          "displayName": "*104",
+                          "headerName": "mul104",
+                          "description": "Multiplied by 104"
+                        },
+                        "52": {
+                          "displayName": "*106",
+                          "headerName": "mul106",
+                          "description": "Multiplied by 106"
+                        },
+                        "53": {
+                          "displayName": "*108",
+                          "headerName": "mul108",
+                          "description": "Multiplied by 108"
+                        },
+                        "54": {
+                          "displayName": "*110",
+                          "headerName": "mul110",
+                          "description": "Multiplied by 110"
+                        },
+                        "55": {
+                          "displayName": "*112",
+                          "headerName": "mul112",
+                          "description": "Multiplied by 112"
+                        },
+                        "56": {
+                          "displayName": "*114",
+                          "headerName": "mul114",
+                          "description": "Multiplied by 114"
+                        },
+                        "57": {
+                          "displayName": "*116",
+                          "headerName": "mul116",
+                          "description": "Multiplied by 116"
+                        },
+                        "58": {
+                          "displayName": "*118",
+                          "headerName": "mul118",
+                          "description": "Multiplied by 118"
+                        },
+                        "59": {
+                          "displayName": "*120",
+                          "headerName": "mul120",
+                          "description": "Multiplied by 120"
+                        },
+                        "60": {
+                          "displayName": "*122",
+                          "headerName": "mul122",
+                          "description": "Multiplied by 122"
+                        },
+                        "61": {
+                          "displayName": "*124",
+                          "headerName": "mul124",
+                          "description": "Multiplied by 124"
+                        },
+                        "62": {
+                          "displayName": "*126",
+                          "headerName": "mul126",
+                          "description": "Multiplied by 126"
+                        },
+                        "63": {
+                          "displayName": "*128",
+                          "headerName": "mul128",
+                          "description": "Multiplied by 128"
+                        }
+                      }
+                    }
+                  }
+                },
+                "q": {
+                  "description": "PLL Q output divider value",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x3",
+                  "enumerations": {
+                    "pllq-enum": {
+                      "description": "Reference Clock Q Divide Ratio Enumeration",
+                      "values": {
+                        "*": {
+                          "displayName": "n/a",
+                          "description": "Not supported"
+                        },
+                        "1": {
+                          "displayName": "/2",
+                          "headerName": "div2",
+                          "description": "Divided by 2"
+                        },
+                        "2": {
+                          "displayName": "/4",
+                          "headerName": "div4",
+                          "description": "Divided by 4"
+                        },
+                        "3": {
+                          "displayName": "/8",
+                          "headerName": "div8",
+                          "description": "Divided by 8"
+                        }
+                      }
+                    }
+                  }
+                },
+                "sel": {
+                  "description": "PLL select",
+                  "bitOffset": "16",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "refsel": {
+                  "description": "PLL reference select",
+                  "bitOffset": "17",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "bypass": {
+                  "description": "PLL bypass",
+                  "bitOffset": "18",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "lock": {
+                  "description": "PLL lock indicator",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "plloutdiv": {
+              "description": "PLL Output Divider",
+              "addressOffset": "0x000C"
+            }
+          }
+        },
+        "otp": {
+          "description": "One-Time Programmable Memory (OTP) Peripheral",
+          "baseAddress": "0x10010000",
+          "size": "0x1000",
+          "registers": {
+            "lock": {
+              "description": "Programmed-I/O Lock Register",
+              "addressOffset": "0x0000"
+            },
+            "ck": {
+              "description": "Device Clock Signal Register",
+              "addressOffset": "0x0004"
+            },
+            "oe": {
+              "description": "Device Output-Enable Signal Register",
+              "addressOffset": "0x0008"
+            },
+            "sel": {
+              "description": "Device Chip-Select Signal Register",
+              "addressOffset": "0x000C"
+            },
+            "we": {
+              "description": "Device Write-Enable Signal Register",
+              "addressOffset": "0x0010"
+            },
+            "mr": {
+              "description": "Device Mode Register",
+              "addressOffset": "0x0014"
+            },
+            "mrr": {
+              "description": "Read-Voltage Regulator Control Register",
+              "addressOffset": "0x0018"
+            },
+            "mpp": {
+              "description": "Write-Voltage Charge Pump Control Register",
+              "addressOffset": "0x001C"
+            },
+            "vrren": {
+              "description": "Read-Voltage Enable Register",
+              "addressOffset": "0x0020"
+            },
+            "vppen": {
+              "description": "Write-Voltage Enable Register",
+              "addressOffset": "0x0024"
+            },
+            "a": {
+              "description": "Device Address Register",
+              "addressOffset": "0x0028"
+            },
+            "d": {
+              "description": "Device Data Input Register",
+              "addressOffset": "0x002C"
+            },
+            "q": {
+              "description": "Device Data Output Register",
+              "addressOffset": "0x0030"
+            },
+            "rsctrl": {
+              "description": "Read Sequencer Control Register",
+              "addressOffset": "0x0034",
+              "fields": {
+                "scale": {
+                  "description": "OTP timescale",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "tas": {
+                  "description": "Address setup time",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "trp": {
+                  "description": "Read pulse time",
+                  "bitOffset": "4",
+                  "bitWidth": "1"
+                },
+                "tracc": {
+                  "description": "Read access time",
+                  "bitOffset": "5",
+                  "bitWidth": "1"
+                }
+              }
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x10012000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "8"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "9"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "10"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "11"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "12"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "13"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "14"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "15"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "16"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "17"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "18"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "19"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "20"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "21"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "22"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "23"
+            },
+            "gpio16": {
+              "description": "GPIO16 Interrupt",
+              "value": "24"
+            },
+            "gpio17": {
+              "description": "GPIO17 Interrupt",
+              "value": "25"
+            },
+            "gpio18": {
+              "description": "GPIO18 Interrupt",
+              "value": "26"
+            },
+            "gpio19": {
+              "description": "GPIO19 Interrupt",
+              "value": "27"
+            },
+            "gpio20": {
+              "description": "GPIO20 Interrupt",
+              "value": "28"
+            },
+            "gpio21": {
+              "description": "GPIO21 Interrupt",
+              "value": "29"
+            },
+            "gpio22": {
+              "description": "GPIO22 Interrupt",
+              "value": "30"
+            },
+            "gpio23": {
+              "description": "GPIO23 Interrupt",
+              "value": "31"
+            },
+            "gpio24": {
+              "description": "GPIO24 Interrupt",
+              "value": "32"
+            },
+            "gpio25": {
+              "description": "GPIO25 Interrupt",
+              "value": "33"
+            },
+            "gpio26": {
+              "description": "GPIO26 Interrupt",
+              "value": "34"
+            },
+            "gpio27": {
+              "description": "GPIO27 Interrupt",
+              "value": "35"
+            },
+            "gpio28": {
+              "description": "GPIO28 Interrupt",
+              "value": "36"
+            },
+            "gpio29": {
+              "description": "GPIO29 Interrupt",
+              "value": "37"
+            },
+            "gpio30": {
+              "description": "GPIO30 Interrupt",
+              "value": "38"
+            },
+            "gpio31": {
+              "description": "GPIO31 Interrupt",
+              "value": "39"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x10013000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "3"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x10014000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x10015000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "40"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "41"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "42"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "43"
+            }
+          }
+        },
+        "uart1": {
+          "baseAddress": "0x10023000",
+          "derivedFrom": "uart0",
+          "groupName": "uart",
+          "interrupts": {
+            "uart1": {
+              "description": "UART1 Interrupt",
+              "value": "4"
+            }
+          }
+        },
+        "spi1": {
+          "baseAddress": "0x10024000",
+          "derivedFrom": "spi0",
+          "groupName": "spi",
+          "interrupts": {
+            "spi1": {
+              "description": "SPI1 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm1": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x10025000",
+          "groupName": "pwm",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "16"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm1cmp0": {
+              "description": "PWM1 Compare 0 Interrupt",
+              "value": "44"
+            },
+            "pwm1cmp1": {
+              "description": "PWM1 Compare 1 Interrupt",
+              "value": "45"
+            },
+            "pwm1cmp2": {
+              "description": "PWM1 Compare 2 Interrupt",
+              "value": "46"
+            },
+            "pwm1cmp3": {
+              "description": "PWM1 Compare 3 Interrupt",
+              "value": "47"
+            }
+          }
+        },
+        "spi2": {
+          "baseAddress": "0x10034000",
+          "derivedFrom": "spi0",
+          "groupName": "spi",
+          "interrupts": {
+            "spi2": {
+              "description": "SPI2 Interrupt",
+              "value": "7"
+            }
+          }
+        },
+        "pwm2": {
+          "baseAddress": "0x10035000",
+          "derivedFrom": "pwm1",
+          "groupName": "pwm",
+          "interrupts": {
+            "pwm2cmp0": {
+              "description": "PWM2 Compare 0 Interrupt",
+              "value": "48"
+            },
+            "pwm2cmp1": {
+              "description": "PWM2 Compare 1 Interrupt",
+              "value": "49"
+            },
+            "pwm2cmp2": {
+              "description": "PWM2 Compare 2 Interrupt",
+              "value": "50"
+            },
+            "pwm2cmp3": {
+              "description": "PWM2 Compare 3 Interrupt",
+              "value": "51"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/FreedomStudio/HiFive1/led_fade/led_fade Debug.launch b/FreedomStudio/HiFive1/led_fade/led_fade OpenOCD.launch
index b5d18d4..6235348 100644
--- a/FreedomStudio/HiFive1/led_fade/led_fade Debug.launch
+++ b/FreedomStudio/HiFive1/led_fade/led_fade OpenOCD.launch
@@ -46,6 +46,7 @@
 <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
 <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/led_fade.elf"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="led_fade"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/fe310-xsvd.json"/>
 <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.516870870"/>
 <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">