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authorDrew Barbier <dbarbi1@gmail.com>2018-01-04 22:11:43 -0600
committerDrew Barbier <dbarbi1@gmail.com>2018-01-04 22:11:43 -0600
commite838c0ea3ec90667c0776c2e08cdc2e76d0a6e19 (patch)
tree63bf3e99e3f553ddfd1e76b257935335e4761f4a /FreedomStudio
parentde90bb286d310e375fdf16d3d06eb4ee030e2203 (diff)
E31 FS dhrystone project
Diffstat (limited to 'FreedomStudio')
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/.cproject216
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/.gitignore1
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/.project408
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/.settings/language.settings.xml25
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/dhrystone JLINK.launch80
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/dhrystone OpenOCD.launch62
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/e31arty-xsvd.json1250
-rw-r--r--FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg31
8 files changed, 2073 insertions, 0 deletions
diff --git a/FreedomStudio/E31FPGA/dhrystone/.cproject b/FreedomStudio/E31FPGA/dhrystone/.cproject
new file mode 100644
index 0000000..31822a9
--- /dev/null
+++ b/FreedomStudio/E31FPGA/dhrystone/.cproject
@@ -0,0 +1,216 @@
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+ <configuration configurationName="Debug">
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diff --git a/FreedomStudio/E31FPGA/dhrystone/.gitignore b/FreedomStudio/E31FPGA/dhrystone/.gitignore
new file mode 100644
index 0000000..3df573f
--- /dev/null
+++ b/FreedomStudio/E31FPGA/dhrystone/.gitignore
@@ -0,0 +1 @@
+/Debug/
diff --git a/FreedomStudio/E31FPGA/dhrystone/.project b/FreedomStudio/E31FPGA/dhrystone/.project
new file mode 100644
index 0000000..7d8f274
--- /dev/null
+++ b/FreedomStudio/E31FPGA/dhrystone/.project
@@ -0,0 +1,408 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>dhrystone</name>
+ <comment></comment>
+ <projects>
+ </projects>
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+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
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+ </buildCommand>
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+ <triggers>full,incremental,</triggers>
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+ </natures>
+ <linkedResources>
+ <link>
+ <name>bsp</name>
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+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>dhry.h</name>
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+ </link>
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diff --git a/FreedomStudio/E31FPGA/dhrystone/.settings/language.settings.xml b/FreedomStudio/E31FPGA/dhrystone/.settings/language.settings.xml
new file mode 100644
index 0000000..fa2c25a
--- /dev/null
+++ b/FreedomStudio/E31FPGA/dhrystone/.settings/language.settings.xml
@@ -0,0 +1,25 @@
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+ <language-scope id="org.eclipse.cdt.core.g++"/>
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+ </extension>
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diff --git a/FreedomStudio/E31FPGA/dhrystone/dhrystone JLINK.launch b/FreedomStudio/E31FPGA/dhrystone/dhrystone JLINK.launch
new file mode 100644
index 0000000..c331740
--- /dev/null
+++ b/FreedomStudio/E31FPGA/dhrystone/dhrystone JLINK.launch
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diff --git a/FreedomStudio/E31FPGA/dhrystone/dhrystone OpenOCD.launch b/FreedomStudio/E31FPGA/dhrystone/dhrystone OpenOCD.launch
new file mode 100644
index 0000000..f4ae61d
--- /dev/null
+++ b/FreedomStudio/E31FPGA/dhrystone/dhrystone OpenOCD.launch
@@ -0,0 +1,62 @@
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+</listAttribute>
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+<listEntry value="4"/>
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diff --git a/FreedomStudio/E31FPGA/dhrystone/e31arty-xsvd.json b/FreedomStudio/E31FPGA/dhrystone/e31arty-xsvd.json
new file mode 100644
index 0000000..4879d45
--- /dev/null
+++ b/FreedomStudio/E31FPGA/dhrystone/e31arty-xsvd.json
@@ -0,0 +1,1250 @@
+{
+ "schemaVersion": "0.2.4",
+ "contentVersion": "0.2.0",
+ "headerVersion": "0.2.0",
+ "device": {
+ "e31arty": {
+ "displayName": "Core Complex E31 Arty",
+ "description": "SiFive’s E31 is a synthesised version of Core Complex E31 running on the Arty board.",
+ "supplier": {
+ "name": "sifive",
+ "id": "1",
+ "displayName": "SiFive",
+ "fullName": "SiFive, Inc.",
+ "contact": "info@sifive.com"
+ },
+ "busWidth": "32",
+ "resetMask": "all",
+ "resetValue": "0x00000000",
+ "access": "rw",
+ "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E31_",
+ "headerTypePrefix": "sifive_e31arty_",
+ "headerInterruptPrefix": "sifive_e31arty_interrupt_global_",
+ "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+ "revision": "r0p0",
+ "numInterrupts": "26",
+ "priorityBits": "3",
+ "regWidth": "32",
+ "cores": {
+ "e31": {
+ "harts": "1",
+ "isa": "RV32IMAC",
+ "isaVersion": "2.2",
+ "mpu": "pmp",
+ "mmu": "none",
+ "localInterrupts": {
+ "machine_software": {
+ "description": "Machine Software Interrupt",
+ "value": "3"
+ },
+ "machine_timer": {
+ "description": "Machine Timer Interrupt",
+ "value": "7"
+ },
+ "machine_ext": {
+ "description": "Machine External Interrupt",
+ "value": "11"
+ },
+ "0": {
+ "description": "Local Interrupt 0",
+ "value": "16"
+ },
+ "1": {
+ "description": "Local Interrupt 1",
+ "value": "17"
+ },
+ "2": {
+ "description": "Local Interrupt 2",
+ "value": "18"
+ },
+ "3": {
+ "description": "Local Interrupt 3",
+ "value": "19"
+ },
+ "4": {
+ "description": "Local Interrupt 4",
+ "value": "20"
+ },
+ "5": {
+ "description": "Local Interrupt 5",
+ "value": "21"
+ },
+ "6": {
+ "description": "Local Interrupt 6",
+ "value": "22"
+ },
+ "7": {
+ "description": "Local Interrupt 7",
+ "value": "23"
+ },
+ "8": {
+ "description": "Local Interrupt 8",
+ "value": "24"
+ },
+ "9": {
+ "description": "Local Interrupt 9",
+ "value": "25"
+ },
+ "10": {
+ "description": "Local Interrupt 10",
+ "value": "26"
+ },
+ "11": {
+ "description": "Local Interrupt 11",
+ "value": "27"
+ },
+ "12": {
+ "description": "Local Interrupt 12",
+ "value": "28"
+ },
+ "13": {
+ "description": "Local Interrupt 13",
+ "value": "29"
+ },
+ "14": {
+ "description": "Local Interrupt 14",
+ "value": "30"
+ },
+ "15": {
+ "description": "Local Interrupt 15",
+ "value": "31"
+ }
+ },
+ "numLocalInterrupts": "16"
+ }
+ },
+ "peripherals": {
+ "clint": {
+ "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+ "baseAddress": "0x02000000",
+ "size": "0x10000",
+ "registers": {
+ "msip": {
+ "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+ "addressOffset": "0x0000",
+ "arraySize": "1"
+ }
+ },
+ "clusters": {
+ "mtimecmp": {
+ "description": "Machine Time Compare Registers per Hart",
+ "addressOffset": "0x4000",
+ "arraySize": "1",
+ "registers": {
+ "low": {
+ "description": "Machine Compare Register Low",
+ "addressOffset": "0x0000"
+ },
+ "high": {
+ "description": "Machine Compare Register High",
+ "addressOffset": "0x0004"
+ }
+ }
+ },
+ "mtime": {
+ "description": "Machine Time Register",
+ "addressOffset": "0xBFF8",
+ "access": "r",
+ "registers": {
+ "low": {
+ "description": "Machine Time Register Low",
+ "addressOffset": "0x0000"
+ },
+ "high": {
+ "description": "Machine Time Register High",
+ "addressOffset": "0x0004"
+ }
+ }
+ }
+ }
+ },
+ "plic": {
+ "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+ "baseAddress": "0x0C000000",
+ "size": "0x4000000",
+ "registers": {
+ "priorities": {
+ "arraySize": "27",
+ "description": "Interrupt Priorities Registers; 0 is reserved.",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority for a given global interrupt",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "pendings": {
+ "arraySize": "8",
+ "description": "Interrupt Pending Bits Registers",
+ "addressOffset": "0x1000",
+ "access": "r"
+ }
+ },
+ "clusters": {
+ "enablestarget0": {
+ "description": "Hart 0 Interrupt Enable Bits",
+ "addressOffset": "0x00002000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-mode Interrupt Enable Bits",
+ "registers": {
+ "enables": {
+ "arraySize": "8",
+ "description": "Interrupt Enable Bits Registers",
+ "addressOffset": "0x0000"
+ }
+ }
+ }
+ }
+ },
+ "target0": {
+ "description": "Hart 0 Interrupt Thresholds",
+ "addressOffset": "0x00200000",
+ "clusters": {
+ "m": {
+ "addressOffset": "0x0000",
+ "description": "Hart 0 M-Mode Interrupt Threshold",
+ "registers": {
+ "threshold": {
+ "description": "The Priority Threshold Register",
+ "addressOffset": "0x0000",
+ "fields": {
+ "value": {
+ "description": "The priority threshold value",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "claimcomplete": {
+ "description": "The Interrupt Claim/Completion Register",
+ "addressOffset": "0x0004"
+ }
+ }
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "switch0": {
+ "description": "SWITCH 0 Interrupt",
+ "value": "2"
+ },
+ "switch1": {
+ "description": "SWITCH 1 Interrupt",
+ "value": "3"
+ },
+ "switch2": {
+ "description": "SWITCH 2 Interrupt",
+ "value": "4"
+ },
+ "switch3": {
+ "description": "SWITCH 3 Interrupt",
+ "value": "5"
+ }
+ }
+ },
+ "gpio": {
+ "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+ "baseAddress": "0x20002000",
+ "size": "0x1000",
+ "registers": {
+ "value": {
+ "description": "Pin Value Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "inputen": {
+ "description": "Pin Input Enable Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Input Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outputen": {
+ "description": "Pin Output Enable Register",
+ "addressOffset": "0x008",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Output Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "port": {
+ "description": "Output Port Value Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output Port Value Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "pue": {
+ "description": "Internal Pull-up Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Internal Pull-up Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "ds": {
+ "description": "Pin Drive Strength Register",
+ "addressOffset": "0x014",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Pin Drive Strength Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseie": {
+ "description": "Rise Interrupt Enable Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "riseip": {
+ "description": "Rise Interrupt Pending Register",
+ "addressOffset": "0x01C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Rise Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallie": {
+ "description": "Fall Interrupt Enable Register",
+ "addressOffset": "0x020",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "fallip": {
+ "description": "Fall Interrupt Pending Register",
+ "addressOffset": "0x024",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Fall Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highie": {
+ "description": "High Interrupt Enable Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "highip": {
+ "description": "High Interrupt Pending Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "High Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowie": {
+ "description": "Low Interrupt Enable Register",
+ "addressOffset": "0x030",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "lowip": {
+ "description": "Low Interrupt Pending Register",
+ "addressOffset": "0x034",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Low Interrupt Pending Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofen": {
+ "description": "HW I/O Function Enable Register",
+ "addressOffset": "0x038",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Enable Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "iofsel": {
+ "description": "HW I/O Function Select Register",
+ "addressOffset": "0x03C",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "HW I/O Function Select Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ },
+ "outxor": {
+ "description": "Output XOR (invert) Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "bit": {
+ "repeatGenerator": "0-31",
+ "description": "Output XOR Bit Field",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "headerName": ""
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "gpio0": {
+ "description": "GPIO0 Interrupt",
+ "value": "7"
+ },
+ "gpio1": {
+ "description": "GPIO1 Interrupt",
+ "value": "8"
+ },
+ "gpio2": {
+ "description": "GPIO2 Interrupt",
+ "value": "9"
+ },
+ "gpio3": {
+ "description": "GPIO3 Interrupt",
+ "value": "10"
+ },
+ "gpio4": {
+ "description": "GPIO4 Interrupt",
+ "value": "11"
+ },
+ "gpio5": {
+ "description": "GPIO5 Interrupt",
+ "value": "12"
+ },
+ "gpio6": {
+ "description": "GPIO6 Interrupt",
+ "value": "13"
+ },
+ "gpio7": {
+ "description": "GPIO7 Interrupt",
+ "value": "14"
+ },
+ "gpio8": {
+ "description": "GPIO8 Interrupt",
+ "value": "15"
+ },
+ "gpio9": {
+ "description": "GPIO9 Interrupt",
+ "value": "16"
+ },
+ "gpio10": {
+ "description": "GPIO10 Interrupt",
+ "value": "17"
+ },
+ "gpio11": {
+ "description": "GPIO11 Interrupt",
+ "value": "18"
+ },
+ "gpio12": {
+ "description": "GPIO12 Interrupt",
+ "value": "19"
+ },
+ "gpio13": {
+ "description": "GPIO13 Interrupt",
+ "value": "20"
+ },
+ "gpio14": {
+ "description": "GPIO14 Interrupt",
+ "value": "21"
+ },
+ "gpio15": {
+ "description": "GPIO15 Interrupt",
+ "value": "22"
+ }
+ }
+ },
+ "uart0": {
+ "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+ "baseAddress": "0x20000000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "uart",
+ "registers": {
+ "txdata": {
+ "description": "Transmit Data Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "full": {
+ "description": "Transmit FIFO full",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Receive Data Register",
+ "addressOffset": "0x004",
+ "resetMask": "none",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "access": "r"
+ },
+ "empty": {
+ "description": "Receive FIFO empty",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txctrl": {
+ "description": "Transmit Control Register ",
+ "addressOffset": "0x008",
+ "fields": {
+ "txen": {
+ "description": "Transmit enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "nstop": {
+ "description": "Number of stop bits",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "txcnt": {
+ "description": "Transmit watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "rxctrl": {
+ "description": "Receive Control Register",
+ "addressOffset": "0x00C",
+ "fields": {
+ "rxen": {
+ "description": "Receive enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxcnt": {
+ "description": "Receive watermark level",
+ "bitOffset": "16",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x014",
+ "access": "r",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark interrupt pending",
+ "bitOffset": "0",
+ "bitWidth": "1"
+ },
+ "rxwm": {
+ "description": "Receive watermark interrupt pending",
+ "bitOffset": "1",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "div": {
+ "description": "Baud Rate Divisor Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "value": {
+ "description": "Baud rate divisor",
+ "bitOffset": "0",
+ "bitWidth": "16",
+ "resetMask": "all",
+ "resetValue": "0x0000FFFF"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "uart0": {
+ "description": "UART0 Interrupt",
+ "value": "1"
+ }
+ }
+ },
+ "spi0": {
+ "description": "Serial Peripheral Interface (SPI) Peripheral",
+ "baseAddress": "0x20004000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "spi",
+ "registers": {
+ "sckdiv": {
+ "description": "Serial clock divisor Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Divisor for serial clock",
+ "bitOffset": "0",
+ "bitWidth": "12",
+ "resetMask": "all",
+ "resetValue": "0x003"
+ }
+ }
+ },
+ "sckmode": {
+ "description": "Serial Clock Mode Register",
+ "addressOffset": "0x004",
+ "fields": {
+ "pha": {
+ "description": "Serial clock phase",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "pol": {
+ "description": "Serial clock polarity",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "csid": {
+ "description": "Chip Select ID Register",
+ "addressOffset": "0x010",
+ "resetMask": "all",
+ "resetValue": "0x00000000"
+ },
+ "csdef": {
+ "description": "Chip Select Default Register",
+ "addressOffset": "0x014",
+ "resetMask": "all",
+ "resetValue": "0x00000001"
+ },
+ "csmode": {
+ "description": "Chip Select Mode Register",
+ "addressOffset": "0x018",
+ "fields": {
+ "mode": {
+ "description": "Chip select mode",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "csmode-enum": {
+ "description": "Chip Select Modes Enumeration",
+ "values": {
+ "0": {
+ "displayName": "auto",
+ "description": "Assert/de-assert CS at the beginning/end of each frame"
+ },
+ "*": {
+ "displayName": "reserved"
+ },
+ "2": {
+ "displayName": "hold",
+ "description": "Keep CS continuously asserted after the initial frame"
+ },
+ "3": {
+ "displayName": "off",
+ "description": "Disable hardware control of the CS pin"
+ }
+ }
+ }
+ }
+ }
+ }
+ },
+ "delay0": {
+ "description": "Delay Control 0 Register",
+ "addressOffset": "0x028",
+ "fields": {
+ "cssck": {
+ "description": "CS to SCK Delay",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "sckcs": {
+ "description": "SCK to CS Delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "delay1": {
+ "description": "Delay Control 1 Register",
+ "addressOffset": "0x02C",
+ "fields": {
+ "intercs": {
+ "description": "Minimum CS inactive time",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ },
+ "interxfr": {
+ "description": "Maximum interframe delay",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x01"
+ }
+ }
+ },
+ "fmt": {
+ "description": "Frame Format Register",
+ "addressOffset": "0x040",
+ "fields": {
+ "proto": {
+ "description": "SPI Protocol",
+ "bitOffset": "0",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "proto-enum": {
+ "description": "SPI Protocol Enumeration",
+ "values": {
+ "0": {
+ "displayName": "single",
+ "description": "DQ0 (MOSI), DQ1 (MISO)"
+ },
+ "1": {
+ "displayName": "dual",
+ "description": "DQ0, DQ1"
+ },
+ "2": {
+ "displayName": "quad",
+ "description": "DQ0, DQ1, DQ2, DQ3"
+ },
+ "*": {
+ "displayName": "reserved"
+ }
+ }
+ }
+ }
+ },
+ "endian": {
+ "description": "SPI endianness",
+ "bitOffset": "2",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0",
+ "enumerations": {
+ "endian-enum": {
+ "description": "SPI Endianness Enumeration",
+ "values": {
+ "0": {
+ "displayName": "msb",
+ "description": "Transmit most-significant bit (MSB) first"
+ },
+ "1": {
+ "displayName": "lsb",
+ "description": "Transmit least-significant bit (LSB) first"
+ }
+ }
+ }
+ }
+ },
+ "dir": {
+ "description": "SPI I/O Direction",
+ "bitOffset": "3",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1",
+ "enumerations": {
+ "dir-enum": {
+ "description": "SPI I/O Direction Enumeration",
+ "values": {
+ "0": {
+ "displayName": "rx",
+ "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+ },
+ "1": {
+ "displayName": "tx",
+ "description": "The receive FIFO is not populated."
+ }
+ }
+ }
+ }
+ },
+ "len": {
+ "description": "Number of bits per frame",
+ "bitOffset": "16",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x8"
+ }
+ }
+ },
+ "txdata": {
+ "description": "Tx FIFO Data Register",
+ "addressOffset": "0x048",
+ "fields": {
+ "data": {
+ "description": "Transmit data",
+ "bitOffset": "0",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x00"
+ },
+ "full": {
+ "description": "FIFO full flag",
+ "bitOffset": "31",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ },
+ "rxdata": {
+ "description": "Rx FIFO Data Register",
+ "addressOffset": "0x04C",
+ "resetMask": "none",
+ "access": "r",
+ "fields": {
+ "data": {
+ "description": "Received data",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ },
+ "empty": {
+ "description": "FIFO empty flag",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "txmark": {
+ "description": "Tx FIFO Watermark Register",
+ "addressOffset": "0x050",
+ "fields": {
+ "value": {
+ "description": "Transmit watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "rxmark": {
+ "description": "Rx FIFO Watermark Register",
+ "addressOffset": "0x054",
+ "fields": {
+ "value": {
+ "description": "Receive watermark",
+ "bitOffset": "0",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "fctrl": {
+ "description": "Flash Interface Control Register",
+ "addressOffset": "0x060",
+ "fields": {
+ "en": {
+ "description": "SPI Flash Mode Select",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ }
+ }
+ },
+ "ffmt": {
+ "description": "Flash Instruction Format Register",
+ "addressOffset": "0x064",
+ "fields": {
+ "cmden": {
+ "description": "Enable sending of command",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x1"
+ },
+ "addrlen": {
+ "description": "Number of address bytes(0 to 4)",
+ "bitOffset": "1",
+ "bitWidth": "3",
+ "resetMask": "all",
+ "resetValue": "0x3"
+ },
+ "padcnt": {
+ "description": "Number of dummy cycles",
+ "bitOffset": "4",
+ "bitWidth": "4",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdproto": {
+ "description": "Protocol for transmitting command",
+ "bitOffset": "8",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "addrproto": {
+ "description": "Protocol for transmitting address and padding",
+ "bitOffset": "10",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "dataproto": {
+ "description": "Protocol for receiving data bytes",
+ "bitOffset": "12",
+ "bitWidth": "2",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmdcode": {
+ "description": "Value of command byte",
+ "bitOffset": "16",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x03"
+ },
+ "padcode": {
+ "description": "First 8 bits to transmit during dummy cycles",
+ "bitOffset": "24",
+ "bitWidth": "8",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ie": {
+ "description": "Interrupt Enable Register",
+ "addressOffset": "0x070",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark enable",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "rxwm": {
+ "description": "Receive watermark enable",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ }
+ }
+ },
+ "ip": {
+ "description": "Interrupt Pending Register",
+ "addressOffset": "0x074",
+ "fields": {
+ "txwm": {
+ "description": "Transmit watermark pending",
+ "bitOffset": "0",
+ "bitWidth": "1",
+ "access": "r"
+ },
+ "rxwm": {
+ "description": "Receive watermark pending",
+ "bitOffset": "1",
+ "bitWidth": "1",
+ "access": "r"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "spi0": {
+ "description": "SPI0 Interrupt",
+ "value": "6"
+ }
+ }
+ },
+ "pwm0": {
+ "description": "Pulse-Width Modulation (PWM) Peripheral",
+ "baseAddress": "0x20005000",
+ "size": "0x1000",
+ "resetMask": "none",
+ "groupName": "pwm",
+ "registers": {
+ "cfg": {
+ "description": "Configuration Register",
+ "addressOffset": "0x000",
+ "fields": {
+ "scale": {
+ "description": "Counter scale",
+ "bitOffset": "0",
+ "bitWidth": "4"
+ },
+ "sticky": {
+ "description": "Sticky - disallow clearing pwmcmpXip bits",
+ "bitOffset": "8",
+ "bitWidth": "1"
+ },
+ "zerocmp": {
+ "description": "Zero - counter resets to zero after match",
+ "bitOffset": "9",
+ "bitWidth": "1"
+ },
+ "deglitch": {
+ "description": "Deglitch - latch pwmcmpXip within same cycle",
+ "bitOffset": "10",
+ "bitWidth": "1"
+ },
+ "enalways": {
+ "description": "Enable always - run continuously",
+ "bitOffset": "12",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "enoneshot": {
+ "description": "enable one shot - run one cycle",
+ "bitOffset": "13",
+ "bitWidth": "1",
+ "resetMask": "all",
+ "resetValue": "0x0"
+ },
+ "cmp0center": {
+ "description": "PWM0 Compare Center",
+ "bitOffset": "16",
+ "bitWidth": "1"
+ },
+ "cmp1center": {
+ "description": "PWM1 Compare Center",
+ "bitOffset": "17",
+ "bitWidth": "1"
+ },
+ "cmp2center": {
+ "description": "PWM2 Compare Center",
+ "bitOffset": "18",
+ "bitWidth": "1"
+ },
+ "cmp3center": {
+ "description": "PWM3 Compare Center",
+ "bitOffset": "19",
+ "bitWidth": "1"
+ },
+ "cmp0gang": {
+ "description": "PWM0/PWM1 Compare Gang",
+ "bitOffset": "24",
+ "bitWidth": "1"
+ },
+ "cmp1gang": {
+ "description": "PWM1/PWM2 Compare Gang",
+ "bitOffset": "25",
+ "bitWidth": "1"
+ },
+ "cmp2gang": {
+ "description": "PWM2/PWM3 Compare Gang",
+ "bitOffset": "26",
+ "bitWidth": "1"
+ },
+ "cmp3gang": {
+ "description": "PWM3/PWM0 Compare Gang",
+ "bitOffset": "27",
+ "bitWidth": "1"
+ },
+ "cmp0ip": {
+ "description": "PWM0 Interrupt Pending",
+ "bitOffset": "28",
+ "bitWidth": "1"
+ },
+ "cmp1ip": {
+ "description": "PWM1 Interrupt Pending",
+ "bitOffset": "29",
+ "bitWidth": "1"
+ },
+ "cmp2ip": {
+ "description": "PWM2 Interrupt Pending",
+ "bitOffset": "30",
+ "bitWidth": "1"
+ },
+ "cmp3ip": {
+ "description": "PWM3 Interrupt Pending",
+ "bitOffset": "31",
+ "bitWidth": "1"
+ }
+ }
+ },
+ "count": {
+ "description": "Configuration Register",
+ "addressOffset": "0x008"
+ },
+ "scale": {
+ "description": "Scale Register",
+ "addressOffset": "0x010",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ },
+ "cmp": {
+ "arraySize": "4",
+ "description": "Compare Registers",
+ "addressOffset": "0x020",
+ "fields": {
+ "value": {
+ "description": "Compare value",
+ "bitOffset": "0",
+ "bitWidth": "8"
+ }
+ }
+ }
+ },
+ "interrupts": {
+ "pwm0cmp0": {
+ "description": "PWM0 Compare 0 Interrupt",
+ "value": "23"
+ },
+ "pwm0cmp1": {
+ "description": "PWM0 Compare 1 Interrupt",
+ "value": "24"
+ },
+ "pwm0cmp2": {
+ "description": "PWM0 Compare 2 Interrupt",
+ "value": "25"
+ },
+ "pwm0cmp3": {
+ "description": "PWM0 Compare 3 Interrupt",
+ "value": "26"
+ }
+ }
+ }
+ }
+ }
+ }
+} \ No newline at end of file
diff --git a/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg
new file mode 100644
index 0000000..8b382dc
--- /dev/null
+++ b/FreedomStudio/E31FPGA/dhrystone/sifive-coreplexip-e31-arty.cfg
@@ -0,0 +1,31 @@
+# JTAG adapter setup
+adapter_khz 10000
+
+interface ftdi
+ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi_vid_pid 0x15ba 0x002a
+
+ftdi_layout_init 0x0808 0x0a1b
+ftdi_layout_signal nSRST -oe 0x0200
+#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi_layout_signal LED -data 0x0800
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+# Un-comment these two flash lines if you have a SPI flash and want to write
+# it.
+flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
+init
+if {[ info exists pulse_srst]} {
+ ftdi_set_signal nSRST 0
+ ftdi_set_signal nSRST z
+}
+halt
+flash protect 0 64 last off
+echo "Ready for Remote Connections"