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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-04-30 16:59:29 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-30 16:59:29 +0000 |
| commit | 0c75c6a612a1620bf1ffe82cd5c77ef9a8369045 (patch) | |
| tree | 1a11e4304b06fbee9c0e525d81c0789530dfba35 /README.md | |
| parent | a351dc8d6aaf1a10be9a08e66c78c37126833d6a (diff) | |
| parent | 8cd756c200cb13c036115a4b851b94f686cf3a3a (diff) | |
Merge pull request #235 from sifive/u54-rtl
Add Multicore Support
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -31,6 +31,8 @@ operating systems to RISC-V. - sifive-hifive1 - SiFive HiFive 1 Rev B - sifive-hifive1-revb + - [SiFive HiFive Unleashed](https://www.sifive.com/boards/hifive-unleashed) + - sifive-hifive-unleashed - [SiFive Freedom E310 Arty](https://github.com/sifive/freedom) - freedom-e310-arty - SiFive CoreIP RTL @@ -43,6 +45,8 @@ operating systems to RISC-V. - coreip-s54-rtl - coreip-e76-rtl - coreip-s76-rtl + - coreip-u54-rtl + - coreip-u54mc-rtl - SiFive CoreIP Arty FPGA Evaluation targets - coreip-e20-arty - coreip-e21-arty |