diff options
| author | Bunnaroath Sou <35707615+bsousi5@users.noreply.github.com> | 2019-03-06 12:21:03 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-06 12:21:03 -0800 |
| commit | c71689996d85011f3d493b8cbe75e1379bdbc932 (patch) | |
| tree | e098bff2a7c45b7860173fb65c3488d8eb7f29c6 /bsp/coreip-e20-arty/README.md | |
| parent | f7601b8a833502a34047af50ebb200d543e81da7 (diff) | |
| parent | f7a18d3711b3bb04b7ed8294a0e47599ac15cf45 (diff) | |
Merge pull request #192 from sifive/arty-19.2
Update/add E20, E21, E24 arty targets for all 19.2 CoreIPs release
Diffstat (limited to 'bsp/coreip-e20-arty/README.md')
| -rw-r--r-- | bsp/coreip-e20-arty/README.md | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/bsp/coreip-e20-arty/README.md b/bsp/coreip-e20-arty/README.md new file mode 100644 index 0000000..a10a36c --- /dev/null +++ b/bsp/coreip-e20-arty/README.md @@ -0,0 +1,13 @@ +The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines. + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMC core +- 4 hardware breakpoints +- Up to 153 CLIC interrupt signals that can be connected to off core complex devices, with 16 levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches + |