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| author | Bunnaroath Sou <35707615+bsousi5@users.noreply.github.com> | 2019-03-18 15:06:06 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-18 15:06:06 -0700 |
| commit | 0f8c780d82b2ec3eda351229e79953bbde7bb95a (patch) | |
| tree | 9f9b0362f09e165cb767d3159fc9f52d6d22920c /bsp/coreip-e20-arty/design.dts | |
| parent | 732f4902aadcd5bda62c8ea0858112a06580406d (diff) | |
| parent | 44c064f651cf4756f44fb96d542a8db2d4a33471 (diff) | |
Merge pull request #202 from sifive/arty-19.2
Add ramrodata, scratchpad linker files, and correct timebase value
Diffstat (limited to 'bsp/coreip-e20-arty/design.dts')
| -rw-r--r-- | bsp/coreip-e20-arty/design.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsp/coreip-e20-arty/design.dts b/bsp/coreip-e20-arty/design.dts index b71170c..de47256 100644 --- a/bsp/coreip-e20-arty/design.dts +++ b/bsp/coreip-e20-arty/design.dts @@ -22,7 +22,7 @@ reg = <0x0>; riscv,isa = "rv32imc"; status = "okay"; - timebase-frequency = <1000000>; + timebase-frequency = <32000000>; hardware-exec-breakpoint-count = <4>; L2: interrupt-controller { #interrupt-cells = <1>; |