Update BSPs

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>

7 files changed, 23 insertions, 18 deletions

diff --git a/bsp/coreip-e20-arty/metal-inline.h b/bsp/coreip-e20-arty/metal-inline.h
index 3b9c4e5..80d673c 100644
--- a/bsp/coreip-e20-arty/metal-inline.h
+++ b/bsp/coreip-e20-arty/metal-inline.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-05-52        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
diff --git a/bsp/coreip-e20-arty/metal-platform.h b/bsp/coreip-e20-arty/metal-platform.h
index d049910..269e419 100644
--- a/bsp/coreip-e20-arty/metal-platform.h
+++ b/bsp/coreip-e20-arty/metal-platform.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-05-52        */
 /* ----------------------------------- */
 
 #ifndef COREIP_E20_ARTY__METAL_PLATFORM_H
diff --git a/bsp/coreip-e20-arty/metal.default.lds b/bsp/coreip-e20-arty/metal.default.lds
index badb729..73f7f46 100644
--- a/bsp/coreip-e20-arty/metal.default.lds
+++ b/bsp/coreip-e20-arty/metal.default.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-05-52        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 0);
 
 
 	.init 		:
diff --git a/bsp/coreip-e20-arty/metal.h b/bsp/coreip-e20-arty/metal.h
index 34014a1..6a73cba 100644
--- a/bsp/coreip-e20-arty/metal.h
+++ b/bsp/coreip-e20-arty/metal.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-05-52        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
@@ -69,18 +69,18 @@
 
 #include <metal/drivers/fixed-clock.h>
 #include <metal/memory.h>
-#include <metal/drivers/riscv,cpu.h>
+#include <metal/drivers/riscv_cpu.h>
 #include <metal/pmp.h>
-#include <metal/drivers/sifive,clic0.h>
-#include <metal/drivers/sifive,local-external-interrupts0.h>
-#include <metal/drivers/sifive,global-external-interrupts0.h>
-#include <metal/drivers/sifive,gpio0.h>
-#include <metal/drivers/sifive,gpio-buttons.h>
-#include <metal/drivers/sifive,gpio-leds.h>
-#include <metal/drivers/sifive,gpio-switches.h>
-#include <metal/drivers/sifive,spi0.h>
-#include <metal/drivers/sifive,test0.h>
-#include <metal/drivers/sifive,uart0.h>
+#include <metal/drivers/sifive_clic0.h>
+#include <metal/drivers/sifive_local-external-interrupts0.h>
+#include <metal/drivers/sifive_global-external-interrupts0.h>
+#include <metal/drivers/sifive_gpio0.h>
+#include <metal/drivers/sifive_gpio-buttons.h>
+#include <metal/drivers/sifive_gpio-leds.h>
+#include <metal/drivers/sifive_gpio-switches.h>
+#include <metal/drivers/sifive_spi0.h>
+#include <metal/drivers/sifive_test0.h>
+#include <metal/drivers/sifive_uart0.h>
 
 /* From clock@0 */
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
diff --git a/bsp/coreip-e20-arty/metal.ramrodata.lds b/bsp/coreip-e20-arty/metal.ramrodata.lds
index 5742665..a86761f 100644
--- a/bsp/coreip-e20-arty/metal.ramrodata.lds
+++ b/bsp/coreip-e20-arty/metal.ramrodata.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-05-52        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 0);
 
 
 	.init 		:
diff --git a/bsp/coreip-e20-arty/metal.scratchpad.lds b/bsp/coreip-e20-arty/metal.scratchpad.lds
index 3702a05..f672544 100644
--- a/bsp/coreip-e20-arty/metal.scratchpad.lds
+++ b/bsp/coreip-e20-arty/metal.scratchpad.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-05-52        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 0);
 
 
 	.init 		:
diff --git a/bsp/coreip-e20-arty/settings.mk b/bsp/coreip-e20-arty/settings.mk
index 9a4c6d6..7507947 100644
--- a/bsp/coreip-e20-arty/settings.mk
+++ b/bsp/coreip-e20-arty/settings.mk
@@ -1,12 +1,14 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 23-05-2019 13-29-49        #
+# [XXXXX] 28-05-2019 10-05-52        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imc
 RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
+RISCV_SERIES=sifive-2-series
 
 TARGET_TAGS=fpga openocd
 TARGET_DHRY_ITERS=20000000
+TARGET_CORE_ITERS=5000