summaryrefslogtreecommitdiff
path: root/bsp/coreip-e20-rtl
diff options
context:
space:
mode:
authorNathaniel Graff <nathaniel.graff@sifive.com>2019-04-29 14:50:24 -0700
committerNathaniel Graff <nathaniel.graff@sifive.com>2019-05-02 11:09:59 -0700
commitb555941a3d06c31e03ecf51eef608c7356bdb3b9 (patch)
tree01ff5eda110417a43bcbff9c6b76fb62a6a5191d /bsp/coreip-e20-rtl
parentf45383993efe41542c0de2ca030a1ff05f765b6e (diff)
Update BSPs for platform header
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-e20-rtl')
-rw-r--r--bsp/coreip-e20-rtl/metal-platform.h31
-rw-r--r--bsp/coreip-e20-rtl/metal.h12
2 files changed, 38 insertions, 5 deletions
diff --git a/bsp/coreip-e20-rtl/metal-platform.h b/bsp/coreip-e20-rtl/metal-platform.h
new file mode 100644
index 0000000..109562d
--- /dev/null
+++ b/bsp/coreip-e20-rtl/metal-platform.h
@@ -0,0 +1,31 @@
+#ifndef COREIP_E20_RTL__METAL_PLATFORM_H
+#define COREIP_E20_RTL__METAL_PLATFORM_H
+
+/* From interrupt_controller@2000000 */
+#define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL
+#define METAL_SIFIVE_CLIC0_2000000_SIZE 16777216UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS 48UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS 16UL
+#define METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS 2UL
+
+#define METAL_SIFIVE_CLIC0
+#define METAL_SIFIVE_CLIC0_MSIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_MTIMECMP_BASE 16384UL
+#define METAL_SIFIVE_CLIC0_MTIME 49144UL
+#define METAL_SIFIVE_CLIC0_CLICINTIP_BASE 0UL
+#define METAL_SIFIVE_CLIC0_CLICINTIE_BASE 1024UL
+#define METAL_SIFIVE_CLIC0_CLICINTCTL_BASE 2048UL
+#define METAL_SIFIVE_CLIC0_CLICCFG 3072UL
+#define METAL_SIFIVE_CLIC0_MMODE_APERTURE 8388608UL
+#define METAL_SIFIVE_CLIC0_HSMODE_APERTURE 10485760UL
+#define METAL_SIFIVE_CLIC0_SMODE_APERTURE 12582912UL
+#define METAL_SIFIVE_CLIC0_UMODE_APERTURE 14680064UL
+
+/* From teststatus@4000 */
+#define METAL_SIFIVE_TEST0_4000_BASE_ADDRESS 16384UL
+#define METAL_SIFIVE_TEST0_4000_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
+#endif /* COREIP_E20_RTL__METAL_PLATFORM_H*/
diff --git a/bsp/coreip-e20-rtl/metal.h b/bsp/coreip-e20-rtl/metal.h
index 094cb45..f031a28 100644
--- a/bsp/coreip-e20-rtl/metal.h
+++ b/bsp/coreip-e20-rtl/metal.h
@@ -3,6 +3,8 @@
#ifndef COREIP_E20_RTL__METAL_H
#define COREIP_E20_RTL__METAL_H
+#include <metal/machine/platform.h>
+
#ifdef __METAL_MACHINE_MACROS
#ifndef __METAL_CLINT_NUM_PARENTS
@@ -110,17 +112,17 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
.vtable = &__metal_driver_vtable_sifive_clic0,
.controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable,
- .control_base = 33554432UL,
- .control_size = 16777216UL,
+ .control_base = METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS,
+ .control_size = METAL_SIFIVE_CLIC0_2000000_SIZE,
.init_done = 0,
.num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
.interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
.interrupt_lines[0] = 3,
.interrupt_lines[1] = 7,
.interrupt_lines[2] = 11,
- .num_subinterrupts = 48UL,
- .num_intbits = 2UL,
- .max_levels = 16UL,
+ .num_subinterrupts = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTS,
+ .num_intbits = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMINTBITS,
+ .max_levels = METAL_SIFIVE_CLIC0_2000000_SIFIVE_NUMLEVELS,
.interrupt_controller = 1,
};