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authorBunnaroath Sou <bsou@sifive.com>2019-03-01 15:28:49 -0800
committerBunnaroath Sou <bsou@sifive.com>2019-03-01 15:28:49 -0800
commit43b6767541e6b20d7f7c2aef39b3a4748e53b6e4 (patch)
treec5dd195d26a51b2b55b91684374ab2815cdb8f4b /bsp/coreip-e20
parentfb3cddda6c0342ae6c91918e769eecafbabb55b0 (diff)
Update CoreIPs E20, E21, E31 and E24 for 19.2 rel
Diffstat (limited to 'bsp/coreip-e20')
-rw-r--r--bsp/coreip-e20/design.dts32
-rw-r--r--bsp/coreip-e20/metal.h11
2 files changed, 12 insertions, 31 deletions
diff --git a/bsp/coreip-e20/design.dts b/bsp/coreip-e20/design.dts
index f3c25a5..d57c342 100644
--- a/bsp/coreip-e20/design.dts
+++ b/bsp/coreip-e20/design.dts
@@ -5,10 +5,10 @@
#size-cells = <1>;
compatible = "SiFive,FE200G-dev", "fe200-dev", "sifive-dev";
model = "SiFive,FE200G";
- L11: cpus {
+ L10: cpus {
#address-cells = <1>;
#size-cells = <0>;
- L4: cpu@0 {
+ L3: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,caboose0", "riscv";
device_type = "cpu";
@@ -17,55 +17,47 @@
status = "okay";
timebase-frequency = <1000000>;
hardware-exec-breakpoint-count = <4>;
- L3: interrupt-controller {
+ L2: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
- L10: soc {
+ L9: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "SiFive,FE200G-soc", "fe200-soc", "sifive-soc", "simple-bus";
ranges;
- pmp: pmp@0 {
- compatible = "riscv,pmp";
- regions = <8>;
- };
- L8: ahb-sys-port@20000000 {
+ L7: ahb-sys-port@20000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sifive,ahb-sys-port", "sifive,ahb-port", "sifive,sys-port", "simple-bus";
ranges = <0x20000000 0x20000000 0x20000000>;
};
- L2: debug-controller@0 {
+ L1: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
- interrupts-extended = <&L3 65535>;
+ interrupts-extended = <&L2 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
- L0: error-device@3000 {
- compatible = "sifive,error0";
- reg = <0x3000 0x1000>;
- };
- L1: interrupt-controller@2000000 {
+ L0: interrupt-controller@2000000 {
#interrupt-cells = <1>;
compatible = "sifive,clic0";
interrupt-controller;
- interrupts-extended = <&L3 3 &L3 7 &L3 11>;
+ interrupts-extended = <&L2 3 &L2 7 &L2 11>;
reg = <0x2000000 0x1000000>;
reg-names = "control";
sifive,numints = <48>;
sifive,numlevels = <16>;
sifive,numintbits = <2>;
};
- L7: local-external-interrupts-0 {
+ L6: local-external-interrupts-0 {
compatible = "sifive,local-external-interrupts0";
- interrupt-parent = <&L1>;
+ interrupt-parent = <&L0>;
interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
};
- L5: teststatus@4000 {
+ L4: teststatus@4000 {
compatible = "sifive,test0";
reg = <0x4000 0x1000>;
reg-names = "control";
diff --git a/bsp/coreip-e20/metal.h b/bsp/coreip-e20/metal.h
index e132a8e..5693e03 100644
--- a/bsp/coreip-e20/metal.h
+++ b/bsp/coreip-e20/metal.h
@@ -49,9 +49,6 @@ struct __metal_driver_cpu __metal_dt_cpu_0;
asm (".weak __metal_dt_interrupt_controller");
struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller;
-asm (".weak __metal_dt_pmp_0");
-struct metal_pmp __metal_dt_pmp_0;
-
/* From interrupt_controller@2000000 */
asm (".weak __metal_dt_interrupt_controller_2000000");
struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000;
@@ -81,11 +78,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = {
.interrupt_controller = 1,
};
-/* From pmp@0 */
-struct metal_pmp __metal_dt_pmp_0 = {
- .num_regions = 8UL,
-};
-
/* From interrupt_controller@2000000 */
struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
.vtable = &__metal_driver_vtable_sifive_clic0,
@@ -171,9 +163,6 @@ struct __metal_driver_cpu *__metal_cpu_table[] = {
#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller)
-/* From pmp@0 */
-#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0)
-
/* From interrupt_controller@2000000 */
#define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller)