diff options
| author | Bunnaroath Sou <bsou@sifive.com> | 2019-02-25 18:57:35 -0800 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-02-25 18:57:35 -0800 |
| commit | e18401806b38ca0f60394780191df4b72cb2f88a (patch) | |
| tree | 50c31a3efbe1f1acce3aeec706c0d8d1227c0964 /bsp/coreip-e20 | |
| parent | bbea559f684a5eee7df45429ed55d41330f44474 (diff) | |
Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty
Diffstat (limited to 'bsp/coreip-e20')
| -rw-r--r-- | bsp/coreip-e20/README.md | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/bsp/coreip-e20/README.md b/bsp/coreip-e20/README.md new file mode 100644 index 0000000..5e19221 --- /dev/null +++ b/bsp/coreip-e20/README.md @@ -0,0 +1,6 @@ +The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 4 regions |