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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-04-11 21:40:27 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-11 21:40:27 +0000 |
| commit | b47459592db6ee7aef2a86b2010d05b8ced7eba9 (patch) | |
| tree | d1c07a9437495210ae266766f6988c0e0bceba17 /bsp/coreip-e21-arty/design.dts | |
| parent | a4d97b7aec6eb939eb1f61883591ba5cc58be258 (diff) | |
| parent | 45a50ed76caa304ba112a312d8309a625be64b7a (diff) | |
Merge pull request #233 from sifive/7-series-pmp
Add PMP nodes to all targets except e20
Diffstat (limited to 'bsp/coreip-e21-arty/design.dts')
| -rw-r--r-- | bsp/coreip-e21-arty/design.dts | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/bsp/coreip-e21-arty/design.dts b/bsp/coreip-e21-arty/design.dts index 6ac4e18..7303568 100644 --- a/bsp/coreip-e21-arty/design.dts +++ b/bsp/coreip-e21-arty/design.dts @@ -36,6 +36,10 @@ #size-cells = <1>; compatible = "SiFive,FE210G-soc", "fe210-soc", "sifive-soc", "simple-bus"; ranges; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <4>; + }; hfclk: clock@0 { #clock-cells = <0>; compatible = "fixed-clock"; |