diff options
| author | hsiang-chia.huang <hsiangchia.huang@sifive.com> | 2019-05-24 10:22:08 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-24 10:22:08 +0800 |
| commit | faf58a49c3b6421107ada0e8af43170a5ffafcea (patch) | |
| tree | 3996d52a748ae2420b5c9c6c9efe4158d5dece53 /bsp/coreip-e21-arty/design.dts | |
| parent | 7817c5e85cb6f9f6d5b98f6702fa4b7d1fb99e02 (diff) | |
| parent | 2c0269905929128bd0bd13a55ae3d8afd60a1af6 (diff) | |
Merge branch 'development-19.05' into dhrystone_19.05
Diffstat (limited to 'bsp/coreip-e21-arty/design.dts')
| -rw-r--r-- | bsp/coreip-e21-arty/design.dts | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/bsp/coreip-e21-arty/design.dts b/bsp/coreip-e21-arty/design.dts index 7303568..40f61d0 100644 --- a/bsp/coreip-e21-arty/design.dts +++ b/bsp/coreip-e21-arty/design.dts @@ -21,6 +21,7 @@ device_type = "cpu"; reg = <0x0>; riscv,isa = "rv32imac"; + riscv,pmpregions = <4>; status = "okay"; timebase-frequency = <32000000>; hardware-exec-breakpoint-count = <4>; @@ -36,10 +37,6 @@ #size-cells = <1>; compatible = "SiFive,FE210G-soc", "fe210-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <4>; - }; hfclk: clock@0 { #clock-cells = <0>; compatible = "fixed-clock"; |