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| author | Bunnaroath Sou <35707615+bsousi5@users.noreply.github.com> | 2019-03-06 12:21:03 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-06 12:21:03 -0800 |
| commit | c71689996d85011f3d493b8cbe75e1379bdbc932 (patch) | |
| tree | e098bff2a7c45b7860173fb65c3488d8eb7f29c6 /bsp/coreip-e21-arty/openocd.cfg | |
| parent | f7601b8a833502a34047af50ebb200d543e81da7 (diff) | |
| parent | f7a18d3711b3bb04b7ed8294a0e47599ac15cf45 (diff) | |
Merge pull request #192 from sifive/arty-19.2
Update/add E20, E21, E24 arty targets for all 19.2 CoreIPs release
Diffstat (limited to 'bsp/coreip-e21-arty/openocd.cfg')
| -rw-r--r-- | bsp/coreip-e21-arty/openocd.cfg | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/bsp/coreip-e21-arty/openocd.cfg b/bsp/coreip-e21-arty/openocd.cfg new file mode 100644 index 0000000..34b9f88 --- /dev/null +++ b/bsp/coreip-e21-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x40000000 0 0 0 $_TARGETNAME 0x20004000 +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off |