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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-07 11:28:06 -0800 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-03-07 14:45:59 -0800 |
| commit | 983a630b07f08af869adc78cb37bf634389519af (patch) | |
| tree | fccb6fa1d7c2c065642cb21cc4d421e3ae8206eb /bsp/coreip-e21-rtl/README.md | |
| parent | c6c0fbf23d1fc8aa9b99eae19b6e3741c8d51548 (diff) | |
Rename coreip-X to coreip-X-rtl
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-e21-rtl/README.md')
| -rw-r--r-- | bsp/coreip-e21-rtl/README.md | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/bsp/coreip-e21-rtl/README.md b/bsp/coreip-e21-rtl/README.md new file mode 100644 index 0000000..6b74a44 --- /dev/null +++ b/bsp/coreip-e21-rtl/README.md @@ -0,0 +1,7 @@ +The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 4 regions |