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| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-22 17:53:09 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-22 17:53:09 +0000 |
| commit | 44deff8b8d615721c11ab5f408da73030b01d0f9 (patch) | |
| tree | 34cd2bb52009a596dc8de95bf2b7262f5a6ce3f9 /bsp/coreip-e21-rtl/design.dts | |
| parent | 9946f2062837098088e4c9701614a2eeffaa921b (diff) | |
| parent | c5dd42c68d030a356c85bb8d174296b4f2df615d (diff) | |
Merge pull request #254 from sifive/dts-pmpregions
Update to new-style riscv,pmpregions property
Diffstat (limited to 'bsp/coreip-e21-rtl/design.dts')
| -rw-r--r-- | bsp/coreip-e21-rtl/design.dts | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/bsp/coreip-e21-rtl/design.dts b/bsp/coreip-e21-rtl/design.dts index 9e846c0..ed9fa86 100644 --- a/bsp/coreip-e21-rtl/design.dts +++ b/bsp/coreip-e21-rtl/design.dts @@ -14,6 +14,7 @@ device_type = "cpu"; reg = <0x0>; riscv,isa = "rv32imac"; + riscv,pmpregions = <4>; status = "okay"; timebase-frequency = <1000000>; hardware-exec-breakpoint-count = <4>; @@ -29,10 +30,6 @@ #size-cells = <1>; compatible = "SiFive,FE210G-soc", "fe210-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L11: ahb-periph-port@20000000 { #address-cells = <1>; #size-cells = <1>; |