Update BSPs for Unleashed and U54(MC)

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>

4 files changed, 67 insertions, 16 deletions

diff --git a/bsp/coreip-e21-rtl/metal.default.lds b/bsp/coreip-e21-rtl/metal.default.lds
index a17a5f1..a3c999a 100644
--- a/bsp/coreip-e21-rtl/metal.default.lds
+++ b/bsp/coreip-e21-rtl/metal.default.lds
@@ -21,6 +21,7 @@ PHDRS
 SECTIONS
 {
 	__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
+	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 
 
@@ -217,7 +218,6 @@ SECTIONS
 	{
 		PROVIDE( metal_segment_heap_target_start = . );
 		. = __heap_size;
-		. = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram);
 		PROVIDE( metal_segment_heap_target_end = . );
 		PROVIDE( _heap_end = . );
 	} >ram AT>ram :ram
diff --git a/bsp/coreip-e21-rtl/metal.h b/bsp/coreip-e21-rtl/metal.h
index 349fdc6..7f017fd 100644
--- a/bsp/coreip-e21-rtl/metal.h
+++ b/bsp/coreip-e21-rtl/metal.h
@@ -5,9 +5,15 @@
 
 #ifdef __METAL_MACHINE_MACROS
 
+#ifndef __METAL_CLINT_NUM_PARENTS
+#define __METAL_CLINT_NUM_PARENTS 0
+#endif
 #ifndef __METAL_PLIC_SUBINTERRUPTS
 #define __METAL_PLIC_SUBINTERRUPTS 0
 #endif
+#ifndef __METAL_PLIC_NUM_PARENTS
+#define __METAL_PLIC_NUM_PARENTS 0
+#endif
 #define __METAL_CLIC_SUBINTERRUPTS 143
 
 #ifndef __METAL_CLIC_SUBINTERRUPTS
@@ -18,9 +24,13 @@
 
 #define METAL_MAX_CLINT_INTERRUPTS 0
 
+#define __METAL_CLINT_NUM_PARENTS 0
+
 #define __METAL_PLIC_SUBINTERRUPTS 0
 #define METAL_MAX_PLIC_INTERRUPTS 0
 
+#define __METAL_PLIC_NUM_PARENTS 0
+
 #define __METAL_INTERRUPT_CONTROLLER_2000000_INTERRUPTS 3
 
 #define __METAL_CLIC_SUBINTERRUPTS 143
@@ -39,19 +49,28 @@
 
 
 #include <metal/drivers/fixed-clock.h>
+#include <metal/memory.h>
 #include <metal/drivers/riscv,cpu.h>
 #include <metal/pmp.h>
 #include <metal/drivers/sifive,clic0.h>
 #include <metal/drivers/sifive,local-external-interrupts0.h>
 #include <metal/drivers/sifive,test0.h>
 
+asm (".weak __metal_dt_mem_sys_sram_0_80000000");
+struct metal_memory __metal_dt_mem_sys_sram_0_80000000;
+
+asm (".weak __metal_dt_mem_sys_sram_1_80008000");
+struct metal_memory __metal_dt_mem_sys_sram_1_80008000;
+
+asm (".weak __metal_dt_mem_testram_20000000");
+struct metal_memory __metal_dt_mem_testram_20000000;
+
 /* From cpu@0 */
 asm (".weak __metal_dt_cpu_0");
 struct __metal_driver_cpu __metal_dt_cpu_0;
 
-/* From interrupt_controller */
-asm (".weak __metal_dt_interrupt_controller");
-struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller;
+asm (".weak __metal_dt_cpu_0_interrupt_controller");
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller;
 
 asm (".weak __metal_dt_pmp_0");
 struct metal_pmp __metal_dt_pmp_0;
@@ -69,16 +88,49 @@ asm (".weak __metal_dt_teststatus_4000");
 struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000;
 
 
+struct metal_memory __metal_dt_mem_sys_sram_0_80000000 = {
+    ._base_address = 2147483648UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_sys_sram_1_80008000 = {
+    ._base_address = 2147516416UL,
+    ._size = 32768UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
+struct metal_memory __metal_dt_mem_testram_20000000 = {
+    ._base_address = 536870912UL,
+    ._size = 134217728UL,
+    ._attrs = {
+        .R = 1,
+        .W = 1,
+        .X = 1,
+        .C = 1,
+        .A = 1},
+};
+
 /* From cpu@0 */
 struct __metal_driver_cpu __metal_dt_cpu_0 = {
     .vtable = &__metal_driver_vtable_cpu,
     .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable,
     .timebase = 1000000UL,
-    .interrupt_controller = &__metal_dt_interrupt_controller.controller,
+    .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller,
 };
 
 /* From interrupt_controller */
-struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = {
+struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = {
     .vtable = &__metal_driver_vtable_riscv_cpu_intc,
     .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable,
     .init_done = 0,
@@ -98,7 +150,7 @@ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = {
     .control_size = 16777216UL,
     .init_done = 0,
     .num_interrupts = METAL_MAX_CLIC_INTERRUPTS,
-    .interrupt_parent = &__metal_dt_interrupt_controller.controller,
+    .interrupt_parent = &__metal_dt_cpu_0_interrupt_controller.controller,
     .interrupt_lines[0] = 3,
     .interrupt_lines[1] = 7,
     .interrupt_lines[2] = 11,
@@ -254,10 +306,13 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = {
 };
 
 
-/* From cpu@0 */
-#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu)
+#define __METAL_DT_MAX_MEMORIES 3
 
-#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu)
+asm (".weak __metal_memory_table");
+struct metal_memory *__metal_memory_table[] = {
+					&__metal_dt_mem_sys_sram_0_80000000,
+					&__metal_dt_mem_sys_sram_1_80008000,
+					&__metal_dt_mem_testram_20000000};
 
 #define __METAL_DT_MAX_HARTS 1
 
@@ -265,11 +320,6 @@ asm (".weak __metal_cpu_table");
 struct __metal_driver_cpu *__metal_cpu_table[] = {
 					&__metal_dt_cpu_0};
 
-/* From interrupt_controller */
-#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller)
-
-#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller)
-
 /* From pmp@0 */
 #define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0)
 
diff --git a/bsp/coreip-e21-rtl/metal.ramrodata.lds b/bsp/coreip-e21-rtl/metal.ramrodata.lds
index cb1ac45..b8f126d 100644
--- a/bsp/coreip-e21-rtl/metal.ramrodata.lds
+++ b/bsp/coreip-e21-rtl/metal.ramrodata.lds
@@ -21,6 +21,7 @@ PHDRS
 SECTIONS
 {
 	__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
+	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 
 
@@ -218,7 +219,6 @@ SECTIONS
 	{
 		PROVIDE( metal_segment_heap_target_start = . );
 		. = __heap_size;
-		. = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram);
 		PROVIDE( metal_segment_heap_target_end = . );
 		PROVIDE( _heap_end = . );
 	} >ram AT>ram :ram
diff --git a/bsp/coreip-e21-rtl/metal.scratchpad.lds b/bsp/coreip-e21-rtl/metal.scratchpad.lds
index cb5d41c..44ced9a 100644
--- a/bsp/coreip-e21-rtl/metal.scratchpad.lds
+++ b/bsp/coreip-e21-rtl/metal.scratchpad.lds
@@ -21,6 +21,7 @@ PHDRS
 SECTIONS
 {
 	__stack_size = DEFINED(__stack_size) ? __stack_size : 0x400;
+	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;