Merge pull request #197 from sifive/rename-rtl-targets

Rename coreip-X to coreip-X-rtl

1 files changed, 0 insertions, 96 deletions

diff --git a/bsp/coreip-e21/design.dts b/bsp/coreip-e21/design.dts
deleted file mode 100644
index 9e846c0..0000000
--- a/bsp/coreip-e21/design.dts
+++ /dev/null
@@ -1,96 +0,0 @@
-/dts-v1/;
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	compatible = "SiFive,FE210G-dev", "fe210-dev", "sifive-dev";
-	model = "SiFive,FE210G";
-	L14: cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		L4: cpu@0 {
-			clock-frequency = <0>;
-			compatible = "sifive,caboose0", "riscv";
-			device_type = "cpu";
-			reg = <0x0>;
-			riscv,isa = "rv32imac";
-			status = "okay";
-			timebase-frequency = <1000000>;
-                        hardware-exec-breakpoint-count = <4>;
-			L3: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-	};
-	L13: soc {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "SiFive,FE210G-soc", "fe210-soc", "sifive-soc", "simple-bus";
-		ranges;
- 		pmp: pmp@0 {
- 			compatible = "riscv,pmp";
- 			regions = <8>;
- 		};
-		L11: ahb-periph-port@20000000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "sifive,ahb-periph-port", "sifive,ahb-port", "sifive,periph-port", "simple-bus";
-			ranges = <0x20000000 0x20000000 0x20000000>;
-		};
-		L10: ahb-sys-port@40000000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "sifive,ahb-sys-port", "sifive,ahb-port", "sifive,sys-port", "simple-bus";
-			ranges = <0x40000000 0x40000000 0x20000000>;
-		};
-		L2: debug-controller@0 {
-			compatible = "sifive,debug-013", "riscv,debug-013";
-			interrupts-extended = <&L3 65535>;
-			reg = <0x0 0x1000>;
-			reg-names = "control";
-		};
-		L0: error-device@3000 {
-			compatible = "sifive,error0";
-			reg = <0x3000 0x1000>;
-		};
-		L1: interrupt-controller@2000000 {
-			#interrupt-cells = <1>;
-			compatible = "sifive,clic0";
-			interrupt-controller;
-			interrupts-extended = <&L3 3 &L3 7 &L3 11>;
-			reg = <0x2000000 0x1000000>;
-			reg-names = "control";
-			sifive,numints = <143>;
-			sifive,numlevels = <16>;
-                        sifive,numintbits = <2>;
-		};
-		L9: local-external-interrupts-0 {
-                        compatible = "sifive,local-external-interrupts0";
-			interrupt-parent = <&L1>;
-			interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126>;
-		};
-		L6: sys-sram-0@80000000 {
-			compatible = "sifive,sram0";
-			reg = <0x80000000 0x8000>;
-			reg-names = "mem";
-		};
-		L7: sys-sram-1@80008000 {
-			compatible = "sifive,sram0";
-			reg = <0x80008000 0x8000>;
-			reg-names = "mem";
-		};
-		L5: teststatus@4000 {
-			compatible = "sifive,test0";
-			reg = <0x4000 0x1000>;
-			reg-names = "control";
-		};
- 		test_memory: testram@20000000 {
- 			compatible = "sifive,testram0";
- 			reg = <0x20000000 0x8000000>;
- 			reg-names = "mem";
- 			word-size-bytes = <4>;
-		};
-	};
-};