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authorBunnaroath Sou <35707615+bsousi5@users.noreply.github.com>2019-03-02 09:18:48 -0800
committerGitHub <noreply@github.com>2019-03-02 09:18:48 -0800
commit13bc9767e23880849142526638a7d4a1110e5a4c (patch)
tree2efee76ed7a719364fc916307aacf8a44927c005 /bsp/coreip-e21
parentfb3cddda6c0342ae6c91918e769eecafbabb55b0 (diff)
parent3cd57c399b080cc3eee813c339258fbb287bf95e (diff)
Merge pull request #186 from sifive/coreip-19.2
Update BSP for 19.2 coreip release
Diffstat (limited to 'bsp/coreip-e21')
-rw-r--r--bsp/coreip-e21/README.md2
-rw-r--r--bsp/coreip-e21/design.dts4
2 files changed, 3 insertions, 3 deletions
diff --git a/bsp/coreip-e21/README.md b/bsp/coreip-e21/README.md
index a2f1a61..6b74a44 100644
--- a/bsp/coreip-e21/README.md
+++ b/bsp/coreip-e21/README.md
@@ -4,4 +4,4 @@ This core target is suitable with Verilog RTL for verification and running appli
- 1 hart with RV32IMAC core
- 4 hardware breakpoints
-- Physical Mempory Protectin with 4 regions
+- Physical Memory Protection with 4 regions
diff --git a/bsp/coreip-e21/design.dts b/bsp/coreip-e21/design.dts
index 4cd74ef..9e846c0 100644
--- a/bsp/coreip-e21/design.dts
+++ b/bsp/coreip-e21/design.dts
@@ -71,12 +71,12 @@
interrupt-parent = <&L1>;
interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126>;
};
- L6: sys-sram@80000000 {
+ L6: sys-sram-0@80000000 {
compatible = "sifive,sram0";
reg = <0x80000000 0x8000>;
reg-names = "mem";
};
- L7: sys-sram@80008000 {
+ L7: sys-sram-1@80008000 {
compatible = "sifive,sram0";
reg = <0x80008000 0x8000>;
reg-names = "mem";