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authorBunnaroath Sou <bsou@sifive.com>2019-02-27 15:26:41 -0800
committerBunnaroath Sou <bsou@sifive.com>2019-02-27 15:26:41 -0800
commit7570a33f98d1980b9bc9e799b0b202fde2cda1ce (patch)
tree5755c5c187cced4e33f6661b46a47c3b2bb44433 /bsp/coreip-e21
parent01767ffd966798887ea3719fd51adb8c606710e8 (diff)
parent2ee3eec227ca11e0355358aa553b4618fff50bd9 (diff)
Merge branch 'e-series' of github.com:sifive/freedom-e-sdk into e-series
Diffstat (limited to 'bsp/coreip-e21')
-rw-r--r--bsp/coreip-e21/README.md7
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diff --git a/bsp/coreip-e21/README.md b/bsp/coreip-e21/README.md
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--- a/bsp/coreip-e21/README.md
+++ b/bsp/coreip-e21/README.md
@@ -1,6 +1,7 @@
The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements.
This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports:
- - 1 hart with RV32IMAC core
- - 4 hardware breakpoints
- - Physical Mempory Protectin with 4 regions
+
+- 1 hart with RV32IMAC core
+- 4 hardware breakpoints
+- Physical Mempory Protectin with 4 regions